阅读说明：本技术 逆变器装置及其控制方法 (Inverter device and control method thereof ) 是由 林巧仟 杨永盛 于 2018-07-27 设计创作，主要内容包括：本发明公开了一种逆变器装置及其控制方法,逆变器装置包含第一开关、第二开关、第三开关、第四开关、负载检知单元及控制单元。第一开关与第四开关形成第一开关组,第二开关与第三开关形成第二开关组。控制单元选择控制模式为第一开关组的两开关皆无关断,且第二开关组的至少一开关为关断,或者第二开关组的两开关皆无关断,且第一开关组的至少一开关为关断,或者第一开关组的两开关及第二开关组的两开关皆无关断。(The invention discloses an inverter device and a control method thereof. The first switch and the fourth switch form a first switch group, and the second switch and the third switch form a second switch group. The control unit selects the control mode that both the switches of the first switch group are not turned off, and at least one switch of the second switch group is turned off, or both the switches of the second switch group are not turned off, and at least one switch of the first switch group is turned off, or both the switches of the first switch group and the switches of the second switch group are not turned off.)

1. An inverter device for converting a dc input voltage to an ac output voltage to power a load, the inverter device comprising:

the first switch and the fourth switch form a first switch group, and the second switch and the third switch form a second switch group;

a load detection unit for detecting the operation state of the load to provide a load signal; and

a control unit for receiving the load signal and providing a plurality of control signals to correspondingly control the switches;

the control unit selects a control mode according to the load signal, wherein the control mode is that both the switches of the first switch set are not disconnected, at least one switch of the second switch set is disconnected, or both the switches of the second switch set are not disconnected, at least one switch of the first switch set is disconnected, or both the switches of the first switch set and the switches of the second switch set are not disconnected.

2. The inverter apparatus of claim 1, wherein one of the control modes is that both switches of the first switch set are high frequency switched and both switches of the second switch set are off, or that both switches of the second switch set are high frequency switched and both switches of the first switch set are off.

3. The inverter of claim 1, wherein one of the control modes is that both switches of the first switch set are high frequency switched and one of the switches of the second switch set is off and the other switch is high frequency switched, or that both switches of the second switch set are high frequency switched and one of the switches of the first switch set is off and the other switch is high frequency switched.

4. The inverter apparatus of claim 1, wherein one of the control modes is that both switches of the first switch set and both switches of the second switch set are high frequency switched.

5. The inverter of claim 1, wherein one of the control modes is that one of the switches of the first switch set is high frequency switched and the other switch is low frequency switched and both switches of the second switch set are off, or that one of the switches of the second switch set is high frequency switched and the other switch is low frequency switched and both switches of the first switch set are off.

6. The inverter of claim 1, wherein one of the control modes is that one of the switches of the first switch set is high frequency switched and the other switch is low frequency switched and one of the switches of the second switch set is off and the other switch is high frequency switched, or one of the switches of the second switch set is high frequency switched and the other switch is low frequency switched and one of the switches of the first switch set is off and the other switch is high frequency switched.

7. The inverter apparatus of claim 1, wherein the first switch and the second switch form a first switch leg, and the third switch and the fourth switch form a second switch leg; the first switch bridge arm is coupled with the second switch bridge arm in parallel; the alternating current output voltage is provided between the connection point of the first switch and the second switch and the connection point of the third switch and the fourth switch.

8. The inverter apparatus of claim 1, further comprising:

one end of the diode bridge arm is coupled with the connection points of the first switch and the fourth switch, and the other end of the diode bridge arm is coupled with the connection points of the second switch and the third switch;

the AC output voltage is provided between the connection point of the second switch and the fourth switch and a grounding point.

9. The inverter apparatus of claim 1, wherein the first switch and the second switch form a first switch leg, and the third switch and the fourth switch form a second switch leg; the first switch bridge arm is coupled with the second switch bridge arm; the AC output voltage is provided between the connection points of the first switch, the second switch and the third switch and a grounding point.

10. A control method of an inverter device, the inverter device converting a DC input voltage into an AC output voltage to supply power to a load, the inverter device comprising a first switch, a second switch, a third switch and a fourth switch, wherein the first switch and the fourth switch form a first switch group, the second switch and the third switch form a second switch group, the control method of the inverter device comprising:

(a) detecting the operating state of the load to provide a load signal;

(b) receiving the load signal and providing a plurality of control signals to correspondingly control the switches; and

(c) and selecting a control mode to control both the switches of the first switch group to be not disconnected and at least one switch of the second switch group to be disconnected according to the load signal, or controlling both the switches of the second switch group to be not disconnected and at least one switch of the first switch group to be disconnected, or controlling both the switches of the first switch group and both the switches of the second switch group to be not disconnected.

11. The method of controlling an inverter apparatus according to claim 10, wherein one of the control modes of step (c) comprises:

controlling the two switches of the first switch set to be switched at high frequency and the two switches of the second switch set to be switched off, or controlling the two switches of the second switch set to be switched at high frequency and the two switches of the first switch set to be switched off.

12. The method of controlling an inverter apparatus according to claim 10, wherein one of the control modes of step (c) comprises:

the two switches of the first switch set are controlled to be switched at high frequency, one switch of the second switch set is switched off, and the other switch of the second switch set is controlled to be switched at high frequency, or the two switches of the second switch set are controlled to be switched at high frequency, one switch of the first switch set is switched off, and the other switch of the first switch set is switched at high frequency.

13. The method of controlling an inverter apparatus according to claim 10, wherein one of the control modes of step (c) comprises:

controlling the two switches of the first switch group and the two switches of the second switch group to be switched at high frequency.

14. The method of controlling an inverter apparatus according to claim 10, wherein one of the control modes of step (c) comprises:

and controlling one switch of the first switch group to be switched at a high frequency, controlling the other switch to be switched at a low frequency, and controlling the two switches of the second switch group to be switched off, or controlling one switch of the second switch group to be switched at a high frequency, controlling the other switch to be switched at a low frequency, and controlling the two switches of the first switch group to be switched off.

15. The method of controlling an inverter apparatus according to claim 10, wherein one of the control modes of step (c) comprises:

and controlling one switch of the first switch group to be switched at a high frequency, controlling the other switch of the first switch group to be switched at a low frequency, and controlling one switch of the second switch group to be switched off and the other switch of the second switch group to be switched at a high frequency, or controlling one switch of the second switch group to be switched at a high frequency, and controlling the other switch of the second switch group to be switched at a low frequency, and controlling one switch of the first switch group to be switched off and the other switch of the first switch group to be switched at a high frequency.

Technical Field

The present invention relates to an inverter apparatus and a control method thereof, and more particularly, to an inverter apparatus and a control method thereof capable of providing different modulation controls based on a load operation state.

Background

The driving control of a conventional inverter is usually realized by using a pulse-width modulation (PWM) signal generated by a modulation signal (modulating signal) and a carrier signal (carrier signal).

Although the PWM control method can improve the efficiency of the inverter, the conventional driving control of the inverter usually only provides high frequency switching to the switching elements of the inverter through a single PWM modulation method, and if interactive (switching) control of different PWM modulation methods is provided according to different load operation states, the inverter needs to be improved through a complicated PWM control method, or even through additional feedback control, so that the conventional driving control of the inverter cannot meet the requirements of maintaining high efficiency and good total harmonic distortion (THD%) in a full load range in an economical and simpler manner. Accordingly, the switching device cannot be selected for the specification reduction, which not only makes the circuit design lack flexibility and freedom, but also cannot reduce the circuit cost.

Disclosure of Invention

The invention aims to provide an inverter device, which solves the problems that the switching loss of a switch cannot be effectively reduced and the overall efficiency cannot be improved.

To achieve the above objective, the present invention provides an inverter device for converting a dc input voltage into an ac output voltage to power a load. The inverter device comprises a first switch, a second switch, a third switch, a fourth switch, a load detection unit and a control unit. The first switch and the fourth switch form a first switch group, and the second switch and the third switch form a second switch group. The load detection unit detects an operation state of the load to provide a load signal. The control unit receives the load signal and provides a plurality of control signals to correspondingly control the switch. The control unit selects a control mode according to the load signal, wherein the control mode is that both the switches of the first switch group are not turned off, and at least one switch of the second switch group is turned off, or both the switches of the second switch group are not turned off, and at least one switch of the first switch group is turned off, or both the switches of the first switch group and the switches of the second switch group are not turned off.

By the inverter device, the switching loss of the switch can be effectively reduced, the overall efficiency is improved, and the requirement of low total harmonic distortion of the output of the inverter device is maintained.

Another object of the present invention is to provide a method for controlling an inverter device, which solves the problem that the switching loss of the switch cannot be effectively reduced, so that the overall efficiency cannot be improved.

To achieve the above objective, the present invention provides a control method for an inverter device, which converts a dc input voltage into an ac output voltage to supply power to a load. The inverter device comprises a first switch, a second switch, a third switch and a fourth switch, wherein the first switch and the fourth switch form a first switch group, and the second switch and the third switch form a second switch group. The control method of the inverter device comprises the following steps: (a) detecting the operating state of the load to provide a load signal; (b) receiving a load signal and providing a plurality of control signals to correspondingly control the switch; (c) and selecting the control mode to control the two switches of the first switch group to be not turned off and at least one switch of the second switch group to be turned off according to the load signal, or controlling the two switches of the second switch group to be not turned off and at least one switch of the first switch group to be turned off, or controlling the two switches of the first switch group and the two switches of the second switch group to be not turned off.

By the control method of the inverter device, the switching loss of the switch can be effectively reduced, the overall efficiency is improved, and the requirement that the output of the inverter device has low total harmonic distortion is maintained.

For a further understanding of the technology, means, and efficacy of the invention to be achieved, reference should be made to the following detailed description of the invention and accompanying drawings which are believed to be a further and specific understanding of the invention, and to the following drawings which are provided for purposes of illustration and description and are not intended to be limiting.

Drawings

FIG. 1: is a circuit diagram of a first embodiment of the inverter apparatus of the present invention.

FIG. 2: a waveform diagram of a first embodiment of switching control of the inverter apparatus of the present invention.

FIG. 3A: is a waveform diagram of a second embodiment of the switching control of the inverter device of the present invention.

FIG. 3B: is a waveform diagram illustrating a third embodiment of switching control of the inverter device of the present invention.

FIG. 3C: is a waveform diagram illustrating a fourth embodiment of the switching control of the inverter device of the present invention.

FIG. 3D: is a waveform diagram illustrating a fifth embodiment of switching control of the inverter device of the present invention.

FIG. 4A: is a waveform diagram illustrating a sixth embodiment of switching control of the inverter device of the present invention.

FIG. 4B: is a waveform diagram illustrating a seventh embodiment of switching control of the inverter device of the present invention.

FIG. 5: is a waveform diagram illustrating an eighth embodiment of switching control of the inverter device of the present invention.

FIG. 6: is a waveform diagram illustrating a ninth embodiment of switching control of the inverter device of the present invention.

FIG. 7A: is a waveform diagram illustrating a tenth embodiment of switching control of the inverter device of the present invention.

FIG. 7B: is a waveform diagram illustrating an eleventh embodiment of switching control of the inverter device of the present invention.

FIG. 8: is a circuit diagram of the AC-AC converter device of the three-bridge arm structure of the invention.

FIG. 9: is a circuit diagram of a third embodiment of the inverter device of the present invention.

FIG. 10: is a circuit diagram of a fourth embodiment of the inverter device of the present invention.

FIG. 11: a flowchart of a control method of the inverter apparatus of the present invention.

FIG. 12: a flowchart of a first embodiment of the inverter apparatus efficiency control mode of the present invention is shown.

FIG. 13: a flowchart of a second embodiment of the inverter apparatus efficiency control mode of the present invention is shown.

FIG. 14: a flowchart of a third embodiment of the inverter apparatus efficiency control mode of the present invention.

FIG. 15: a flowchart of a fourth embodiment of the inverter apparatus efficiency control mode of the present invention is shown.

FIG. 16: a flowchart of a fifth embodiment of the inverter apparatus efficiency control mode of the present invention.

Wherein the reference numerals

Vi direct current input voltage

Vo AC output voltage

20 load detection unit

30 control unit

40 filter

11 first switch bridge arm

12 second switching leg

13 third switch bridge arm

Q1 first switch

Q2 second switch

Q3 third switch

Q4 fourth switch

S1 first control signal

S2 second control signal

S3 third control signal

S4 fourth control signal

21 first switch bridge arm

22 second switching leg

23 diode bridge arm

31 first switching leg

32 second switching leg

Neutral point of Po

Sd load signal

90 load

Vcon1 first modulation wave

Vcon2 second modulation wave

Vtri carrier

Detailed Description

The technical contents and the detailed description of the present invention are described below with reference to the drawings.

Referring to fig. 1, the inverter device of the present embodiment is a full-bridge inverter device, and the full-bridge inverter device converts a dc input voltage Vi into an ac output voltage Vo, so as to supply power to a load 90. In addition, an output filter 40 is provided at the output side of the full bridge inverter device for filtering the ac output voltage Vo. The dc input side has two input capacitors, which receive a dc input voltage Vi, and the two input capacitors are connected to the neutral point Po to maintain the cross voltages of the two capacitors equal to half of the dc input voltage Vi. Incidentally, the output filter 40 provided on the output side is not limited to the embodiment shown in fig. 1, that is, may be implemented by another type of filter circuit, such as an LC filter circuit.

The full-bridge inverter device includes two switching legs 11 and 12, a load detection unit 20, and a control unit 30. Each of the switch legs 11,12 is coupled in parallel, receives a dc input voltage Vi, and includes switches Q1, Q2 and switches Q3, Q4.

The load detecting unit 20 is coupled to the load 90 and detects an operating state of the load 90 to provide a load signal Sd. For example, the load detecting unit 20 may be a current detector (current sensor) for detecting an output current flowing through the load 90, so as to determine an operation state of the load 90, and determine a control mode of the control unit 30 according to the operation state, for example, taking the pumping load as 30% of the rated load as a basis for switching the control mode, but not limited thereto. However, the current detector is not limited to different circuit designs and applications. Incidentally, the position where the load detection unit 20 is disposed is not limited to the embodiment shown in fig. 1, that is, the load detection unit 20 may be disposed at the front end (rear end compared to that shown in fig. 1) of the output filter 40 or disposed on any one of the paths of the two switch arms 11 and 12, so as to detect the current information and feed back the current information to the control unit 30.

In addition, in addition to the above example of using 30% of the rated load as the basis for switching the control mode, a "load hysteresis zone" buffer can also be introduced as the basis for determining the operating state of the load 90. Assuming that the load hysteresis range is in the range of 2%, one switching pattern is set to have a load drawn at 31% or more of the rated load, and the other switching pattern is set to have a load drawn at 29% or less of the rated load, in other words, the load hysteresis range of 29% to 31% is a buffer range, so as to reduce the sensitivity of the load variation to the control switching method (due to a change in the load state).

For example, when the pumping load continuously increases from 29% below the rated load to 29% above the rated load but not yet 31% above the rated load, the control unit 30 maintains the original control mode; on the contrary, when the load pumping is continuously reduced from 31% higher than the rated load to 31% lower than the rated load but not yet lower than 29% of the rated load, the control unit 30 maintains the original control mode, so that the sensitivity of the load pumping variation to the load state change can be reduced compared with the load judgment of a constant value (for example, 30% described above), and particularly, when the load pumping condition fluctuates around 30% described above, the frequent transition of the control switching mode corresponding to the load state change can be greatly reduced by the buffering of the "load hysteresis zone". In addition, the buffer range can be adjusted according to the actual requirement of the circuit control instead of the limit of the load hysteresis zone being 2%. In summary, after the load detection unit 20 detects the operating state of the load 90, the provided load signal Sd includes information about the operating state of the load 90, i.e., the operating state of the load 90 can be known according to the load signal Sd.

The control unit 30 receives the load signal Sd, determines the operating state of the load 90 according to the load signal Sd, and provides a control signal to correspondingly control the switches to control the full-bridge inverter device. Incidentally, the switching of the control mode is not limited to the switching based on the operation state of only one load 90, but may be based on the operation states of two or more loads 90, for example, the control mode is switched once when the load is 30% of the rated load, and the control mode is switched once again when the load is 80% of the rated load. The above-described switching control will be described in detail later.

Referring to fig. 2, in combination with fig. 1, two switch legs 11 and 12 of the full-bridge inverter are a first switch leg 11 and a second switch leg 12. First switch leg 11 includes a first switch Q1 and a second switch Q2, and second switch leg 12 includes a third switch Q3 and a fourth switch Q4. The first switch Q1 and the fourth switch Q4 form a first switch group, and the second switch Q2 and the third switch Q3 form a second switch group. An alternating current output voltage Vo is provided between a connection point of the first switch Q1 and the second switch Q2 and a connection point of the third switch Q3 and the fourth switch Q4. The control unit 30 provides a first control signal S1 controlling the first switch Q1, a second control signal S2 controlling the second switch Q2, a third control signal S3 controlling the third switch Q3, and a fourth control signal S4 controlling the fourth switch Q4.

As shown in fig. 2, the control signals (S1-S4) are Pulse Width Modulation (PWM) signals generated by comparing the first modulation wave Vcon1, the second modulation wave Vcon2 and the carrier wave Vtri, wherein the first modulation wave Vcon1 and the second modulation wave Vcon2 are sine waves, and the carrier wave Vtri is a triangular wave, but not limited thereto. Specifically, the first control signal S1 is obtained by comparing the first modulation wave Vcon1 with the carrier wave Vtri: when the first modulation wave Vcon1 is greater than the carrier Vtri, the first control signal S1 is at high level; when the first modulation wave Vcon1 is smaller than the carrier Vtri, the first control signal S1 is at a low level, and the compared first control signal S1 is the first high frequency switching signal. Furthermore, the second control signal S2 is a control signal complementary to the first high frequency switching signal level. Similarly, the third control signal S3 is derived by comparing the second modulated wave Vcon2 with the carrier Vtri: when the second modulation wave Vcon2 is greater than the carrier Vtri, the third control signal S3 is high; when the second modulation wave Vcon2 is smaller than the carrier Vtri, the third control signal S3 is low, and the compared third control signal S3 is the second high frequency switching signal. Furthermore, the fourth control signal S4 is a control signal complementary to the second high-frequency switching signal level. In addition, the level of the control signal obtained by comparing the modulated wave with the carrier wave can also be reversed, for example, when the modulated wave is larger than the carrier wave, the control signal is at a low level; when the modulation wave is smaller than the carrier wave, the control signal is at high level. It should be noted that fig. 2 illustrates a conventional Unipolar (Unipolar) voltage switching control method, and the following description is made by taking the Unipolar voltage switching control method as an example, but not limited thereto, and a Bipolar (Bipolar) voltage switching method may be used for generating the control signal.

When the control unit 30 determines that the control mode does not require the efficiency optimization control (e.g., the load-shedding of the load 90 is lower than 30% of the rated load) according to the load signal Sd, the control unit 30 outputs the first control signal S1 as the first high-frequency switching signal, the third control signal S3 as the second high-frequency switching signal, the second control signal S2 as the switching signal complementary to the first high-frequency switching signal level, and the fourth control signal S4 as the switching signal complementary to the second high-frequency switching signal level. Therefore, the output waveform can maintain a sine wave in a light-load operation state, and the total harmonic distortion (THD%) is better.

With the increase of the extraction load, on the basis of maintaining the quality of the output waveform to be acceptable, the efficiency optimization control is carried out to reduce the high-frequency switching of the switching element of the inverter and simultaneously improve the efficiency of the inverter.

As shown in fig. 3A, compared to fig. 2, in the positive half cycle operation, the second control signal S2 is set as off signal; in the negative half cycle operation, the fourth control signal S4 is set to off. As shown in fig. 3B, compared to fig. 2, in the positive half cycle operation, the third control signal S3 is set as off signal; in the negative half cycle operation, the first control signal S1 is set to off. As shown in fig. 3C, compared to fig. 2, in the positive half cycle operation, the second control signal S2 is set as off signal; in the negative half cycle operation, the first control signal S1 is set to off. As shown in fig. 3D, compared to fig. 2, in the positive half cycle operation, the third control signal S3 is set as off signal; in the negative half cycle operation, the fourth control signal S4 is set to off.

In summary, the control modes shown in fig. 3A to 3D are efficiency optimization control, that is, both switches of the first switch set maintain the high frequency switching as shown in fig. 2, and one switch of the second switch set is turned off, and the other switch is switched at high frequency, or both switches of the second switch set maintain the high frequency switching as shown in fig. 2, and one switch of the first switch set is turned off, and the other switch is switched at high frequency. Furthermore, in fig. 3A to 3D, compared to the control waveforms shown in fig. 2, the turn-off signal generated in fig. 2 can be outputted as the turn-off signal by using the control signal of the high frequency switch in fig. 2 through the external control or firmware programming method, and the masking or the like.

It should be noted that in the switching control used in fig. 3A to 3D and fig. 4A and 4B (described later), the duty cycle (duty cycle) of the pwm signal is changed immediately before the current cycle is ended, so that the waveform distortion may occur at the zero crossing of the output waveform. Therefore, the duty cycle of the pulse width modulation signal can be changed to switch when the current period is finished, and the waveform distortion can be effectively improved.

As shown in fig. 4A, as the extraction load continues to increase (e.g., the extraction load of the load 90 is greater than 80% of the rated load), the quality of the output waveform can be maintained and the efficiency of the inverter can be improved by reducing the high frequency switching of the switching elements of the inverter more.

In addition to the control waveforms shown in fig. 2, in order to reduce the high frequency switching of more switches, during the positive half cycle, the second control signal S2 and the third control signal S3 are off signals (which are also set by the external control or firmware programming method, and are not particularly emphasized later), that is, the second switch Q2 and the third switch Q3 (i.e., the second switch group) are controlled to be in an off state. Accordingly, in the positive half cycle operation, the control of the positive half cycle is completed only by switching the first switch Q1 and the fourth switch Q4 (i.e., the first switch group) at a high frequency. During the negative half cycle, the control unit 30 controls the first switch Q1 and the fourth switch Q4 (i.e., the first switch set) to be turned off, so that the load 90 only switches the second switch Q2 and the third switch Q3 (i.e., the second switch set) at high frequency during the negative half cycle to complete the control of the negative half cycle.

Referring to fig. 4B, which shows another control waveform corresponding to fig. 4A, the control unit 30 can output the first control signal S1 and the fourth control signal S4 as off signals, and the second control signal S2 and the third control signal S3 maintain the high frequency switching as shown in fig. 2 during the positive half cycle operation; during the negative half cycle operation, the second control signal S2 and the third control signal S3 are output as off signals, and the first control signal S1 and the fourth control signal S4 maintain the high frequency switching as shown in fig. 2, so as to reduce the high frequency switching of more switches.

In summary, the control unit 30 switches only two switching elements at high frequency at the time of the positive half cycle operation and the negative half cycle operation, thereby reducing the high frequency switching of the switching elements of more inverters. The direct current input voltage Vi can be converted into the alternating current output voltage Vo to supply power to the load 90, and the effects of reducing switching loss and improving efficiency are achieved.

Referring to fig. 5, in another way of generating the control signals, the control signals (S1-S4) are Pulse Width Modulation (PWM) signals, and are generated by comparing the first modulation wave Vcon1, the second modulation wave Vcon2 and the carrier Vtri, which can be seen from the above description of fig. 2 and will not be described again. The biggest difference between fig. 5 and fig. 2 is that the minimum value of the carrier Vtri in the former (i.e., fig. 5) is zero, and the carrier Vtri in the latter (i.e., fig. 2) is a positive or negative value symmetrical to the zero. Thus, the waveforms of the control signals (S1 to S4) shown in fig. 5 can be obtained by comparing the first modulation wave Vcon1, the second modulation wave Vcon2, and the carrier Vtri.

Referring to fig. 1 again, when the control unit 30 determines that it does not need the efficiency optimization control according to the load signal Sd, in the positive half cycle, the first control signal S1 is the first high frequency switching signal, the fourth control signal S4 is the first low frequency on signal, the second control signal S2 is the switching signal complementary to the first high frequency switching signal level, and the third control signal S3 is the off signal. In the negative half cycle operation, the second control signal S2 is a low-frequency on signal, the third control signal S3 is a high-frequency switching signal, the first control signal S1 is an off signal, and the fourth control signal S4 is a switching signal complementary to the level of the high-frequency switching signal. It is worth mentioning that the "low frequency" mentioned in the present invention is a frequency of about 60Hz (or 50Hz), but not limited thereto; while "high frequency" is relative to "low frequency" and is a frequency of about 20kHz or 10kHz, without limitation.

With the increase of the load extraction, the efficiency optimization control can be carried out to reduce the high-frequency switching of the switching elements of the inverter, and the quality of the output waveform can be maintained and the efficiency of the inverter can be improved.

Referring to fig. 6, compared to fig. 5, in order to reduce the high frequency switching of more switches, the second control signal S2 is off signal during the positive half cycle, i.e., the second switch Q2 and the third switch Q3 (i.e., the second switch group) are turned off (turnedoff). Accordingly, in the positive half cycle operation, the fourth switch Q4 is controlled by only the high frequency switch Q1 and the low frequency conduction to complete the positive half cycle control. In the negative half cycle operation, the fourth control signal S4 is an off signal, i.e., controls the first switch Q1 and the fourth switch Q4 (i.e., the first switch set) to be in an off state. Accordingly, in the negative half cycle operation, the second switch Q2 is controlled by only the high frequency switch Q3 and the low frequency conduction to complete the control of the negative half cycle.

Referring to FIG. 7A, according to the control waveforms of FIG. 5, the control waveforms of the first control signal S1, the second control signal S2, the third control signal S3 and the fourth control signal S4 are asserted during the positive half cycle operation; during the negative half cycle, the first control signal S1 is further exchanged with the third control signal S3, the second control signal S2 is exchanged with the fourth control signal S4, and the control waveforms of the third control signal S3 and the fourth control signal S4 are inverted. Thus, during the positive and negative half-cycles, at least one of the third control signal S3 and the fourth control signal S4 is controlled to be the off signal, i.e., the third control signal S3 is controlled to be the off signal during the positive half-cycle, and the fourth control signal S4 is controlled to be the off signal during the negative half-cycle (as shown in fig. 7A); or the deformation of the other control waveform may be: in FIG. 7A, the first control signal S1 is exchanged with the third control signal S3, and the second control signal S2 is exchanged with the fourth control signal S4 (not shown).

Referring to fig. 7B, switching element control for optimizing efficiency is shown in comparison to fig. 7A. During the positive half cycle operation, the second control signal S2 is further switched from high frequency to off signal, and during the negative half cycle operation, the first control signal S1 is further switched from high frequency to off signal, so as to reduce the high frequency switching of the switching element and achieve the purpose of optimizing efficiency.

Referring to fig. 8, the three-bridge ac-ac converter device includes an ac-dc conversion stage formed by a third switch bridge arm 13 and a first switch bridge arm 11, a dc-ac conversion stage (i.e., an inverter device) formed by the first switch bridge arm 11 and a second switch bridge arm 12, a load detection unit 20, and a control unit 30. The first switch leg 11 is a common leg of the ac-dc conversion stage and the inverter device, and a Neutral line (Neutral) of the ac input voltage and a Neutral line of the ac output voltage are connected to a common connection point of two switches in the common leg 11.

Depending on the operating state of the load 90, the inverter devices in the three-leg configuration ac-ac converter device can be controlled by the switches shown in fig. 7A or 7B, and the common leg (i.e., the first switch leg 11) is operated at a low frequency, and the third switch Q3 and the fourth switch Q4 of the first switch leg 11 are controlled in a control mode in which one switch is turned off in each of the positive and negative half cycles. The detailed description is as follows: since the first switch leg 11 of the three-leg structure ac-ac converter device is a common leg of the ac-dc conversion stage and the inverter device, control signals of the third switch Q3 and the fourth switch Q4 of the first switch leg must be matched with the ac waveform of the input end, so that when the ac power at the input end is positive half cycle (voltage is greater than zero), the upper switch (i.e., the third switch Q3) of the common leg 11 needs to be turned off, and when the ac power at the input end is negative half cycle (voltage is less than zero), the lower switch (i.e., the fourth switch Q4) of the common leg 11 needs to be turned off.

As shown in fig. 9, the inverter device according to the third embodiment is a Neutral Point Clamped (NPC) inverter device, and includes a first switching leg 21, a second switching leg 22, a diode leg 23, a load detection unit 20, and a control unit 30. First switch leg 21 includes first switch Q1 and second switch Q2, and second switch leg 22 includes third switch Q3 and fourth switch Q4. One end of the diode leg 23 is coupled to a connection point of the first switch Q1 and the fourth switch Q4, and the other end of the diode leg 23 is coupled to a connection point of the second switch Q2 and the third switch Q3. An alternating current output voltage Vo is provided between the connection point of the second switch Q2 and the fourth switch Q4 and the grounding point.

When the control unit 30 determines that it needs to perform efficiency optimization control according to the operating state of the load 90, it controls one of the switches of the first switch set to be switched at a high frequency and the other switch to be switched at a low frequency, and both switches of the second switch set are turned off, or one of the switches of the second switch set to be switched at a high frequency and the other switch to be switched at a low frequency and both switches of the first switch set to be turned off, as shown in fig. 6.

As shown in fig. 10, the inverter device according to the fourth embodiment is a T-type neutral point clamped (T-type NPC) inverter device, and includes a first switching arm 31, a second switching arm 32, a load detection unit 20, and a control unit 30. First switch leg 31 is coupled to second switch leg 32. First switch leg 31 includes first switch Q1 and second switch Q2, and second switch leg 32 includes third switch Q3 and fourth switch Q4. The common connection point of the first switch Q1, the second switch Q2 and the third switch Q3 provides the ac output voltage Vo with the ground point.

When the control unit 30 determines that it needs to perform efficiency optimization control according to the operating state of the load 90, it controls one of the switches of the first switch set to be switched at a high frequency and the other switch to be switched at a low frequency, and both switches of the second switch set are turned off, or one of the switches of the second switch set to be switched at a high frequency and the other switch to be switched at a low frequency and both switches of the first switch set to be turned off, as shown in fig. 6.

It should be noted that the switching control strategies shown in fig. 2 to 7B can be applied to the inverter apparatus with the full-bridge architecture shown in fig. 1; the switching control strategies illustrated in fig. 5 and 6 may be applied to the neutral point clamped inverter arrangement illustrated in fig. 9 and the T-type neutral point clamped inverter arrangement illustrated in fig. 10; the switching control strategy shown in fig. 3D, 4A, 6, 7A and 7B can be applied to the inverter device in the three-bridge arm configuration ac-ac converter device shown in fig. 8.

In summary, the main spirit of the switching element control for optimizing efficiency by providing different PWM modulation schemes according to the load operation status is: during the positive half cycle, the control signal originally output by the first switch group is kept, and the second switch group selectively turns off one control signal or is completely off; or, during the positive half cycle, the control signal originally output by the second switch group is kept, and the first switch group selectively turns off one of the control signals or is completely off, and during the negative half cycle, the control signal originally output by the first switch group is kept, and the second switch group selectively turns off one of the control signals or is completely off.

It should be noted that, for the same generation manner of the pwm signal, fig. 3A to 3D, fig. 4A and 4B are the optimization control of fig. 2, fig. 6 is the optimization control of fig. 5, and fig. 7B is the optimization control of fig. 7A, and the three-stage control (for example, fig. 2 → fig. 3A to 3D → fig. 4A and 4B) or the two-stage control (for example, fig. 2 → fig. 4A and 4B, or fig. 3A to 3D → fig. 4A and 4B, or fig. 2 → fig. 3A to 3D, or fig. 5 → fig. 6, or fig. 7A → fig. 7B) may be practically unlimited according to the load operation state, or only a single control mode (any one of fig. 2 to 7B) may be used. However, it is not limited thereto, and the control waveforms generated by different width modulation signal generation methods may be used to match (for example, under the condition that the inverter device can work normally, one or more than two control waveforms of fig. 2 to 7B are used to match), so as to achieve the purpose of optimizing efficiency.

In addition, the waveform of the control signal of fig. 5, the waveform of the control signal of fig. 7A obtained by shifting, and the first control signal S1 and the second control signal S2 in the waveform of the control signal of fig. 7B which are further optimized are switched between various control modes, and only two states of off or low frequency on are provided, and high frequency switching does not occur, so that specification selection of the corresponding switch can be reduced, and circuit cost is reduced.

Referring to fig. 11, the control method can be applied to a full-bridge inverter device, an inverter device in a three-bridge arm structure ac-ac converter device, a neutral point clamped inverter device, and a T-type neutral point clamped inverter device.

The control method comprises the following steps: first, an operating state of a load is detected to provide a load signal (S10). Then, a load signal is received and a plurality of control signals are provided to correspondingly control the switch (S20). Finally, the control mode is selected according to the load signal to control neither the two switches of the first switch set to be turned off and at least one switch of the second switch set to be turned off, or to control both the switches of the second switch set to be turned off and at least one switch of the first switch set to be turned off, or to control both the switches of the first switch set and the switches of the second switch set to be turned off (S30).

As shown in fig. 12, one of the control modes of step (S30) may be: the two switches of the first switch set are controlled to be switched at high frequency, and the two switches of the second switch set are both switched off, or the two switches of the second switch set are controlled to be switched at high frequency, and the two switches of the first switch set are both switched off (S31), as can be seen from the descriptions of fig. 4A and 4B.

As shown in fig. 13, one of the control modes of step (S30) may be: controlling both switches of the first switch set to be high frequency switching, and one switch of the second switch set to be off, and the other switch to be high frequency switching, or controlling both switches of the second switch set to be high frequency switching, and one switch of the first switch set to be off, and the other switch to be high frequency switching (S32), may be combined with the description with reference to fig. 3A to 3D.

As shown in fig. 14, one of the control modes of step (S30) may be: the two switches of the first switch set and the two switches of the second switch set are controlled to be switched at high frequency (S33), which can be referred to the description of fig. 2.

As shown in fig. 15, one of the control modes of step (S30) may be: one of the switches of the first switch set is controlled to be switched at a high frequency, the other switch is controlled to be switched at a low frequency, and both switches of the second switch set are turned off, or one of the switches of the second switch set is controlled to be switched at a high frequency, the other switch is controlled to be switched at a low frequency, and both switches of the first switch set are turned off (S34), which can be referred to the description of fig. 6 and 7B.

As shown in fig. 16, one of the control modes of step (S30) may be: one of the switches of the first switch set is controlled to be switched at a high frequency, the other switch is controlled to be switched at a low frequency, and one of the switches of the second switch set is turned off, and the other switch is controlled to be switched at a high frequency, or one of the switches of the second switch set is controlled to be switched at a high frequency, and the other switch is controlled to be switched at a low frequency, and one of the switches of the first switch set is turned off, and the other switch is switched at a high frequency (S35), which can be referred to the description of fig. 5 and 7A. In summary, the inverter and the control method thereof provided by the present invention can effectively reduce the switching loss of the switch, so as to improve the overall efficiency and maintain the requirement of low total harmonic distortion of the output of the inverter.

While the invention has been described in connection with what is presently considered to be the most practical and preferred embodiment, it is to be understood that the invention is not to be limited to the disclosed embodiment, but on the contrary, is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims.