阅读说明：本技术 受箝制受控延迟运算放大器、控制电路及选择性控制从运算放大器电路的箝制恢复的方法 (Clamped controlled delay operational amplifier, control circuit and method for selectively controlling clamp recovery from an operational amplifier circuit ) 是由 M·H·莱特 于 2019-08-08 设计创作，主要内容包括：本发明涉及受箝制受控延迟运算放大器、控制电路及选择性控制从运算放大器电路的箝制恢复的方法。本发明描述了用于箝制运算放大器的输出电压、同时使箝制后恢复延迟最小化的设备、系统和方法。控制两种操作模式之间的转换的电路可包括用于将输出电压与箝制电压进行比较并且输出第一模式信号的第一比较器、用于将输入电压与参考电压进行比较并且输出第二模式信号的第二比较器。第一逻辑部件可接收所述模式信号,执行逻辑操作,并且输出逻辑信号。基于所述逻辑信号的值,双工输出可输出跟踪信号和反向对应的保持信号,此类跟踪信号和保持信号由运算放大器电路用来配置调节块,所述调节块用于在模式转换期间控制瞬变。(The invention relates to a clamped controlled delay operational amplifier, a control circuit and a method for selectively controlling the clamped recovery of an operational amplifier circuit. Apparatus, systems, and methods are described for clamping the output voltage of an operational amplifier while minimizing post-clamp recovery delay. The circuit for controlling the transition between the two operation modes may include a first comparator for comparing the output voltage with the clamped voltage and outputting a first mode signal, a second comparator for comparing the input voltage with a reference voltage and outputting a second mode signal. The first logic may receive the mode signal, perform a logic operation, and output a logic signal. Based on the value of the logic signal, the duplex output may output a tracking signal and an inversely corresponding hold signal, such tracking and hold signals being used by the operational amplifier circuit to configure an adjustment block for controlling transients during mode transitions.)

1. A clamped controlled delay operational amplifier, comprising:

a first circuit comprising an operational amplifier; and

a second circuit configured to regulate the first circuit into one of a first mode of operation and a second mode of operation for a first comparison of an output voltage of the first circuit to a clamped voltage and a second comparison of an input voltage to a reference voltage.

2. The clamped controlled delay operational amplifier of claim 1,

wherein the first circuit further comprises:

a first regulating block;

a second regulating block;

an operational amplifier; and

a first switch for controlling the operation of the switch,

the operational amplifier includes: a first gain stage and a second gain stage;

the first switch includes:

a first switch input node;

a first switched tracking track coupled to each of the second conditioning block and the second gain stage via a second node; and

a first switch holding rail coupled to the first conditioning block;

wherein the second conditioning block and the second gain stage are coupled in parallel between the second node and a third node;

wherein the second gain stage is a miller compensation amplifier;

wherein a second capacitor is coupled in parallel with the second gain stage and the second conditioning block;

wherein the first switch selectively couples and decouples the operational amplifier with each of the first and second conditioning blocks according to whether a current operating mode is one of the first operating mode, the second operating mode, and a conversion mode.

3. The clamped controlled delay operational amplifier of claim 2,

wherein the first switch couples the first gain stage to the first conditioning block during the first mode of operation; and is

Wherein the first switch couples the first gain stage to the second gain stage during the second mode of operation.

4. The clamped controlled delay operational amplifier of claim 1, wherein the second circuit comprises:

a first comparator configured to compare the output voltage with the clamped voltage and output a first mode signal;

a second comparator configured to compare the input voltage with the reference voltage and output a second mode signal;

a first logic configured to receive the first mode signal and the second mode signal, perform at least one logic operation, and output a logic signal; and

a duplex output component configured to receive the logic signal and, based on a current value of the logic signal, output each of a corresponding tracking signal and an inversely corresponding hold signal;

wherein the tracking signal and the holding signal have different voltage potentials.

5. The clamped controlled delay operational amplifier of claim 4,

wherein the first mode signal has a positive value when the output voltage is greater than or equal to the clamped voltage;

wherein the second mode signal has a positive value when the input voltage is less than the reference voltage;

wherein the current value of the logic signal is negative when the first mode signal and the second mode signal both have positive values;

wherein the current value of the logic signal is positive when at least one of the first mode signal and the second mode signal has a negative value;

wherein when the duplex output component outputs a positive value, the first circuit is configured into the second mode of operation; and is

Wherein the first circuit is configured to the first mode of operation when the duplex output means outputs a negative value.

6. The clamped controlled delay operational amplifier of claim 5,

wherein the first mode of operation is a hold mode and the second mode of operation is a track mode;

wherein the operational amplifier comprises:

a first gain stage; and

a second gain stage having a second gain stage output where the output voltage is provided to a third node;

wherein the first gain stage is selectively coupled to the second gain stage by a first switch and a second node;

the controlled delay operational amplifier further comprises:

a first conditioning block selectively coupled to the first gain stage by the first switch during the first mode of operation; and

a second conditioning block coupled to the second node and to the third node in a parallel configuration with the second gain stage;

wherein the first switch is configured to receive at least one of the tracking signal and the hold signal;

wherein the first switch selectively couples and decouples the first gain stage and the second gain stage based on receipt of at least one of the tracking signal and the hold signal;

wherein during the first mode of operation, the first gain stage is decoupled from the second gain stage; and is

Wherein during the second mode of operation, the first gain stage is coupled to the second gain stage.

7. A control circuit for controlling the switching of a controlled delay operational amplifier circuit between a first mode of operation and a second mode of operation, the control circuit comprising:

a first comparator configured to compare an output voltage with a clamped voltage and output a first mode signal;

a second comparator configured to compare an input voltage with a reference voltage and output a second mode signal;

a first logic configured to receive the first mode signal and the second mode signal, perform at least one logic operation, and output a logic signal; and

a duplex output component configured to receive the logic signal and output each of a corresponding tracking signal and an inverted corresponding hold signal based on whether the logic signal comprises a positive value or a negative value;

wherein the tracking signal and the hold signal have different voltage potentials and are used by a first switch to selectively couple and decouple a first gain stage of an operational amplifier with a second gain stage of the operational amplifier.

8. The control circuit of claim 7, wherein the control circuit,

wherein the tracking signal and the hold signal are used by a first conditioning block to provide a fast response generated by the operational amplifier when switching from clamp mode to tracking mode;

wherein the tracking signal and the hold signal are used by a second adjustment block to minimize transients that occur when the operational amplifier transitions between two different modes of operation; and is

Wherein a first one of the two different operating modes is the clamping mode and a second one of the two different operating modes is the tracking mode.

9. A method for selectively controlling clamp recovery from an operational amplifier circuit, comprising:

coupling a capacitor provided in the operational amplifier circuit to a reference voltage during a first mode of operation; and

biasing an input voltage of the operational amplifier circuit with the reference voltage by discharging the capacitor when the operational amplifier circuit transitions from a first mode of operation to a second mode of operation.

10. The method of claim 9, wherein the first and second light sources are selected from the group consisting of,

wherein the capacitor is provided in a first conditioning block and is selectively coupled to a first operational amplifier provided in the operational amplifier circuit;

wherein the first operational amplifier comprises a first gain stage and a first switch; and is

Wherein a first switch couples the first gain stage with the capacitor during the first mode of operation.

Technical Field

The technology described herein relates generally to operational amplifiers. More particularly, the technology described herein relates generally to apparatus and methods for accurately clamping the output of an operational amplifier.

Background

As is generally known and understood, operational amplifier ("op-amp") integrator circuits, such as the circuit 100 shown in fig. 1A, are typically formed with a resistive-capacitive (RC) feedback loop. As shown, such an operational amplifier circuit generally includes an operational amplifier (a)101 having a non-inverting (+) input 102 connected to a reference voltage signal source 104 that provides a reference voltage signal VREF, and an inverting (-) input 106 connected to an RC circuit formed by a resistor 103 having a first resistance R1 connected to an input voltage signal source 108 that provides an input voltage signal VIN. The inverting input 106 is also connected in parallel with a first capacitor 105 having a first capacitance C1 that is connected to an output voltage node 110 that provides the output voltage signal VOUT of the operational amplifier 101.

As is generally known, during operation, the operational amplifier circuit often saturates, causing the RC feedback loop to be detuned. Recovery from saturation typically takes time because the operational amplifier typically includes a miller capacitor that requires proper biasing. In addition, the re-biasing of the capacitors typically occurs slowly, such that the op-amp circuit 100 itself may recover very slowly. A delay in the linear operation of the operational amplifier 101 typically occurs because the operational amplifier 101 is required to exit the clamp and re-bias itself. The re-biasing occurs when the input voltage signal VIN returns to the value of the reference voltage signal VREF. The RC time constant formed by the first resistor R1 and the first capacitor C1 generally determines the amount of time required for the operational amplifier 101 to linearly resume operation. As used herein, the response of the operational amplifier circuit when recovering from a saturated and/or clamped output condition may be determined from the product of the RC time constants. Recovery substantially less than the RC time constant is defined herein as recovery less than a percentage (20%) of the RC time constant, and such response is further defined herein as a "fast" response.

As shown in FIG. 1B, usingOne common solution to attempt to prevent saturation of the operational amplifier circuit 100 is to use a "clamp" circuit 111, wherein the output voltage VOUT of the operational amplifier circuit 111 is clamped at a maximum output voltage. As shown, in general, the device is included

The buffer 112 is connected to a clamped voltage signal source 114 that provides a clamped voltage signal VCLAMP. The buffer 112 is further connected to a positive supply voltage terminal 116 of the operational amplifier 101 in a maximum limiter configuration, wherein a negative supply voltage terminal 118 is connected to a low voltage potential N, such as a ground voltage potential. VCLAMP is typically set at a predefined value to prevent the operational amplifier 101 from being driven to an output voltage VOUT that is too high or too low.

As shown in fig. 1C, this approach typically causes the operational amplifier 101 to produce a voltage response that will cause a delay tdelay when the output voltage VOUT is lowered after the specified value of the clamped voltage signal VCLAMP has been reached. This delay occurs because although the output voltage is clamped, the potential at the negative supply voltage N will drift downward until the next input voltage signal VIN is received. Furthermore, the delay tdelay occurs because the operational amplifier 101A needs to be re-biased by making the negative input supply voltage N equal to the reference voltage VREF.

Similarly, other known methods of preventing saturation of an operational amplifier integrator circuit by using clamping or otherwise also suffer from post-clamp recovery delays. Accordingly, there is a need for an apparatus, circuit, and method that facilitates clamping of the output voltage of an operational amplifier (such as an operational amplifier integrator circuit) while minimizing post-clamp recovery delay. Various embodiments of the present disclosure meet these and other needs.

Disclosure of Invention

Various embodiments of the present disclosure relate generally to apparatus, systems, and methods for minimizing recovery delay of a clamped operational amplifier circuit. According to at least one embodiment of the present disclosure, a clamp controlled delay operational amplifier may include a first circuit including an operational amplifier; and a second circuit configured to adjust the first circuit to one of a first mode of operation and a second mode of operation. For at least one embodiment, the first circuit is configured into one of the two modes based on results generated from a first comparison of an output voltage of the first circuit to a clamped voltage and a second comparison of an input voltage to a reference voltage.

For at least one implementation, a first circuit for a clamped controlled delay operational amplifier may include an operational amplifier, a first switch, a first regulation block, and a second regulation block. The first switch may selectively couple and decouple the operational amplifier with each of the first and second conditioning blocks. Such coupling and/or decoupling may depend on whether the current operating mode is in the first operating mode, the second operating mode, or the transition mode. For at least one implementation, an operational amplifier may include a first gain stage and a second gain stage.

For at least one embodiment, the operational amplifier may include a first switch, which may include a first switch having an input node, a first switch tracking a rail, and a first switch holding the rail. For at least one embodiment, the first switch holding rail may be coupled to the first conditioning block. For at least one implementation, the first switched tracking track may be coupled to each of the second conditioning block and the second gain stage via a second node. For at least one implementation, a second regulation block may be coupled in parallel with the second gain stage between the second node and a third node of the circuit, forming a clamped controlled delay operational amplifier. For at least one embodiment, the second gain stage may include a miller compensation amplifier that is compensated by a second capacitor coupled in parallel with the second gain stage.

For at least one implementation, the clamped controlled delay operational amplifier may include a first switch that couples the first gain stage to the first conditioning block during the first mode of operation. The first switch may also couple the first gain stage to the second gain stage during the second mode of operation. The first mode of operation may include a hold or clamp mode, while the second mode of operation may include a tracking or steady-state (e.g., non-saturated) mode of operation.

For at least one embodiment, the clamped controlled delay operational amplifier may include a second circuit including a first comparator configured to compare the output voltage with a clamped voltage. The first comparator may output a first mode signal based on the result of such comparison. Also, the clamped controlled delay operational amplifier may include a second circuit, which may further include a second comparator configured to compare the input voltage with a reference voltage. The second comparator may output a second mode signal based on the result of such comparison.

For at least one embodiment, a clamped controlled delay operational amplifier may include a first logic configured to receive a first mode signal and a second mode signal, perform at least one logic operation, and output a logic signal.

For at least one embodiment, the clamped controlled delay operational amplifier may include a duplexing output component configured to receive the logic signal and output each of the corresponding tracking signal and the inverse corresponding hold signal based on a value of the logic signal, such as whether the value is a positive value or a negative value. For at least one embodiment, the tracking signal and the hold signal may have different voltage potentials.

For at least one embodiment, the clamp controlled delay operational amplifier may include a control circuit that generates the first mode signal when an output voltage of the operational amplifier is greater than or equal to a clamp voltage of the operational amplifier. For at least one embodiment, the mode signal may have a positive value. For at least one embodiment, the clamped controlled delay operational amplifier may include a control circuit that generates a second mode signal that may have a positive value when an input voltage to the operational amplifier is less than a reference voltage.

For at least one implementation, the clamped controlled delay operational amplifier may include a control circuit that generates a first logic signal that may have a negative value when each of the first mode signal and the second mode signal has a positive value. For at least one implementation, the second logic signal may have a positive value when at least one of the first mode signal and the second mode signal has a negative value. For at least one embodiment, the duplex output component may be configured to output a positive value that configures the operational amplifier into the second mode of operation. For at least one embodiment, the duplex output component may be configured to output a negative value that configures the operational amplifier into the first mode of operation.

For at least one implementation, a clamped controlled delay operational amplifier may include a first gain stage and a second gain stage. For at least one embodiment, the second gain stage may generate an output voltage that is provided to the third node. For at least one embodiment, the first gain stage may be selectively coupled to the second gain stage, for example, by a first switch and a second node. For at least one embodiment, the first switch may be configured to receive at least one of a track signal and a hold signal. For at least one implementation, the first switch may selectively couple and decouple the first gain stage to the second gain stage based on receipt of at least one of the tracking signal and the hold signal. For at least one implementation, the first gain stage [204] may be decoupled from the second gain stage during the first mode of operation. For at least one implementation, the first gain stage may be coupled to the second gain stage during the second mode of operation.

For at least one implementation, the clamped controlled delay operational amplifier may include a first switch having a first switch holding rail. The first conditioning block may be selectively coupled to the first gain stage by a first switch during a first mode of operation. For at least one embodiment, the first conditioning block may include a fourth node coupled to the first switch holding rail, and a third capacitor coupled between the fourth node and the fourth switch. For at least one embodiment, the fourth node may be coupled to the first switch. The fourth switch may include a fourth switch input node that may be coupled to the third capacitor, a fourth switch tracking rail that may be coupled to a reference voltage node that provides a reference voltage [ VREF ], and a fourth switch holding rail that may be coupled to a fifth node. For at least one embodiment, the second switch may include a second switch input node that may be coupled to the fifth node, a second switch tracking rail that may be coupled to the fourth node, and a second switch holding rail that may be coupled to the operational amplifier. For at least one embodiment, the fourth gain stage may include a fourth gain stage input node that may be coupled to a fourth node; and a fourth gain stage output node coupleable to the fifth node. For at least one implementation, the second switch may be configured to selectively couple the fourth gain stage to one of the fourth node or the operational amplifier by pulling to one of the second switch tracking rail and the fourth switch holding rail, respectively, based on whether the tracking signal or the holding signal has a positive value. For at least one implementation, the fourth switch may be configured to selectively couple the third capacitor to one of the reference voltage node or the fifth node by pulling to one of the fourth switch tracking rail and the fourth switch holding rail, respectively, based on whether the tracking signal or the holding signal has a positive value.

For at least one embodiment, the clamped controlled delay operational amplifier may include a second regulation block coupled to the first gain stage by a first switch and a second node; and a second conditioning block coupled to the third node and configured in a parallel configuration with the second gain stage and the second capacitor.

For at least one embodiment, the clamped controlled delay operational amplifier may include a second conditioning block including a third switch having a third switch input, a third switch tracking rail coupleable to ground, and a third switch holding rail coupleable to a second node. Further, a third gain stage may be coupled to the second gain stage and to the third switching input. The third switch may be configured to selectively couple the third gain stage to one of ground or a second node by pulling to one of the third switch tracking rail and the third switch holding rail, respectively, based on the values of the tracking signal and the holding signal (and whether such values are positive or not).

For at least one embodiment, the clamped controlled delay operational amplifier may include a first gain stage having a non-inverting input node, an inverting input node coupleable to a reference voltage source, and an output node coupleable to the first switch. For at least one embodiment, the first circuit may include a first resistor that may be coupled to the first circuit at a first node and between the input voltage source and the non-inverting input node; and a first capacitor, the first capacitor being coupleable to the first node and to the third node.

For at least one implementation, the clamped controlled delay operational amplifier may include a second capacitor. The second capacitor may be a miller compensation capacitor. For at least one embodiment, the integration clamped controlled delay operational amplifier may be formed by an RC circuit formed by a first circuit, a first resistor, and a first capacitor. For at least one implementation, the controlled delay may be generated based on a response time associated with at least one of the first comparator and the second comparator.

For at least one implementation, at least one of the clamped controlled delay operational amplifier, the clamping voltage used thereby, and the reference voltage may be predetermined.

The control circuit for controlling a transition between a first mode of operation and a second mode of operation of the operational amplifier circuit may comprise a first comparator configured to compare the output voltage with a clamped voltage and to output a first mode signal. For at least one embodiment, the control circuit may include a second comparator configured to compare the input voltage with a reference voltage and output a second mode signal. For at least one embodiment, the control circuit may include a first logic configured to receive the first mode signal and the second mode signal, perform at least one logical operation, and output a logic signal. For at least one embodiment, the control circuit may include a duplex output component configured to receive the logic signal and output each of the corresponding tracking signal and the inverted corresponding hold signal based on whether the logic signal includes a positive value or a negative value. For at least one embodiment, the control circuit may include the use of a tracking signal [ T ] and a hold signal [ H ] having different voltage potentials.

For at least one implementation, the control circuit may include a first switch to selectively couple and decouple a first gain stage of an operational amplifier with a second gain stage of the operational amplifier using a tracking signal and a hold signal.

For at least one implementation, the control circuit may include a first regulation block to provide a fast response generated by the operational amplifier when switching from the clamp mode to the tracking mode using the tracking signal and the hold signal.

For at least one implementation, the control circuit may include a second adjustment block that uses the tracking signal and the hold signal to minimize transients that occur when the operational amplifier transitions between the two different modes of operation. For at least one embodiment, a first of the two different operating modes is a clamping mode and a second of the two different operating modes is a tracking mode.

For at least one embodiment of the present disclosure, a method for selectively controlling clamp recovery from an operational amplifier circuit may include coupling a third capacitor to a reference voltage during a first mode of operation; and biasing the input voltage of the operational amplifier circuit with the reference voltage by discharging the third capacitor when the operational amplifier circuit transitions from the first mode of operation to the second mode of operation.

For at least one embodiment of the present disclosure, a method for selectively controlling clamp recovery from an operational amplifier circuit may include the use of a third capacitor present in a first conditioning block selectively coupled to the operational amplifier circuit. For at least one embodiment configured for use with a method for selectively controlling clamp recovery from an operational amplifier circuit, a first operational amplifier circuit may include a first gain stage. For at least one embodiment of the method, during the first mode of operation, the first switch may be configured to couple the first gain stage with the third capacitor via the fourth node.

For at least one implementation, a method for selectively controlling clamp recovery from an operational amplifier circuit may include the use of a first conditioning block having a fourth switch. During the method, a third capacitor may be coupled between the fourth node and the fourth switch. For at least one embodiment, the fourth switch may include a fourth switch input node that may be coupled to the third capacitor, a fourth switch tracking rail that may be coupled to a reference voltage node that provides a reference voltage, and a fourth switch holding rail that may be coupled to the fifth node.

For at least one embodiment, a method for selectively controlling clamp recovery from an operational amplifier circuit may include the use of a second switch including a second switch input node coupleable to a fifth node, a second switch tracking rail coupleable to a fourth node, and a second switch holding rail coupleable to a first circuit.

For at least one embodiment, a method for selectively controlling clamp recovery from an operational amplifier circuit may include the use of a fourth gain stage including a fourth gain stage input node coupleable to a fourth node and a fourth gain stage output node coupleable to a fifth node.

For at least one embodiment, a method for selectively controlling clamp recovery from an operational amplifier circuit may include use of a second switch configured to selectively couple a fourth gain stage to one of a fourth node or an operational amplifier by pulling to one of a second switch tracking rail and a fourth switch holding rail, respectively, based on a value and/or polarity of a received tracking signal [ T ] or a received holding signal [ H ]. For at least one implementation, the selective coupling occurs when one of the track signal and the hold signal has a positive value.

For at least one embodiment, a method for selectively controlling clamp recovery from an operational amplifier circuit may include the use of a fourth switch configured to selectively couple a third capacitor to one of a reference voltage node or a fifth node by pulling to one of a fourth switch tracking rail and a fourth switch holding rail, respectively, based on a value and/or polarity of a received tracking signal [ T ] or a received holding signal. For at least one implementation, the selective coupling occurs when one of the track signal and the hold signal has a positive value.

Drawings

Features, aspects, advantages, functions, modules, and components of the devices, systems, and methods provided by various embodiments of the present disclosure are further disclosed herein with respect to at least one of the following description and the accompanying drawings.

Fig. 1A is a schematic diagram of a prior art integrating operational amplifier circuit.

FIG. 1B is a diagram of a clamped integral operational amplifier circuit according to the prior art.

FIG. 1C is a graph showing the voltage response over time of the prior art circuit of FIG. 1B.

Fig. 2 is a schematic diagram illustrating a first circuit for use in a clamped controlled delay operational amplifier, the first circuit configured for use in accordance with at least one embodiment of the present disclosure.

Fig. 3 is a schematic diagram illustrating a second circuit for use in a clamped controlled delay operational amplifier, the second circuit configured for use in accordance with at least one embodiment of the present disclosure.

Fig. 4 is a schematic diagram illustrating a third circuit for use in a clamped controlled delay operational amplifier configured to operate the first circuit of fig. 2 in a hold mode of operation in accordance with at least one embodiment of the present disclosure.

Fig. 5 is a schematic diagram illustrating a fourth circuit for use in a clamped controlled delay operational amplifier configured to operate the first circuit of fig. 2 in a tracking mode of operation in accordance with at least one embodiment of the present disclosure.

Fig. 6 is a graph illustrating the voltage response over time of a clamped controlled delay operational amplifier configured in accordance with at least one embodiment of the present disclosure.

Detailed Description

Various embodiments described herein relate to apparatus, circuits, systems, and methods that facilitate clamping of an output voltage of an operational amplifier (such as an operational amplifier integrator circuit) while minimizing post-clamp recovery delay. Various embodiments of the present disclosure meet these and other needs.

As shown in fig. 2, a first circuit 200 of an embodiment of a clamped controlled delay operational amplifier circuit providing clamping of an operational amplifier output voltage while minimizing post-clamp recovery delay according to at least one embodiment of the present disclosure includes an operational amplifier 202 having a first gain stage 204, a second gain stage 206, and a second capacitor 208 having a second capacitance C2. For at least one embodiment, the operational amplifier 202 is a miller compensation operational amplifier, wherein the second capacitor 208 is connected in parallel across the second gain stage input node 209 and the second gain stage output 207. The characteristics and configuration of miller compensation operational amplifiers are well known in the art. For at least one embodiment, the first gain stage, the second gain stage, and the third and fourth gain stages to be described below may use Operational Transconductance Amplifiers (OTA) illustrated in fig. 2 and 4-5 by the symbols a1, a2, A3, and a 4.

The first gain stage 204 is suitably configured to receive the input voltage signal VIN and the reference voltage signal VREF at the respective non-inverting 201 and inverting 203 input nodes. The non-inverting input node 201 is connected at a first node 211. The first gain stage 204 is also connected to the input voltage source 108, suitably via an RC circuit formed by the first resistor 103 and the first capacitor 105 at the first node 211.

The circuit 200 also includes a first switch (S1)210 suitably connected between the first gain stage output 205 and the second gain stage input 209. The second gain stage 206 is suitably configured to output the output voltage signal VOUT at the second gain stage output 207.

As further shown, for at least one embodiment, the first switch 210 may be configured as a double throw switch. It should be understood that in other embodiments of the present disclosure, other types of switches may be used for any of the switches described herein. First switch input node 213 is coupled to the output of first gainstage output 205. The first switch 210 couples the first gain stage output 205 to the top rail 212 of the first switch 210 when the hold signal H is present at the first holding node 214 and couples the first gain stage output to the bottom rail 216 of the first switch 210 when the tracking signal T is present at the first tracking node 218. As described further below, at any given time, either the hold signal H or the tracking signal T has only one of the signals active at any given time. The hold signal H, when active, configures the circuit for a hold mode of operation and the track signal T, when active, configures the circuit for a track mode of operation. The active signal may be represented by a positive voltage, polarity, or other aspect.

The circuit 200 may further include a first conditioning block 220. The first adjustment block 220 is suitably connected to the first switch holding rail 212. As discussed further below, when the hold signal H is active, a second internal voltage V2 will be generated on the first switch hold rail 212. The first conditioning block 220 is further configured to receive a hold signal H at a second hold node 222, a tracking signal T at a second tracking node 224, and a reference voltage signal VREF at a reference voltage source 226. The first regulation block 220 is also connected to the first resistor 103 and the first capacitor 105 via the first node 211.

Circuit 200 also includes a second conditioning block 228. The second conditioning block 228 is suitably connected in parallel with the second gain stage 206 and the second capacitor 208 via a second node 229 and a third node 231. As discussed further below, when the first switch 210 is configured to track position (which, as will be appreciated, occurs when the tracking signal T is active), a first internal voltage V1 will be generated at the second node 229. The second conditioning block 228 is further configured to receive the hold signal H at a third hold node 230, the tracking signal T at a third tracking node 232, and the clamped voltage signal VCLAMP from a clamp source 234.

It should be appreciated that in the first combination of the first gain stage 204 and the first conditioning block 220 and the second combination of the second gain stage 206 and the second conditioning block 228, each conditioning block 220 and 228 acts as a respective voltage buffer. These buffers constrain each of the third internal voltage V3 at the first node 211 and the output voltage VOUT at the third node 231 such that the third internal voltage V3 follows the reference voltage signal VREF and the output voltage signal VOUT follows the clamped voltage signal VCLAMP, while providing the first internal voltage V2 to remain properly biased.

As shown in fig. 3, the second circuit 300 of the clamped controlled delay operational amplifier circuit according to at least one embodiment of the present disclosure comprises a first comparator ("Comp 1") 302, a second comparator ("Comp 2") 304, each of which is suitably connected to a first logic component 306, which is connected to a duplex output component 308. In at least one embodiment, the first logic component 306 outputs a signal resulting from the performance of a desired logical operation, which is designated herein as the logic signal L1. For at least one embodiment, the first logic 306 may be configured as a nand gate. However, it should be understood that other forms of logic components may be utilized as desired for any given embodiment of the present disclosure. Further, for at least one embodiment, the duplex output component 308 is a non-overlapping duplex output component that provides two output signals having opposite values (e.g., "high" versus "low", "active" versus "passive", or otherwise).

As further shown in fig. 3, the first comparator 302 is configured to receive the output voltage signal VOUT and the clamp voltage signal VCLAMP. Based on the comparison of these signals, when the output voltage signal is less than the clamped voltage signal, the first comparator 302 will output a negative (e.g., "0" value) first mode signal M1; otherwise, the first comparator 302 will output a positive (e.g., a "1" value) first mode signal M1, wherein a positive first mode signal indicates that output voltage clamping may be required.

Similarly, the second comparator 304 is configured to receive the reference voltage signal VREF and the input voltage signal VIN. Based on the comparison of these signals, the second comparator will output a positive (e.g., a "1" value) second mode signal M2 when the input voltage signal VIN is less than the reference voltage signal VREF. It should be appreciated that when both the first mode signal M1 and the second mode signal M2 are positive, the second circuit 300 instructs the first circuit 200 to perform clamping of the output voltage VOUT via the positive hold signal H.

Further, the first logic component 306 is configured to determine whether to output the first (e.g., high or positive) or second (e.g., low or negative) logic signal L1 based on the values of the first mode signal M1 and the second mode signal M2. It should be understood that "high"/"positive" and "low"/"negative" or other naming conventions may be used to designate the first and second values of logic signal L1. For at least one embodiment, the high logic signal L1 corresponds to a high tracking signal T. Further, based on the value of the logic signal L1, the second circuit 300 will output a high hold signal H or a high tracking signal T to the first circuit 200. As shown in the embodiment of fig. 3, the hold signal H will be "high" or positive when the inversion of the logical nand operation outputs a negative result. Conversely, when a logical nand operation outputs a positive result, the tracking signal T will be "high" or positive. As shown above with reference to fig. 2, the tracking signal T and the hold signal H configure the operation of the first switch 210 and, as discussed below with respect to fig. 4 and 5, the operation of the first and second conditioning blocks 220 and 228.

As shown in fig. 4 and 5 for at least one embodiment of the present disclosure, the track mode circuit 401 and the hold mode circuit 500 include a first conditioning block 220 that is further configured to include a fourth gain stage 402. For at least one embodiment, the fourth gain stage 402 provides an inverted output signal at a fourth gain stage output 420. The first conditioning block 220 may be configured to include a second switch 406 (also identified as "S2"), a third capacitor 404 having a third capacitance C3, and a fourth switch 410 (also identified as "S1").

Each of second switch 406 and fourth switch 410 may be a double throw switch having respective inputs 430 and 432, tracking rails 422 and 426 configured to facilitate a tracking mode of operation, and holding rails 424 and 428 configured to facilitate a holding mode of operation. The second switch tracking track 422 may be connected to the first terminal of the third capacitor 404 and the fourth gain stage input node 418 at a fourth node 438. The second switch holding rail 424 may also be connected to the first node 211. Second switch input 430 may be connected to fourth gain stage output node 420 at a fifth node 440, which is also connected to fourth switch holding rail 428. Fourth switched input 432 may be connected to a second terminal of third capacitor 404. Fourth switch tracking rail 426 may be connected to reference voltage source 226, where a reference voltage VREF is provided. The configuration of each of the second switch 406 and the fourth switch 410 is controlled by the opposite hold signal H and the tracking signal T, which are output by the second circuit 300 and shown in fig. 4 and 5 as being received at the respective nodes 222 ', 222 ", 224' and 224".

As further shown in fig. 4 and 5 for at least one embodiment of the present disclosure, the second conditioning block 228 is further configured to include a third gain stage 400. For at least one embodiment, the third gain stage 400 is configured to receive the output voltage signal VOUT at the third gain stage non-inverting input 412 via the third node 231 and the clamped voltage signal VCLAMP at the third gain stage inverting input 414. The third gain stage output 416 is connected to a third switching input 431. In accordance with at least one embodiment, the third switch 408 is a double throw switch configured to operate between a hold mode and a tracking mode based on which of the hold signal H and the tracking signal T is active at any given time. The third holding node 230 and the third tracking node 232 may be configured to receive the holding signal H and the tracking signal T output by the second circuit 300, respectively, to configure the third switch 408. Third switch 408 may be configured to include a third switch tracking track 436, which is suitably grounded via a ground node 442, and a third switch holding track 434 connected to second node 229.

In view of the circuit configurations of fig. 2-5, the operating principle of at least one embodiment of the present disclosure is as follows.

Tracking mode of operation

During the tracking mode, the first circuit 200, the first conditioning block 220, and the second conditioning block 228 are configured to provide a third circuit 401. As shown in fig. 4 with respect to the third circuit 401 implementation, the output voltage signal VOUT is less than the clamp voltage signal VCLAMP. This causes the first mode signal M1 to have a low value (e.g., zero), thereby causing the tracking signal T to have a high value (e.g., one). More specifically, during the tracking mode, the first gain stage 204 drives the second gain stage 206 via the first switch 210. Further, the configuration of the second switch 406 and the fourth switch 410 onto their respective tracking rails 422 and 426 isolates the third gain stage 400 from the main circuit. Likewise, the configuration of the third switch 408 onto the third switch tracking track 436 causes the third gain stage 400 to be effectively switched out to ground.

Furthermore, for at least one embodiment, the characteristics of the fourth gain stage 402 are ideally substantially the same as the characteristics of the second gain stage 206. Further, during the tracking mode, the third capacitor 404 is charged to a value occurring between the reference voltage signal VREF and the second internal voltage V2. It should be appreciated that if the fourth gain stage 402 is configured to generate a Direct Current (DC) operating point at the fourth gain stage input node 418 that is similar to the DC operating point generated at the second gain stage input 209, the first internal voltage V1 and the second internal voltage V2 will be approximately the same. Furthermore, it should be appreciated that when the hold mode is enabled, ground node 442 may advantageously be biased to nearly match the DC operating point at second gain stage input 209 and so that minimal delay will be encountered in stabilizing second gain stage 206 with the signal output by third gain stage 400.

Maintaining mode of operation

During the hold mode, the first circuit 200, the first conditioning block 220, and the second conditioning block 228 are configured to provide a fourth circuit 401. As shown in fig. 5 with respect to the fourth circuit 501 implementation, the output voltage signal VOUT is greater than or equal to the clamp voltage signal VCLAMP. In addition, the input voltage signal VIN is smaller than the reference voltage signal VREF. According to fig. 3, these conditions are such that both M1 and M2 have a high value and the tracking signal T has a low value, while the hold signal H has a high value. This enables the switches to be configured according to fig. 5, respectively.

More specifically, as shown in fig. 5, during the hold mode of operation, the first switch 210 isolates the first gain stage 204 from the second gain stage 206. Furthermore, the third gain stage 400 and the fourth gain stage 402 are now connected to the main circuit. In addition, the third capacitor 404 is connected via a fourth switch 410 to a fifth node 440-which, as described above, is connected to the fourth gain stage output 420. This configuration causes the third capacitor 404 to effectively act as a miller capacitor for the fourth gain stage 402. Further, the fourth gain stage 402 is then operated as another ("second") second gain stage via the arrangement of the first gain stage 204(a1) and the fourth gain stage 402(a 4). Furthermore, since the third capacitor 404 has been substantially pre-charged during the tracking mode, insignificant and/or minimal disturbances occur in the third internal voltage V3 generated at the first node 211. It should be appreciated that the amplifier of the effectively generated a1-a4 combination operates as a first voltage follower amplifier driven by the reference voltage signal VREF with respect to the first node 211. Similarly, the configuration of the first switch 210 and the third switch 408 as shown in fig. 5 effectively produces the second gain stage 206(a2) and the third gain stage 400(A3), which also effectively operate as a second voltage follower amplifier at the second node 229, with the clamp voltage signal VCLAMP acting as the second input voltage signal.

Switching modes

During the transition mode, the first circuit 200 transitions between a retention mode of operation and a tracking mode of operation. For at least one embodiment, such a transition occurs between the fourth/hold mode circuit 501 of FIG. 5 and the third/track mode circuit 401 of FIG. 4. Furthermore, it should be understood that according to the embodiments shown in fig. 2, 4, and 5, such transitions occur when the input voltage signal VIN is greater than the reference voltage signal VREF. According to the second circuit 300 of fig. 3, this condition causes M2 to have a low value, thereby causing the tracking signal T to have a high value and the hold signal H to have a low value. It should be appreciated that since the third and fourth gain stages 400, 402 are biased together with the third capacitor 404 during each mode of operation in order to minimize any settling transients, a transition between the clamping mode and the tracking mode may occur in order to provide a fast response-as defined above. Further, it should be appreciated that when the third and fourth gain stages 400, 402 are properly biased (as one of ordinary skill in the art would be able to accomplish such operation), the settling time will depend primarily on the response times associated with the first and second comparators 302, 304.

In fig. 6, an operational response of a circuit configured according to at least one embodiment of the present disclosure is shown. As shown, the comparator delay time tCD determines the amount of delay that occurs between transitions from the hold mode to the track mode.

It should be understood that as used herein with respect to at least one embodiment of the present disclosure, the "hold" mode corresponds to a first mode of operation in which the output voltage signal VOUT is clamped at a voltage potential specified by the clamp voltage signal VCLAMP for at least one embodiment of the first circuit 200 and/or the fourth/hold mode circuit 501. Conversely, the "tracking" mode corresponds to a second mode of operation, wherein for embodiments of at least the first circuit 200 and/or the third/tracking mode circuit 401, the system operates in a steady state manner, wherein the output voltage signal VOUT is increased or decreased accordingly based on the presence or absence of the input voltage signal VIN (while performing an integration function for at least one embodiment), and the time required to re-bias the first gain stage 204 in the clamped mode of operation is substantially independent of the RC time constant, but substantially dependent primarily on any delays that occur based on operational constraints of the first comparator 302 and/or the second comparator 304 of the second circuit 300.

Although various embodiments of the claimed invention have been described above with a certain degree of particularity, or with reference to one or more individual embodiments, those skilled in the art could make numerous alterations to the disclosed embodiments without departing from the spirit or scope of the claimed invention. The use of the terms "about," "about," or "substantially" means that the value of an element has a parameter that is expected to be close to the stated value or position. However, as is well known in the art, there may be slight variations that prevent a value from being exactly equal to a stated value. Thus, it is expected that differences, such as a 10% difference, would be reasonable differences that would be expected and known by one of ordinary skill in the art, and are acceptable with respect to the stated or desired goal of one or more embodiments of the present disclosure. It should also be understood that the terms "top" and "bottom," "left" and "right," "upper" and "lower," "first," "second," "front," "rear," and other similar terms are used for descriptive and reference purposes only and are not intended to be limiting to any orientation or configuration of any element or any sequence of operations of various embodiments of the present disclosure. Furthermore, the terms "and" or "are not intended to be used in a limiting or expanding sense, and cover any possible range of combinations of elements and operations of embodiments of the present disclosure. Other embodiments are therefore contemplated. It is intended that all matter contained in the above description and shown in the accompanying drawings shall be interpreted as illustrative only of the embodiments and not limiting. Changes in detail or structure may be made without departing from the basic elements of the invention as defined in the appended claims.

For at least one embodiment, a first conditioning block [220] for a controlled delay operational amplifier may include a fourth node [438] coupled to a first switch holding rail [212 ]; a third capacitor [404] coupled between the fourth node [438] and the fourth switch [432 ]; wherein the fourth node [438] is coupled to the first switch [210 ]; wherein the fourth switch [410] comprises: a fourth switch input node [432] coupled to the third capacitor [404 ]; a fourth switch tracking track [426] coupled to a reference voltage node [226] that provides a reference voltage [ VREF ]; and a fourth switch holding rail [428] coupled to a fifth node [440 ]; a second switch [406], the second switch comprising: a second switch input node [430] coupled to a fifth node [440 ]; a second switch tracking track [422] coupled to a fourth node [438 ]; and a second switch holding rail [424] coupled to the operational amplifier [202 ]; a fourth gain stage [402], the fourth gain stage comprising: a fourth gain stage input node [418] coupled to a fourth node [438 ]; and a fourth gain stage output node [420] coupled to a fifth node [440 ]; wherein the second switch [406] selectively couples the fourth gain stage [402] to one of the fourth node [438] or the operational amplifier [202] by pulling to one of the second switch tracking rail [422] and the fourth switch holding rail [424], respectively, based on whether the tracking signal [ T ] or the holding signal [ H ] has a positive value; and wherein the fourth switch [410] selectively couples the third capacitor [404] to one of the reference voltage node [226] or the fifth node [440] by pulling to one of the fourth switch tracking rail [426] and the fourth switch holding rail [428], respectively, based on whether the tracking signal [ T ] or the hold signal [ H ] has a positive value.

For at least one implementation, the second conditioning block [228] for the controlled delay operational amplifier may comprise: a third switch [408], the third switch comprising: a third switch input [431 ]; a third switch coupled to ground [442] to track the track [436 ]; and a third switch holding track [434] coupled to the second node [229 ]; and a third gain stage [400] coupled to the second gain stage [206] and to a third switching input [431 ]; wherein the third switch [408] selectively couples the third gain stage [400] to one of ground [442] or second node [229] by pulling to one of a third switch tracking track [436] and a third switch hold track [434], respectively, based on whether the tracking signal [ T ] or the hold signal [ H ] has a positive value.

For at least one implementation, a first gain stage [204] for a clamped controlled delay operational amplifier may comprise: a non-inverting input node [201 ]; an inverting input node [203] coupled to a reference voltage [ VREF ] source [226 ]; and an output node [205] coupled to the first switch [210 ].

For at least one embodiment, a first circuit [200] for a controlled delay operational amplifier may include a first resistor [103] coupled between a source of an input voltage [ VIN ] and a non-inverting input node [201] at a first node [211 ]; and a first capacitor [105] coupled to the first node [211] and the third node [231 ].

For at least one implementation of the clamped controlled delay operational amplifier, the second capacitor [208] used may be a miller compensation capacitor; and the integration clamped controlled delay operational amplifier may be formed by an RC circuit formed by the first circuit [202], the first resistor [203] and the first capacitor [105 ]; and the controlled delay may be generated based on a response time associated with at least one of the comparator [302] and the second comparator [304 ].

For at least one implementation of the clamped controlled delay operational amplifier of claim 12, each of the clamping voltage and the reference voltage used therewith may be predetermined.

For at least one implementation of the method of using a clamped controlled delay operational amplifier, wherein the clamped controlled delay operational amplifier comprises: a first conditioning block [220], the first conditioning block comprising: a fourth switch [410] having a fourth switch input node [432] coupled to the third capacitor [404], a fourth switch tracking rail [426] coupled to a reference voltage node [226] providing a reference voltage [ VREF ], a fourth switch holding rail [428] coupled to a fifth node [440 ]; wherein the third capacitor [404] is coupled between the fourth node [438] and the fourth switch [432 ]; a second switch [406] having a second switch input node [430] coupled to a fifth node [440], a second switch tracking rail [422] coupled to a fourth node [438], and a second switch holding rail [424] coupled to the first circuit [202 ]; a fourth gain stage [402] having a fourth gain stage input node [418] coupled to a fourth node [438], and a fourth gain stage output node [420] coupled to a fifth node [440 ]; wherein the second switch [406] selectively couples the fourth gain stage [402] to one of the fourth node [438] or the operational amplifier [202] by pulling to one of the second switch tracking rail [422] and the fourth switch holding rail [424], respectively, based on whether the tracking signal [ T ] or the holding signal [ H ] has a positive value; and wherein the fourth switch [410] selectively couples the third capacitor [404] to one of the reference voltage node [226] or the fifth node [440] by pulling to one of the fourth switch tracking rail [426] and the fourth switch holding rail [428], respectively, based on whether the tracking signal [ T ] or the hold signal [ H ] has a positive value.