阅读说明：本技术 一种用于锁相环的转换电路以及形成转换电路的方法 (Conversion circuit for phase-locked loop and method for forming conversion circuit ) 是由 金松正幸 于 2019-07-09 设计创作，主要内容包括：本发明涉及一种用于锁相环的转换电路以及形成转换电路的方法。在一个实施方案中,本发明公开了一种差分到单端转换电路,所述差分到单端转换电路被配置为在不使用运算放大器的情况下和在不使用电流源对电容器充电的情况下将差分信号转换为单端信号。(The invention relates to a conversion circuit for a phase locked loop and a method of forming a conversion circuit. In one embodiment, a differential to single-ended conversion circuit is configured to convert a differential signal to a single-ended signal without using an operational amplifier and without using a current source to charge a capacitor.)

1. A conversion circuit for a phase locked loop, the conversion circuit comprising:

a first signal input configured to receive a first portion of a differential signal from a differential loop filter and a second signal input configured to receive a second portion of the differential signal from the differential loop filter;

inputting a power supply;

a common loop input;

a first capacitor having a first terminal coupled to a common mode node, the first capacitor having a second terminal;

a second capacitor having a first terminal coupled to the common mode node, the second capacitor having a second terminal;

a first switch having a first terminal coupled to the first signal input and having a second terminal coupled to the second terminal of the first capacitor;

a second switch having a first terminal coupled to the first signal input and having a second terminal coupled to the second terminal of the second capacitor;

a third switch having a first terminal coupled to the second signal input and having a second terminal coupled to the common mode node;

a fourth switch having a first terminal coupled to the power supply input and having a second terminal coupled to the second terminal of the first capacitor;

a fifth switch having a first terminal coupled to the common loop input and having a second terminal coupled to the second terminal of the second capacitor;

a sixth switch having a first terminal coupled to the common mode node and a second terminal coupled to an output node of the conversion circuit; and

a control circuit configured to enable the first, second, and third switches substantially simultaneously and to disable the first, second, and third switches substantially simultaneously, the control circuit configured to enable the fourth, fifth, and sixth switches substantially simultaneously and to disable the fourth, fifth, and sixth switches substantially simultaneously, wherein the control circuit enables the fourth, fifth, and sixth switches in a substantially non-overlapping manner with respect to the enabling of the first, second, and third switches.

2. The conversion circuit of claim 1, further comprising an output capacitor coupled between the output node and the common loop input.

3. The conversion circuit of claim 1, wherein the conversion circuit is not provided with an operational amplifier.

4. The conversion circuit of claim 1, wherein the conversion circuit is free of a current source.

5. A method of forming a conversion circuit for a phase locked loop, the method comprising:

forming a first input and a second input to receive a differential signal from a differential loop filter;

forming a first conversion capacitor coupled to a second conversion capacitor;

configuring the conversion circuit to selectively charge the first conversion capacitor and the second conversion capacitor to the value of the differential signal; and

the switching circuit is configured to then selectively couple the first and second switching capacitors in series and to selectively couple a reference voltage in parallel with the first and second switching capacitors.

6. The method of claim 5, wherein configuring the conversion circuit to selectively charge the first and second conversion capacitors comprises configuring the conversion circuit to selectively couple the first and second conversion capacitors in parallel with the differential signal.

7. The method of claim 5, wherein configuring the conversion circuit to thereafter selectively couple the first conversion capacitor and the second conversion capacitor in series comprises configuring the conversion circuit to selectively couple a supply voltage in parallel with the first conversion capacitor and the second conversion capacitor.

8. The method of claim 5, wherein configuring the conversion circuit to then selectively couple the first conversion capacitor and the second conversion capacitor in series comprises: a first terminal of the first conversion capacitor is coupled to a first terminal of the second conversion capacitor, the reference voltage is selectively coupled to a second terminal of the first conversion capacitor, and a second terminal of the second conversion capacitor is selectively coupled to a common return of the reference voltage.

9. The method of claim 5, further comprising coupling a first switch between the first input and a conversion node commonly coupled to a first terminal of the first conversion capacitor and a first terminal of the second conversion capacitor.

10. A method of forming a conversion circuit for a phase locked loop that converts a differential signal to a single-ended signal, the method comprising:

providing an input to receive a differential signal from a differential loop filter;

configuring the conversion circuit to store values of the differential signal to form a stored signal; and

the conversion circuit is configured to add a portion of a value of a reference signal to the stored signal to form a single-ended output signal.

Technical Field

The invention relates to a conversion circuit for a phase locked loop and a method of forming a conversion circuit.

Background

The present invention relates generally to electronic devices and, more particularly, to semiconductors, semiconductor structures, and methods of forming semiconductor devices.

In the past, the electronics industry utilized various circuits and methods to form Phase Locked Loop (PLL) systems. PLL systems typically include a differential loop filter that provides a differential signal as an output. The system may also include a differential amplifier that converts differential signals to single-ended signals for use within the system. The differential amplifier may also amplify differential signals while forming single-ended signals.

The differential amplifier is typically formed on the semiconductor device along with the rest of the PLL. However, the differential amplifier occupies a large area of the semiconductor die on which the semiconductor device is formed. The large area results in higher cost of the semiconductor device.

Accordingly, it is desirable to have a differential to single-ended signal conversion apparatus for a PLL that has a small area and/or occupies a small area of a semiconductor die.

Disclosure of Invention

In one embodiment of the present invention, a switching circuit for a phase locked loop is provided. The conversion circuit includes: a first signal input configured to receive a first portion of a differential signal from a differential loop filter and a second signal input configured to receive a second portion of the differential signal from the differential loop filter; inputting a power supply; a common loop input; a first capacitor having a first terminal coupled to a common mode node, the first capacitor having a second terminal; a second capacitor having a first terminal coupled to the common mode node, the second capacitor having a second terminal; a first switch having a first terminal coupled to the first signal input and having a second terminal coupled to the second terminal of the first capacitor; a second switch having a first terminal coupled to the first signal input and having a second terminal coupled to the second terminal of the second capacitor; a third switch having a first terminal coupled to the second signal input and having a second terminal coupled to the common mode node; a fourth switch having a first terminal coupled to the power supply input and having a second terminal coupled to the second terminal of the first capacitor; a fifth switch having a first terminal coupled to the common loop input and having a second terminal coupled to the second terminal of the second capacitor; a sixth switch having a first terminal coupled to the common mode node and a second terminal coupled to an output node of the conversion circuit; and a control circuit configured to enable the first, second, and third switches substantially simultaneously and to disable the first, second, and third switches substantially simultaneously, the control circuit configured to enable the fourth, fifth, and sixth switches substantially simultaneously and to disable the fourth, fifth, and sixth switches substantially simultaneously, wherein the control circuit enables the fourth, fifth, and sixth switches in a substantially non-overlapping manner with respect to the enabling of the first, second, and third switches.

According to another embodiment of the present invention, there is provided a method of forming a conversion circuit for a phase-locked loop, including: forming a first input and a second input to receive a differential signal from a differential loop filter; forming a first conversion capacitor coupled to a second conversion capacitor; configuring the conversion circuit to selectively charge the first conversion capacitor and the second conversion capacitor to the value of the differential signal; and configuring the switching circuit to then selectively couple the first and second switching capacitors in series and to selectively couple a reference voltage in parallel with the first and second switching capacitors.

According to yet another embodiment of the present invention, there is provided a method of forming a conversion circuit for a phase locked loop that converts a differential signal to a single-ended signal, including: providing an input to receive a differential signal from a differential loop filter; configuring the conversion circuit to store values of the differential signal to form a stored signal; and configuring the conversion circuit to add a portion of the value of the reference signal to the stored signal to form a single-ended output signal.

Drawings

Fig. 1 schematically illustrates a phase-locked loop (PLL) system according to the present invention, the PLL system including a differential to single-ended signal conversion circuit;

fig. 2 schematically illustrates an example of an embodiment of a differential signal to single-ended signal conversion circuit according to the present invention, which may have an embodiment of an alternative embodiment of the differential to single-ended signal conversion circuit of fig. 1;

FIG. 3 is a graph having plots illustrating examples of some embodiments of control signals that may be formed by the differential to single-ended signal conversion circuit of FIG. 2, in accordance with the present invention; and is

Fig. 4 shows an enlarged plan view of a semiconductor device according to the present invention, which includes at least the differential to single-ended signal conversion circuit of fig. 1 or fig. 2.

Elements in the figures are not necessarily to scale, some elements may be exaggerated for illustrative purposes and, unless otherwise specified, like reference numerals in different figures denote like elements. Moreover, descriptions and details of well-known steps and elements may be omitted for simplicity of the description. As used herein, current carrying element or current carrying electrode means an element of a device that carries current through the device, such as a source or drain of an MOS transistor or an emitter or collector of a bipolar transistor or a cathode or anode of a diode, while a control element or control electrode means an element of a device that controls current through the device, such as a gate of an MOS transistor or a base of a bipolar transistor. In addition, one current carrying member may carry current through the device in one direction, such as carrying current into the device, while a second current carrying member may carry current through the device in the opposite direction, such as carrying current out of the device. Although the devices may be described herein as certain N-channel or P-channel devices or certain N-type or P-type doped regions, one of ordinary skill in the art will appreciate that complementary devices according to the present invention are also possible. It is understood by those of ordinary skill in the art that conductivity type refers to the mechanism by which conduction occurs, such as through holes or electrons, and thus, conductivity type does not refer to the doping concentration but to the doping type, such as P-type or N-type. It will be understood by those skilled in the art that the terms "during … …", "at … … simultaneously", and "when … …" as used herein in relation to circuit operation do not mean exactly that an action is said to occur immediately after the action is initiated, but that there may be some minor but reasonable delay, such as various propagation delays, between the reactions initiated by the initial action. Additionally, the term "simultaneously at … …" means that some action occurs at least for a period of time during the duration of the trigger action. Use of the word "approximately" or "substantially" means that the value of an element has a parameter that is expected to be close to the stated value or position. However, as is well known in the art, there are always minor differences that prevent a value or position from being exactly the stated value or position. It is recognized in the art that deviations of up to at least ten percent (10%) (and up to twenty percent (20%) for some components including semiconductor dopant concentrations) are reasonable deviations from the ideal target exactly as described. When used with respect to signal states, the term "active" means an active state of a signal, and the term "inactive" means an inactive state of a signal. The actual voltage value or logic state of a signal (such as a "1" or "0") depends on whether positive or negative logic is used. Thus, if positive logic is used, high voltage or high logic can be asserted, and if negative logic is used, low voltage or low logic can be asserted; whereas a low voltage or low state may fail if positive logic is used, and a high voltage or high logic may fail if negative logic is used. In this context, a positive logic convention is used, but those skilled in the art will appreciate that a negative logic convention may also be used. The terms "first," "second," "third," and the like in the claims and/or in the detailed description, as used in portions of the names of elements, are used for distinguishing between similar elements and not necessarily for describing a sequential or chronological order, spatial order, hierarchical order, or any other order. It is to be understood that the terms so used are interchangeable under appropriate circumstances and that the embodiments described herein are capable of operation in other sequences than described or illustrated herein. Reference to "one embodiment" or "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the invention. Thus, the appearances of the phrase "in one embodiment" appearing in various places throughout the specification are not necessarily all referring to the same embodiment, but in some instances may. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments, as would be apparent to one of ordinary skill in the art. For clarity of illustration, the doped regions of the device structure are shown as having substantially straight edges and precisely angled corners. However, those skilled in the art understand that due to the diffusion and activation of dopants, the edges of the doped regions may not typically be straight lines and the corners may not be precisely angled.

The embodiments illustrated and described as appropriate below may lack any elements not specifically disclosed herein and/or may be practiced in the absence of any element not specifically disclosed herein.

Detailed Description

Fig. 1 schematically illustrates a phase-locked loop (PLL) system 10 that includes a differential to single-ended signal conversion circuit, or conversion circuit 26. The system 10 includes a voltage controlled oscillator circuit or VCO 29 that forms an oscillating signal 30 on an output of the VCO 29. A frequency divider circuit, or divider circuit 32, divides the frequency of the signal 30 to form a divided signal 33 that is representative of the signal 30 but divided by a division ratio (1/N) set by the circuit 32. Thus, divided signal 33 has a frequency that is a divisor of the frequency of signal 30. The system 10 also includes a phase/frequency detection circuit, or PFD circuit 14, which receives the source signal 13 on a first input of the circuit 14. In some embodiments, the system 10 may include an optional frequency divider circuit 12 that divides (1/M) the source signal 13 before the source signal is received by the PFD circuit 14. Circuit 14 also receives a divided signal 33 on a second input and generates a pulse indicating that the frequency of signal 30 should be increased or decreased. The PFD circuit 14 compares the phase of the source signal 13 with the phase of the divided signal 33 and forms a rising pulse on output 15 and a falling pulse on output 16. In one embodiment, the rising pulse and the falling pulse may be voltage pulses. The differential charge pump circuit, or DCP circuit 18, receives the voltage pulses and converts the voltage pulses into current pulses. For example, a pulse on output 19 may indicate that the frequency of VCO 29 should be increased and a pulse on output 20 may indicate that the frequency of VCO 29 should be decreased.

A differential loop filter circuit, or DLF 22, may be configured to filter the current pulses and convert the current pulses to a voltage. For example, DLF 22 may include one or more low pass filters that filter the pulses to form a more slowly varying signal. The low pass filter function removes high frequency components of the signals received from outputs 19 and 20, which minimizes spurious changes in the frequency of signal 30. DLF 22 may have an output 23 having an analog signal that increases in value in response to current pulses received from output 19 of DCP circuit 18 and may decrease in value in response to pulses received from output 20 of DCP circuit 18. DLF 22 may also have an output 24 having an analog signal that may increase in value in response to receiving a current pulse from output 20 of DCP18 and may decrease in value in response to receiving a current pulse from output 19 of DCP 18. Thus, embodiments of DLF 22 may include that outputs 23 and 24 may form a differential signal indicating whether the frequency of VCO 29 should be increased or decreased. Those skilled in the art will appreciate that differential signals are formed as two complementary signals transmitted on two separate conductors. The information in the two signals is the difference between the values of the voltage or current on the two conductors, rather than the difference between the potential on the conductors and ground or a common reference potential.

Conversion circuit 26 receives the differential signals from outputs 23 through 24 and forms a single-ended signal 27 having values representative of the differential values of the signals on outputs 23 through 24. The information in signal 27 is a value, such as a current value or a voltage value, of a signal related to a common loop, such as a ground reference. Signal 27 may be used to control VCO 29 to increase or decrease the frequency of signal 30. In one embodiment, circuit 26 does not include a current source for charging the capacitor, and does not include any type of current source. Embodiments of circuit 26 also do not include a differential amplifier or any type of operational amplifier (packaged as an amplifier configured as an integrator or summing element). Circuit 26 may have a transfer function that may affect the operation of DLF 22 or may affect the stability of system 10. Therefore, the transfer function should be considered in designing the DLF 22. An embodiment of circuit 26 may be comprised of switched capacitors.

The circuit 26 may receive operating power supplied between the power terminal 35 and the common return terminal 36. Embodiments of VCO 29 may also be connected to receive operating power supplied between terminals 35 through 36. The voltage applied between terminals 35 and 36 may sometimes be referred to as a supply voltage, or operating voltage, or Vcc, or Vdd. The common return voltage on terminal 36 is typically low and provides a return for the voltage supplied to terminal 35. The potential applied to terminal 36 may be referred to as ground, or ground potential, or Vss, for example. For simplicity of explanation, the potential applied between the terminals 35 to 36 will be referred to as an operating voltage and abbreviated Vd. In one embodiment, the operating voltage (Vd) applied between terminals 35 and 36 may also be used as the operating voltage to operate PFD14, DCP18, and DLF 22.

Fig. 2 schematically illustrates an example of an embodiment of a differential signal to single-ended signal conversion circuit 40, which may have an embodiment that is an alternative embodiment to circuit 26 of fig. 1. Circuit 40 includes differential inputs including inputs 45 and 46 configured to receive differential signals. Embodiments may include inputs 45-46 configured to receive differential signals from outputs 23-24 of DLF 22. These two signals are shown in fig. 2 as signal S + and signal S-. The value of signal S + relative to signal S-is referred to as value S and is shown by the arrow representing the voltage of signal S, where the arrow has a positive value relative to signal S-.

Circuit 40 includes an output 66 that provides a single-ended signal 27 having a value representative of the differential value of the differential signal. A power input terminal 42 of circuit 40 is commonly connected to terminal 35 and a common return terminal 43 is commonly connected to terminal 36. Therefore, the operating voltage Vd is applied between the terminals 42 and 43. Circuit 40 also includes transfer capacitors 57 and 58, each having a first terminal commonly connected to transfer node 68, to a first terminal of output switch 55, and to a first terminal of input switch 50. A second terminal of switch 50 is connected to input 45. A second terminal of capacitor 57 is commonly connected to a first terminal of switch 53 and to a first terminal of input switch 48. A second terminal of switch 48 is connected to input 46 and a second terminal of switch 53 is connected to terminal 42. A second terminal of capacitor 58 is commonly connected to a first terminal of switch 54 and to a first terminal of input switch 49. A second terminal of switch 49 is connected to input 46 and a second terminal of switch 54 is connected to terminal 43. Input switch 50 is configured to selectively couple input 45 to switching node 68 and thus to the first terminals of capacitors 57-58. Input switch 48 is configured to selectively couple a second terminal of capacitor 57 to input 46, and input switch 49 is configured to selectively couple input 46 to a second terminal of capacitor 58. The output switch 55 is configured to selectively couple the transfer node 68 to the output node 62 and to the capacitor 61 so as to store the value of the one-terminal signal on the capacitor 61. Thus, the second terminal of switch 55 is connected to node 62.

Control circuit 70 of circuit 40 is configured to selectively enable or close switches 48-50 during the time that switches 53-55 are disabled or open in order to selectively charge each of capacitors 57 and 58 to the value S of the differential signal received between inputs 45 and 46. For example, circuit 70 may be configured to assert signal 71 and negate signal 72. Enabling switches 48-50 charges each of capacitors 57-58 to a value S when switches 53-55 are disabled, as indicated by arrows 56 and 59. Note that the plate of each of the capacitors 57 and 58 connected to the node 68 has a positive potential, while the opposite plate has a negative potential, as indicated by arrows 56 and 59. The control circuit 70 is configured to then disable the switches 48 to 50 while the switches 53 to 55 remain disabled. For example, circuit 70 may deactivate signal 71 and keep signal 72 inactive.

The controller 70 is configured to then enable the switches 53 to 55 while disabling the switches 48 to 50. For example, controller 70 may keep signal 71 inactive and may assert signal 72. Enabling or closing the switches 53-54 connects the capacitors 57-58 in series with the voltage Vd. Since the series-connected capacitors function as a voltage divider, a voltage approximately equal to half the value of the voltage Vd is combined with the voltage S that has been stored on the capacitors 57 to 58. Since the switch 53 connects the negatively charged plate of the capacitor 57 to the voltage Vd, the voltage stored on the capacitor 57 in the direction shown by arrow 56 becomes half the voltage S minus the voltage Vd (S-0.5 Vd). However, the positively charged plate of the capacitor 58 receives the voltage, such that the capacitor 58 is charged in the direction of arrow 59 to a value of the voltage S plus half of the voltage Vd (S +0.5 Vd). The voltage on the conversion node 68 relative to the voltage on terminal 43 is the same as the voltage stored on capacitor 58. Since the switch 55 is also enabled, the voltage of the capacitor 58 (S +0.5Vd) is stored on the capacitor 61 and applied to the output node 62. Thus, the single-ended signal 27 has a value of the signal S that varies around a common mode voltage of about 0.5 Vd.

Subsequently, the switches 53 to 55 are disabled, so that the voltage on the output node 62 remains at the value (S +0.5 Vd). Thereafter, the switches 48 to 50 may be enabled again to store the value S of the differential signal on the capacitors 57 to 58. Since switch 55 remains open, charging capacitors 57-58 does not affect the voltage on output node 62.

In some embodiments, output node 62 may serve as an output to form signal 27. In other embodiments, circuit 40 may include an optional buffer that receives a signal from output node 62 and forms a signal representative of the signal on output 27. Such a buffer prevents loading from affecting the value of the single-ended signal. In some embodiments, the buffer may be a follower circuit, such as a source follower. An example of an embodiment of a source follower may include transistor 65 and resistor 64. Embodiments may include a source of transistor 65 connected to output 66 and to a first terminal of a resistor 64 having a second terminal connected to terminal 43. A drain of transistor 65 may be connected to terminal 42 and a gate of transistor 65 may be connected to node 62.

Those skilled in the art will appreciate that the voltage between terminals 42 and 43 may be other voltages such as a reference voltage, rather than an operating voltage or a supply voltage, so long as the sum of about half the value of the voltage plus the value S is less than the value of the supply voltage or the operating voltage.

Fig. 3 is a graph having plots illustrating an example of an implementation of control signals 71 and 72 formed by controller 70. The abscissa indicates time and the ordinate indicates an increasing value of the signal shown. Curve 75 shows the value of signal 71 and curve 76 shows the value of signal 72. Assume that at time T0, signals 71 and 72 are both inactive, such that switches 48 through 50 and 53 through 55 are all disabled or open. At time T1, controller 70 is configured to assert signal 71 to enable or close switches 48-50 while signal 72 remains inactive such that switches 53-55 remain disabled. Thus, the capacitors 57 to 58 are charged to the value S of the signal received between the inputs 45 to 46. At time T2, controller 70 is configured to deactivate signal 71 to disable switches 48 to 50, while signal 72 remains inactive. Subsequently, at time T3, the controller 70 is configured to assert the signal 72 to enable the switches 53-55 to connect the capacitors 57-58 in series with the voltage Vd. Note that controller 70 is configured to leave an interval between times T2 and T3, where both switches 71 and 72 are disabled, to ensure that switches 48-50 are fully disabled before switches 53-55 are enabled. Subsequently, at time T4, controller 70 deasserts signal 72 to disable switches 53 through 55. Thereafter, at time T5, the cycle begins again by asserting signal 71. Note that there is a gap between T4 and T5 in which both control signals 71 and 72 are inactive, such that switches 48 through 50 and 53 through 55 are all disabled. The width of the interval between times T1 and T2 depends on the value of S and the capacitances of capacitors 57 through 58. The interval between time T3 and T4 also depends on the capacitance of capacitors 58 and 61. Embodiments of circuit 40 may include an oscillator to help form signals 71 and 72.

In some embodiments, signal 72 may control only switches 53-54, and controller 70 may have a third control signal that enables switch 55 after disabling switches 53 and 54 and while switches 48-50 are also disabled.

Circuitry 40 is configured to convert differential signals received on inputs 45 and 46 to single-ended signals on output 27, or alternatively single-ended signals on node 62. The circuit 40 is configured without a current source to charge the capacitor to different values. The circuit 40 is also configured without any type of differential amplifier or operational amplifier (including amplifiers configured as integrators or summing elements). Thus, circuit 40 uses less area on the semiconductor die than other types of conversion circuits including amplifiers or current sources, thereby reducing the cost of the circuit and reducing the cost of a phase-locked loop system utilizing circuit 40.

Accordingly, the circuit 40 is configured to receive the differential signal from the differential loop filter and store the value of the differential signal. The circuit 40 is configured to then add a portion of the value of the reference signal to the stored signal to form a single-ended signal.

Fig. 4 shows an enlarged plan view of a portion of an embodiment of a semiconductor device or integrated circuit 90 formed on a semiconductor die 91. In one embodiment, circuit 26 or 40 may be formed on die 91. Any of circuits 14, 18, 22, and/or 20 may also be formed on die 91. To simplify the drawing, die 91 may also include other circuitry not shown in fig. 4.

From all of the foregoing, those skilled in the art will appreciate that the conversion circuit for a phase locked loop may include:

a first signal input, such as input 45, configured to receive a first portion of the differential signal from the differential loop filter, and a second signal input, such as input 46, configured to receive a second portion of the differential signal from the differential loop filter;

a power input, such as input 42;

a common loop input, such as input 43;

a first capacitor having a first terminal coupled to a common mode node, such as node 59, the first capacitor having a second terminal;

a second capacitor, such as capacitor 58, having a first terminal coupled to the common mode node, the second capacitor having a second terminal;

a first switch, such as switch 48, having a first terminal coupled to the first signal input and having a second terminal coupled to the second terminal of the first capacitor;

a second switch, such as switch 49, having a first terminal coupled to the first signal input and having a second terminal coupled to the second terminal of the second capacitor;

a third switch, such as switch 50, having a first terminal coupled to the second signal input and having a second terminal coupled to the common mode node;

a fourth switch (53) having a first terminal coupled to the power input and having a second terminal coupled to the second terminal of the first capacitor;

a fifth switch having a first terminal coupled to the common loop input and having a second terminal coupled to the second terminal of the second capacitor;

a sixth switch, such as switch 55, having a first terminal coupled to the common mode node and a second terminal coupled to an output node of the conversion circuit, such as node 62; and

a control circuit, such as circuit 70, configured to enable the first, second, and third switches substantially simultaneously and to disable the first, second, and third switches substantially simultaneously, is configured to enable the fourth, fifth, and sixth switches substantially simultaneously and to disable the fourth, fifth, and sixth switches substantially simultaneously, wherein the control circuit enables the fourth, fifth, and sixth switches in a substantially non-overlapping manner with respect to the enabling of the first, second, and third switches.

Another exemplary embodiment may also include an output capacitor, such as capacitor 61, coupled between the output node and the common loop input.