阅读说明：本技术 多路复用的σ-δ模数转换器 (Multiplexed sigma-delta analog-to-digital converter ) 是由 Y·J·沙玛 A·J·卡尔布 于 2019-08-23 设计创作，主要内容包括：本公开涉及多路复用的Σ-Δ模数转换器。具有模拟环路滤波器电路的Σ-ΔADC电路可以通过刷新模拟环路滤波器积分器和数字抽取滤波器的存储器在不同输入之间进行多路复用,并为其填充当前输入的新数据。然而,相对于采样频率,填充存储器可能是慢的,因为必须在生成有意义的输出数据之前建立关于过去历史的信息。因此,使用Σ-ΔADC电路的信道之间的复用率可以通过这种存储器刷新而减慢。描述了可以克服这些问题的多路复用Σ-ΔADC电路,以便能够支持多个信道的逐周期采样。这些技术可以提供快速的Σ-Δ模数转换器(ADC)电路,其面积小并且可以动态地在多个信道上复用。(The present disclosure relates to a multiplexed sigma-delta analog-to-digital converter. A sigma-delta ADC circuit with an analog loop filter circuit may multiplex between different inputs and fill it with new data of the current input by refreshing the memories of the analog loop filter integrator and the digital decimation filter. However, filling the memory can be slow relative to the sampling frequency, as information about the past history must be built before meaningful output data is generated. Thus, the multiplexing rate between channels using sigma-delta ADC circuits may be slowed by such memory refresh. A multiplexed sigma-delta ADC circuit is described that can overcome these problems so as to be able to support cycle-by-cycle sampling of multiple channels. These techniques may provide fast sigma-delta analog-to-digital converter (ADC) circuits that are small in area and may be dynamically multiplexed over multiple channels.)

1. A multiplexed multi-channel sigma-delta (SD) analog-to-digital converter (ADC) circuit, comprising:

a shared analog circuit configured to receive a selected one of a plurality of analog input signals, the shared analog circuit comprising:

an ADC circuit coupled to an input of the analog circuit; and

a digital-to-analog converter (DAC) circuit configured to provide an analog feedback signal to an input of the analog circuit; and

a plurality of digital channels coupled to outputs of the shared analog circuit and DAC circuit, each of the plurality of digital channels configured to generate a digital output signal representative of a respective one of the analog input signals.

2. The SD ADC circuit of claim 1, further comprising:

a gain amplifier circuit coupled to an input of the ADC circuit and configured to receive and amplify a difference between an output of the DAC circuit and one of the received analog input signals;

a first chopping switch circuit coupled to an input of the gain amplifier circuit; and

a second chopping switch circuit coupled to an output of the gain amplifier circuit.

3. The SD ADC circuit of claim 2, further comprising:

a first multiplexer circuit coupled to an input of the analog circuit and configured to select one of the plurality of analog input signals;

a second multiplexer circuit coupled to an input of the DAC circuit and each of the plurality of digital channels;

a digital demultiplexer circuit coupled to an output of the analog circuit and each of the plurality of digital channels, the demultiplexer circuit configured to select one of a plurality of digital circuits to receive the output of the analog circuit; and

a controller circuit configured to:

controlling operation of the first and second multiplexer circuits and the demultiplexer circuit; and

controlling the operation of the first and second chopping switches.

4. The SD ADC of claim 3 wherein the controller circuit is configured to control operation of the demultiplexer circuit to select the plurality of digital channels in a sequential mode.

5. The SD ADC of claim 3 wherein the controller circuit is configured to control operation of the demultiplexer circuit to select the plurality of digital channels in a non-sequential mode.

6. The SD ADC of claim 1, wherein the ADC circuit is a memoryless ADC circuit.

7. The SD ADC of claim 1 wherein each of the plurality of digital channels comprises:

a quantizer circuit coupled to an output of the digital filter circuit;

a digital filter circuit configured to receive an output signal of the analog circuit and output a filter circuit output signal to a DAC circuit; and

a digital decimation filter circuit configured to generate a digital output signal corresponding to a particular one of the received analog input signals.

8. The SD ADC circuit of claim 7, wherein each digital filter circuit comprises a digital integrator circuit.

9. The SD ADC of claim 7, wherein each of the plurality of digital channels further comprises:

a quantization error compensation circuit coupled to an input of the digital decimation filter and an output of the quantizer circuit, the quantization error compensation circuit configured to combine an output signal of the analog circuit with an input signal of the DAC circuit and output a quantization error compensation signal to the digital decimation filter.

10. A method of multiplexing a plurality of channels using sigma-delta (SD) analog-to-digital converter (ADC) circuitry, the method comprising:

performing analog-to-digital conversion of a first input signal selected from a plurality of received analog input signals using a shared analog circuit;

processing a digital output of the shared analog circuit using a first digital channel selected from the plurality of digital channels;

performing digital-to-analog conversion on the processed digital output to produce a feedback signal for application to an input of the shared analog circuit; and

a digital output signal is generated representing a respective one of the analog input signals.

11. The method of claim 10, further comprising:

receiving and amplifying a difference between the feedback signal and one of the received analog input signals;

controlling a chopper switch circuit to be coupled to an input and an output of the gain amplifier circuit; and

controlling a first multiplexer circuit to select a first one of the plurality of received analog input signals; and

controlling a second multiplexer circuit to select one of the plurality of digital channels to couple to an input of a digital-to-analog converter (DAC) circuit.

12. The method of claim 10, further comprising:

selecting other digital channels of the plurality of digital channels in a sequential mode to receive a digital output of a shared analog circuit.

13. The method of claim 10, further comprising:

selecting other digital channels of the plurality of digital channels in a non-sequential mode to receive a digital output of a shared analog circuit.

14. The method of claim 10, wherein performing analog-to-digital conversion of a first input signal selected from a plurality of received analog input signals using shared analog circuitry comprises:

analog-to-digital conversion is performed on the selected first input signal using a memoryless ADC circuit.

15. The method of claim 10, wherein performing analog-to-digital conversion of a first input signal selected from a plurality of received analog input signals using shared analog circuitry comprises:

a Successive Approximation Register (SAR) ADC operation is performed on the selected first input signal.

16. The method of claim 10, wherein performing analog-to-digital conversion of the selected first input signal using the shared analog circuit comprises:

a flash ADC operation is performed on the selected first input signal.

17. The method of claim 10, wherein performing analog-to-digital conversion of the selected first input signal using the shared analog circuit comprises:

a pipelined ADC operation is performed on the selected first input signal.

18. The method of claim 10, further comprising:

combining a digital output signal of the analog circuit with an input signal of the digital-to-analog converter (DAC) circuit and outputting a quantization error compensation signal to a digital decimation filter.

19. A multiplexed multi-channel sigma-delta (SD) analog-to-digital converter (ADC) circuit comprising:

means for performing analog-to-digital conversion of a first input signal selected from a plurality of received analog input signals using a shared analog circuit;

means for processing a digital output of the shared analog circuit using a first digital channel selected from the plurality of digital channels;

means for performing digital to analogue conversion on the processed digital output to produce a feedback signal for application to the input of the shared analogue circuit; and

means for generating a digital output signal representative of a respective one of said analog input signals.

20. The SD ADC circuit of claim 18, further comprising:

means for receiving and amplifying a difference between the feedback signal and one of the received analog input signals;

means for chopping an input and an output of the gain amplifier circuit; and

means for selecting a first one of the plurality of received analog input signals; and

means for selecting one of the plurality of digital channels to couple to an input of the digital-to-analog converter (DAC) circuit.

Technical Field

This document relates generally, but not exclusively, to integrated circuits and, more particularly, to analog-to-digital converter circuits and systems.

Background

In many electronic applications, an Analog Front End (AFE) may convert an analog electrical signal (e.g., light, sound, temperature, or pressure) representative of a real-world phenomenon for digital processing, for example, for further signal processing. For example, in some precision measurement systems, one or more sensors may be provided for an electronic device to take measurements and generate analog signals. The analog signal may be provided to an analog-to-digital converter (ADC) to generate a digital representation for further processing.

AFEs can be found in many places, such as broadband communication systems, audio systems, receiver systems, and the like. AFEs are used for a wide range of applications including communications, energy, healthcare, instrumentation and measurement, motor and power control, industrial automation, and aerospace/defense.

Disclosure of Invention

A sigma-delta ADC circuit with an analog loop filter circuit may multiplex between different inputs and fill it with new data of the current input by refreshing the memories of the analog loop filter integrator and the digital decimation filter. However, filling the memory can be slow relative to the sampling frequency, as information about the past history must be built before meaningful output data is generated. Thus, the multiplexing rate between channels using sigma-delta ADC circuits may be slowed by such memory refresh. It is not possible to retain past data in the loop filter circuit and skip samples because the loop filters are analog circuits and they cannot store past history due to leakage effects. Similarly, skipping samples in the digital decimation filter circuit may change the filtering action of the decimation filter.

The present disclosure describes a multiplexed sigma-delta ADC circuit that may overcome these problems in order to be able to support cycle-by-cycle sampling of multiple channels. The techniques of this disclosure may provide a fast sigma-delta analog-to-digital converter (ADC) circuit that is small in area and can be dynamically multiplexed over multiple channels.

In certain aspects, the present disclosure relates to a multiplexed multi-channel sigma-delta (SD) analog-to-digital converter (ADC) circuit, comprising: a shared analog circuit configured to receive a selected one of a plurality of analog input signals, the shared analog circuit comprising: an ADC circuit coupled to an input of the analog circuit; a digital-to-analog converter (DAC) circuit configured to provide an analog feedback signal to an input of the analog circuit; and a plurality of digital channels coupled to outputs of the shared analog circuit and the DAC circuit, each of the plurality of digital channels configured to generate a digital output signal representative of a respective one of the analog input signals.

In certain aspects, the present disclosure relates to a method of multiplexing a plurality of channels using sigma-delta (SD) analog-to-digital converter (ADC) circuitry, the method comprising: performing analog-to-digital conversion of a first input signal selected from a plurality of received analog input signals using a shared analog circuit; processing a digital output of the shared analog circuit using a first digital channel selected from the plurality of digital channels; performing digital-to-analog conversion on the processed digital output to produce a feedback signal for application to an input of the shared analog circuit; and generating a digital output signal representative of a respective one of the analog input signals.

In certain aspects, the present disclosure relates to a multiplexed multi-channel sigma-delta (SD) analog-to-digital converter (ADC) circuit, comprising: means for performing analog-to-digital conversion of a first input signal selected from a plurality of received analog input signals using a shared analog circuit; means for processing the digital output of the shared analog circuit using a first digital channel selected from the plurality of digital channels; means for performing digital to analogue conversion on the processed digital output to produce a feedback signal for application to the input of the shared analogue circuit; and means for generating a digital output signal representative of a respective one of said analogue input signals.

This summary is intended to provide an overview of the subject matter of the present patent application. It is not intended to provide an exclusive or exhaustive explanation of the invention. The detailed description is included to provide further information about the present patent application.

Drawings

In the drawings, which are not necessarily drawn to scale, like numerals may describe similar components in different views. Like numerals having different letter suffixes may represent different instances of similar components. The drawings illustrate by way of example, and not by way of limitation, various embodiments discussed in the present document.

Fig. 1 is a block diagram of an example of a multiplexed multi-channel sigma-delta analog-to-digital converter circuit according to the present invention.

Fig. 2 is an example of a timing diagram that may be used with the circuits of fig. 1 or 3.

Fig. 3 is a block diagram of another example of a multiplexed multi-channel sigma-delta analog-to-digital converter circuit according to the present invention.

Fig. 4 is a simplified block diagram of a multiplexed multi-channel sigma-delta analog-to-digital converter circuit according to the present invention.

Detailed Description

In a Successive Approximation Register (SAR) analog-to-digital converter (ADC) circuit, each digital output code is a function of the last input sample and is independent of previous input samples processed by the ADC circuit. In other words, the SAR ADC is memoryless. Therefore, SAR ADCs are suitable for multi-channel solutions. Due to its memoryless nature, SAR ADC may allow multiplexing between different input signals on a sample-by-sample basis. For a SAR ADC, the clock cycle delay between two samples of the same channel is equal to the number of channels.

Unlike SAR ADCs, sigma-delta ADC circuits have memory. In particular, the sigma-delta ADC circuit may include an analog loop filter circuit having a plurality of analog integration circuit stages, wherein information from past inputs may be used in conjunction with the current input to process and provide the digital output code. Additionally, the sigma-delta ADC circuit may include a digital decimation filter circuit that also has a memory of past input signal values.

A sigma-delta ADC circuit with an analog loop filter circuit may be multiplexed between different inputs by refreshing the memories of the analog loop filter integrator and the digital decimation filter and filling them with new data of the current input. However, filling the memory can be slow relative to the sampling frequency, as information about the past history must be built before meaningful output data is generated. Thus, the rate of multiplexing between channels using sigma-delta ADC circuits may be slowed by such memory refresh. It is not possible to retain past data in the loop filter circuit and skip samples because the loop filters are analog circuits and they cannot store past history due to leakage effects. Similarly, skipping samples in the digital decimation filter circuit may change the filtering action of the decimation filter.

The present disclosure describes a multiplexed sigma-delta ADC circuit that may overcome these problems in order to be able to support cycle-by-cycle sampling of multiple channels. The techniques of this disclosure may provide a fast sigma-delta analog-to-digital converter (ADC) circuit that is small in area and can be dynamically multiplexed over multiple channels.

Fig. 1 is a block diagram of an example of a multiplexed multi-channel sigma-delta analog-to-digital converter (ADC) circuit according to the present invention. The system 10 may include a gain circuit 12 having a first input 14 receiving one of a plurality of analog input signals 16A-16N via an analog input multiplexer circuit 18, and a memoryless ADC circuit 20 for receiving an output 22 of the gain circuit 12. Examples of the memoryless ADC circuit 20 may include, but are not limited to, SAR ADC circuits, pipelined ADC circuits, and flash ADC circuits.

The ADC circuit 20 may generate a digital output signal 24, such as an Electrocardiogram (ECG) output signal or other signal of interest, corresponding to one of the analog input signals 16A-16N. In the example configuration shown, gain circuit 12 may include an adder circuit 26 and a gain amplifier circuit 28, such as a Capacitive Gain Amplifier (CGA). In some example implementations, the circuit 10 may also include chopper switch circuits 30, 32 to chop the signal amplified by the gain amplifier circuit 28.

According to the present invention, the sigma-delta ADC circuit 10 may include a plurality of digital channels 34A-34N, e.g., connected in parallel. Each digital channel 34A-34N may include a digital loop filter circuit 36A (also referred to as a "digital filter circuit" in this disclosure), a quantizer circuit 38A, and a decimation filter circuit 40A, e.g., a combination of a digital low pass filter circuit and a down-sampling circuit. A digital output signal 24 corresponding to a particular one of the analog input signals 16A-16N may be coupled to one of the digital channels 34A-34N by a digital demultiplexer circuit 42. Further, to process the received analog input signals 16A-16N, the control circuit 44 may control the operation of the input multiplexer circuit 18 to select a particular one of the analog input signals 16A-16N, e.g., signal 16A, and control the operation of the digital demultiplexer circuit 42 to select a particular one of the digital channels 34A-34N, e.g., digital channel 34A.

Using the techniques of this disclosure, analog circuitry 46, which may include various analog blocks such as gain circuitry 12, ADC circuitry 20, and DAC circuitry 52, may be shared by digital channels 34A-34N. Likewise, each digital channel may include its own digital filter circuit, quantizer circuit, and decimation filter circuit. Thus, for an N-channel input, the circuit of fig. 1 has a set of analog blocks (e.g., gain circuit 12, ADC circuit 20, and DAC circuit 52) that can be shared by an 'N' set of digital channels.

As shown in fig. 1, a digital filter circuit 36A, e.g., digital channel 34A, may receive the digital output signal 24 of the ADC circuit 20 and provide a filtered digital output 48A to a quantizer circuit 38A. In some example implementations, the digital filter circuit may include one or both of a plurality of integrator circuits and a low pass filter circuit. For example, the digital filter circuit may have a high gain in the frequency band of interest. In some examples, the quantizer circuit may be a coarse 1-bit quantizer, such as a comparator circuit, or in other examples, the quantizer circuit may have more than two levels.

Quantizer circuit 38A may output a quantized digital signal 50A and provide signal 50A to (1) a digital-to-analog converter (DAC) circuit 52 in a feedback loop 54, and (2) a digital decimation filter circuit 40A to produce a digital output signal 56A corresponding to a particular one of the received analog input signals 16A-16N. It should be appreciated that each of the remaining digital channels 34B-34N produces a corresponding digital output signal 56B-56N, which is more clearly shown in FIG. 4.

Each of the plurality of digital channels 34A-34N may be coupled to a respective input of a digital multiplexer circuit 57. Control circuitry 44 may control the operation of multiplexer circuitry 57 to couple a digital signal of a particular digital channel, e.g., output signal 50A of quantizer circuitry 38A, to an input of DAC circuitry 52 via multiplexer 57.

DAC circuit 52 may generate an analog feedback signal 58 and provide feedback signal 58 to a second input 60 of gain circuit 12 such that adder circuit 26 subtracts the digital signal corresponding to a particular digital channel, e.g., output 50A of channel 34A, from the corresponding input signal 16A. In some example configurations, DAC circuit 52 may be a capacitive DAC circuit, which may help facilitate integration in configurations that include capacitive gain amplifier 28. Adder circuit 26 may subtract analog feedback signal 58 from the original analog input signal (input signal 16A) to generate a difference signal. It should be noted that adder circuit 26 is depicted separately for conceptual purposes, but may form part of gain circuit 12 itself in some configurations. For example, adder circuit 26 may be implemented as a high impedance "summing junction" node at which charge is injected from multiple inputs, or as inverting and non-inverting inputs of a buffer amplifier, or the like.

The action of feedback loop 54 may cause an input signal (e.g., input signal 16A) to be reproduced at the output at a frequency where the gain is high. The quantization noise may be shaped by the gain of the feedback loop 54. A decimation filter circuit (e.g., decimation filter circuit 40A) may filter the shaped quantization noise to achieve a high signal-to-noise ratio (SNR) in the frequency band of interest.

For purposes of non-limiting illustrative explanation, control circuitry 44 may control the operation of input multiplexer circuitry 18 to select first analog input signal 16A to be processed by circuitry 10. The difference between input signal 16A and feedback signal 58 may be received and amplified by gain circuit 12. In some example configurations, control circuit 44 may control chopper switch circuits 30, 32 to chop gain circuit 12 in order to shift its 1/f noise out of the frequency band of interest. The amplified difference signal may be digitized by the ADC circuit 20.

Control circuitry 44 may control analog multiplexer 18 to multiplex input signals 16A-16N to analog circuitry 46. At the same time, control circuitry 44 may control digital demultiplexer circuitry 42 to couple a respective data channel of one of digital channels 34A-34N to process a respective output digital signal from shared analog circuitry 46. For example, control circuit 44 may select input signal 16A multiplexed by analog multiplexer 18 into analog circuit 46 and corresponding digital channel 34A, and its associated digital filter circuit 36A and quantizer circuit 38A may process output digital signal 24. The control circuitry 44 may also control the multiplexer circuitry 57 to select the digital channel 34A corresponding to the input signal 16A, and the respective output 50A of its digital sigma-delta feedback loop may drive the DAC circuitry 52 to the adder circuitry 26, whose other input 14 is the input signal 16A, forming the analog multiplexer 18. Decimation filter circuit 40A of digital channel 34A may receive the output of quantizer circuit 38A and may generate a digital output signal 56A corresponding to received analog input signal 16A.

In a non-limiting illustrative configuration, a fixed Capacitive Gain Amplifier (CGA) circuit 28 (e.g., having a gain of 16) may be used to amplify the difference between a selected one of the analog input signals 16A-16N and the feedback signal 58 generated by the DAC circuit 52. The differential signal may be processed by 14-bit SAR ADC circuit 20. The output digital signal of SAR ADC circuit 20 may be processed by a selected one of digital channels 34A-34N (e.g., digital channel 34A) having a digital sigma-delta feedback loop including one or more digital integrator circuits and a quantizer circuit (e.g., quantizer circuit 38A). The output of the digital sigma-delta feedback loop may drive a DAC circuit 52, such as a 7-bit DAC circuit. In some example implementations, DAC circuit 52 may include a noise shaping DAC circuit.

One way to implement the numeration is for each channel to have its own block of numerics. Alternatively, it may be more area efficient to include a shared digital compute engine with separate memory for each channel.

It should be noted that the analog block may operate at a 'N' times higher sampling frequency. However, a large amount of area can be saved due to the use of a set of analog modules. Furthermore, the architecture described in this disclosure may scale particularly well when doing finer geometry processing, as the 'N' digital blocks (e.g., digital filter circuits, quantizer circuits, and decimation filter circuits) may scale significantly.

Fig. 2 is an example of a timing diagram 70 that may be used with the circuits of fig. 1 or 3. For simplicity, four (4) channel selection signals 72-78 are shown in FIG. 2. In other implementations, there may be more than four channels or less than four channels. In addition to the channel selection signals 72-78, the timing diagram 70 depicts a chopping signal 80, an amplifier mode signal 82, and an ADC acquisition signal 84, as well as an ADC output signal 86.

A control circuit, such as control circuit 44 of fig. 1, may output channel selection signals 72-78. For example, the control circuit may generate and apply a logic high signal of the CH1 select signal 72 to the multiplexer circuit 18 of fig. 1 (or fig. 3) to select the input signal 16A. The control circuit's CH1 selection signal 72 may also select a corresponding one of the digital channels, such as digital channel 34A of fig. 1 (or fig. 3), to process the digital output signal and may select a corresponding one of the DAC circuit 52 inputs (e.g., input 50A) for the feedback loop. The control circuit may then select the next set of signals corresponding to channel 2, channel 3, etc.

In some example configurations, the control circuitry may control the operation of the input multiplexer circuitry and demultiplexer circuitry to select a plurality of digital channels, e.g., channel 1, followed by channel 2, followed by channel 3, etc., in a sequential mode. In other example configurations, the control circuitry may control operation of the input multiplexer circuitry and the demultiplexer circuitry to select the plurality of digital channels in a non-sequential mode. In one non-limiting illustrative configuration, the control circuitry may control the selection of the following channels: channel 1, channel 2. Other non-sequential modes are also possible and are considered within the scope of this disclosure, such as channel 1, channel 3, channel 2, channel 4, etc.

In configurations that include chopping, control circuit 44 may output a first chopping signal, e.g., a logic high signal, to control chopping switches, e.g., chopping switches 30, 32 in fig. 1 (or fig. 3), in a first chopping cycle. Chopping may be done 'N' times slower than the ADC acquisition signal 84, sharing a chopping period for all 'N' channels. During the second chopping cycle, the control circuit 44 may output a second chopping signal, such as a logic low signal, to control the chopping switches.

In addition, a gain amplifier circuit, such as amplifier circuit 28 of FIG. 1 (or FIG. 3), such as a capacitive gain amplifier, may be auto-zeroed. During each chopping cycle, each channel may first be auto-zeroed (e.g., "AZ 1," "AZ 2," etc. of the amplifier mode signal 82) to set the input common mode of the input capacitors of the amplifier circuit at the channel inputs and reset the DAC circuit. After the auto-zero phase, e.g. after AZ1, the DAC circuit may be set to an appropriate feedback signal determined by the digital engine based on past cycles. The amplifier circuit may amplify the difference between the input signal for that channel and the DAC feedback signal (e.g., "CH 1," "CH 2," etc. of the amplifier mode signal 82) to convey the analog signal at the ADC input 22.

In some examples, an ADC circuit (e.g., ADC circuit 20 of fig. 1 or (fig. 3)) may obtain a large difference signal from an amplifier circuit on a falling edge of ADC acquisition signal 84. The ADC circuit may process the signal, e.g., perform a bit trial, when the ADC acquire signal 84 is a logic low. The digital output signal of the ADC circuit may be processed to deliver a digital output to a digital channel, as shown by ADCOUT signal 86.

The digital signal may be processed by a digital filter circuit for a particular digital channel, such as digital channel 34A of fig. 1 (or fig. 3), and an appropriate output signal for that channel may be generated. Since the filter circuit 36A is digital, once the input is multiplexed to the next channel and the amplifier auto-zeroes the input, the amplifier circuit and ADC circuit can process the signal of the next channel.

It should be noted that the ADCOUT signal 24 need not occur with auto-zeroing of the amplifier circuit. For example, auto-zero AZ2 of the mode signal 82 may occur once the ADC circuit acquires the channel 1 input signal. The control circuit may then control the input multiplexer circuit to connect to channel 2, the DAC circuit may reset, and the analog circuit may begin processing channel 2 data.

Fig. 3 is a block diagram of another example of a multiplexed multi-channel sigma-delta ADC circuit 100 according to the present invention. Some of the elements shown in the circuit 100 of fig. 3 are similar to the elements shown and described above with respect to the circuit 10 of fig. 1. For the sake of brevity, the new features will be described in detail.

The circuit 100 of fig. 3 may include a quantization error compensation circuit 102 for combining the output signal of the analog circuit 24 (e.g., which is also the digital input to the digital filter circuit 36A) with the digital input signal of the DAC circuit and outputting a quantization error compensation signal (e.g., signal 50A) to the digital decimation filter. In the example shown in FIG. 3, the two inputs may be combined using a ratio of 1/GE, where GE is the fixed gain of gain amplifier circuit 28.

The actual amplifier gain error (GA) may return the loop quantization noise, but its contribution can be significantly suppressed using the technique of FIG. 3. The amplifier gain error does not affect the Signal Transfer Function (STF) in the frequency band of interest because the loop gain can be high in the frequency band of interest. The DAC circuit gain error may occur directly on the STF.

Additional information regarding the technique of FIG. 3 may be found in U.S. patent application No.15/621,621 entitled "Quantization noise cancellation in a Feedback Loop" to Kalb et al, and filed on 2017, 13.6, which is incorporated herein by reference in its entirety, including its description of Quantization noise cancellation techniques.

Fig. 4 is a simplified block diagram of a multiplexed multi-channel sigma-delta ADC circuit 200 according to the present invention. The circuit 200 of fig. 4 may implement the techniques of fig. 1 and 3 and more clearly depict the parallel connection of the digital channels 34A-34N and how each digital channel 34A-34N outputs a respective digital output signal 56A-56N corresponding to a particular one of the received analog input signals 16A-16N.

The architecture described in this disclosure may allow for processing of input signals of different bandwidth, input range, and SNR requirements in a multiplexing operation. Non-limiting illustrative configurations are described below. The sigma-delta ADC circuit architecture described in this disclosure may be configured to support eight multiplexed channels. The gain amplifier may be a CGA with a fixed gain of 16. The ADC circuit may be a 14-bit resolution sar ADC sampled at 2 MHz. The DAC circuit may be a 7-bit DAC, and in some examples, noise-shaped.

In some example implementations, the sigma-delta ADC circuit may process input signals up to 5V and provide an 18-bit SNR at 625 samples per second (sps), with an oversampling ratio (OSR) of 200). Some digital channels may operate without a digital feedback loop in which the DAC circuitry is disconnected or disabled. With a CGA gain of 1, these channels can process up to 5V of input signal and provide output at a resolution of 305uV of 250 ksps. With a CGA gain of 16, some channels can process up to 300mV of input signal and provide 18.3uV output at a resolution of 250 ksps. The converter architecture described in this invention can support these varying input signals and process them cycle by cycle with the same shared analog signal chain.

Various notes

Each of the non-limiting aspects or examples described herein can exist independently or can be combined in various permutations or with one or more other examples.

The foregoing detailed description includes references to the accompanying drawings, which form a part of the detailed description. The drawings show, by way of illustration, specific embodiments in which the invention may be practiced. These embodiments are also referred to herein as "examples". These examples may include elements in addition to those shown or described. However, the inventors also contemplate examples in which only those elements shown or described are provided. Moreover, the inventors also contemplate examples using any combination or permutation of those elements shown or described (or one or more aspects thereof), with respect to a particular example (or one or more aspects thereof), or with respect to other examples (or one or more aspects thereof) shown or described herein.

If there is no inconsistency in the usage of this document with any of the documents incorporated by reference, then the usage in this document shall prevail.

In this document, the terms "a" or "an" are used generically in the patent document, and include any other instance or use of one or more than one, independent of "at least one" or "one or more. In this document, the term "or" is used to indicate nonexclusivity, e.g., "a or B" includes "a but not B," "B but not a" and "a and B," unless otherwise indicated. The terms "including" and "wherein" are used herein as the equivalent of the respective terms "comprising" and "wherein". Furthermore, in the following claims, the terms "comprises" and "comprising" are open-ended, i.e., a system, apparatus, article, composition, formulation, or process that comprises elements other than those listed after such term in a claim is considered to be within the scope of that claim. Furthermore, in the following claims, the terms "first," "second," and "third," etc. are used merely as labels, and are not intended to impose numerical requirements on their objects.

The method examples described herein may be machine or computer-implemented at least in part. Some examples may include a computer-readable or machine-readable medium encoded with instructions operable to configure an electronic device to perform a method as described in the above examples. Implementations of such methods may include code, such as microcode, assembly language code, higher level language code, and the like. Such code may include computer readable instructions for performing various methods. The code may form part of a computer program product. Further, in an example, the code can be tangibly stored on one or more volatile, non-transitory, or non-volatile tangible computer-readable media, e.g., during execution or at other times. Examples of such tangible computer-readable media may include, but are not limited to, hard disks, removable magnetic disks, removable optical disks (e.g., compact disks and digital video disks), magnetic tape, memory cards or sticks, Random Access Memories (RAMs), Read Only Memories (ROMs), and the like.

The above description is intended to be illustrative and not restrictive. For example, the above-described examples (or one or more aspects thereof) may be used in combination with each other. Other embodiments may be utilized, for example, by one of ordinary skill in the art, upon reading the above description. The abstract is provided to comply with 37c.f.r. § 1.72(b), allowing the reader to quickly ascertain the nature of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. Also, in the foregoing detailed description, various features may be combined together to simplify the present disclosure. This should not be interpreted as intending that an unclaimed disclosed feature is essential to any claim. Rather, inventive subject matter may lie in less than all features of a particular disclosed embodiment. Thus, the following claims are hereby incorporated into the detailed description as examples or embodiments, with each claim standing on its own as a separate embodiment, and it is contemplated that these embodiments may be combined with each other in various combinations or permutations. The scope of the invention should be determined with reference to the appended claims, along with the full scope of equivalents to which such claims are entitled.