Semiconductor structure manufacturing method
阅读说明:本技术 一种半导体结构制造方法 (Semiconductor structure manufacturing method ) 是由 张玉贵 方建智 彭康钧 李建财 于 2018-08-27 设计创作,主要内容包括:本发明提供一种半导体结构制造方法,涉及半导体技术领域。该方法提供一种半导体堆叠结构,所述半导体堆叠结构包括基底以及依次堆叠在所述基底上的过渡层、金属层和捕获层,在所述半导体堆叠结构在进行热处理并形成半导体结构时,过渡层能够在形成半导体结构的过程中提供硅补偿,避免出现金属层与基底反应速度过快以及形成的半导体结构空洞、表面不平整以及粗糙度较大等问题,降低了半导体结构的表面电阻,提高了制程工艺的稳定性以及良品率。(The invention provides a semiconductor structure manufacturing method, and relates to the technical field of semiconductors. The method provides a semiconductor stacking structure which comprises a substrate, and a transition layer, a metal layer and a capturing layer which are sequentially stacked on the substrate, wherein when the semiconductor stacking structure is subjected to heat treatment and forms a semiconductor structure, the transition layer can provide silicon compensation in the process of forming the semiconductor structure, so that the problems of overhigh reaction speed of the metal layer and the substrate, formed cavities, uneven surfaces, larger roughness and the like of the semiconductor structure are avoided, the surface resistance of the semiconductor structure is reduced, and the stability and the yield of a manufacturing process are improved.)
1. A method of fabricating a semiconductor structure, comprising:
providing a substrate, and forming a transition layer on the substrate;
forming a metal layer on the transition layer;
forming a trapping layer on the metal layer to form a semiconductor stacked structure;
performing a first anneal on the semiconductor stacked structure;
after the first annealing step is carried out, providing a first cleaning solution to clean the semiconductor stacking structure; and
after the cleaning step, performing second annealing on the semiconductor stacking structure to form a semiconductor structure.
2. The method of manufacturing a semiconductor structure of claim 1, wherein: the substrate is silicon.
3. The method of manufacturing a semiconductor structure of claim 2, wherein: and before the transition layer is formed, providing a second cleaning liquid to clean the native oxide layer on the surface of the substrate.
4. The method of manufacturing a semiconductor structure of claim 1, wherein: and stacking silicon dioxide on the substrate and forming the transition layer.
5. The method of manufacturing a semiconductor structure of claim 1, wherein: the thickness of the transition layer is
6. The method of manufacturing a semiconductor structure of claim 1, wherein: the metal layer is cobalt.
7. The method of manufacturing a semiconductor structure of claim 1, wherein: the thickness of the metal layer is
8. The method of manufacturing a semiconductor structure of claim 1, wherein: the metal layer is titanium and/or titanium nitride.
9. The method of manufacturing a semiconductor structure of claim 1, wherein: the thickness of the trapping layer isTo
10. The method of manufacturing a semiconductor structure of claim 1, wherein: the temperature of the first annealing is 380 to 510 degrees.
11. The method of manufacturing a semiconductor structure of claim 1, wherein: the temperature of the second annealing is 680 to 890 degrees.
12. The method of claim 6, wherein: during the first anneal, the metal layer reacts with the transition layer and forms cobaltous silicide.
13. The method of fabricating a semiconductor structure of claim 12, wherein: the cobalt silicide further forms cobalt silicide when the second anneal is performed.
Technical Field
The invention relates to the technical field of semiconductors, in particular to a manufacturing method of a semiconductor structure.
Background
In the manufacture of semiconductor devices, Contact windows or holes are required to connect local lines, and metal silicides with low Contact resistance are usually selected.
Disclosure of Invention
In view of the above-mentioned shortcomings of the prior art, the present invention provides a method for manufacturing a semiconductor structure, which is used to solve the problem of low quality of the metal silicide process in the prior art.
To achieve the above and other related objects, the present invention provides a method for fabricating a semiconductor structure, comprising:
providing a substrate, and forming a transition layer on the substrate;
forming a metal layer on the transition layer;
forming a trapping layer on the metal layer to form a semiconductor stacked structure;
performing a first anneal on the semiconductor stacked structure;
cleaning the semiconductor stacked structure after the first annealing step is performed; and
after the cleaning step, performing second annealing on the semiconductor stacking structure to form a semiconductor structure.
Optionally, the substrate is silicon.
Optionally, before forming the transition layer, a second cleaning solution is provided to clean the native oxide layer on the substrate surface.
Optionally, silicon dioxide is stacked on the substrate and the transition layer is formed.
Optionally, the thickness of the transition layer isTo
Optionally, the metal layer is cobalt.
Optionally, the thickness of the metal layer isTo
Optionally, the metal layer is titanium and/or titanium nitride.
Optionally, the thickness of the trapping layer is
ToOptionally, the temperature of the first annealing is 380 to 510 degrees.
Optionally, the temperature of the second anneal is between 680 and 890 degrees.
Optionally, when the first annealing is performed, the metal layer reacts with the transition layer and forms cobaltous silicide.
Optionally, the cobalt silicide further forms cobalt silicide when the second annealing is performed.
Drawings
Fig. 1 is a schematic flow chart illustrating a method for fabricating a semiconductor structure according to an embodiment of the invention.
FIG. 2 is a schematic view of a substrate structure.
Fig. 3 is a schematic diagram of a transition layer structure.
Fig. 4 is a schematic view of a metal layer structure.
Fig. 5 is a schematic view of a semiconductor stack structure.
FIG. 6 is a schematic view of a semiconductor stack after a first anneal.
FIG. 7 is a schematic view of a semiconductor stack after being cleaned by a first cleaning solution.
FIG. 8 is a schematic view of a semiconductor structure formed after a second anneal.
FIG. 9 is a schematic view of a metal silicide void structure.
FIG. 10 is a schematic view showing the movement of ions during the first annealing process according to the embodiment of the present invention.
FIG. 11 is a schematic diagram illustrating exemplary motion during a first anneal in accordance with an embodiment of the present invention.
FIG. 12 is a schematic electron microscope view of a semiconductor structure.
Description of reference numerals
1 substrate
2 transition layer
3 Metal layer
4 trapping layer
5 cobalt silicide layer
6 impurity layer
7 cobalt silicide layer
8 hollow
Detailed Description
In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present invention. It will be apparent, however, to one skilled in the art, that the present invention may be practiced without one or more of these specific details. In other instances, well-known features have not been described in order to avoid obscuring the invention.
It is to be understood that the present invention may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the size and relative sizes of layers and regions may be exaggerated for clarity. Like reference numerals refer to like elements throughout.
It will be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it can be directly on, adjacent to, connected or coupled to the other elements or layers or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to" or "directly coupled to" other elements or layers, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention.
Spatial relational terms such as "under," "below," "under," "above," "over," and the like may be used herein for convenience in describing the relationship of one element or feature to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, then elements or features described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary terms "under" and "under" can encompass both an orientation of above and below. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial descriptors used herein interpreted accordingly.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.
Embodiments of the invention are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the invention. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, embodiments of the invention should not be limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an implanted region shown as a rectangle will typically have rounded or curved features and/or implant concentration gradients at its edges rather than a binary change from implanted to non-implanted region. Also, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation is performed. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the present invention.
In order to provide a thorough understanding of the present invention, detailed steps and detailed structures will be set forth in the following description in order to explain the present invention. The following detailed description of the preferred embodiments of the invention, however, the invention is capable of other embodiments in addition to those detailed.
In an embodiment of the present invention, referring to fig. 1 to 8, a method for fabricating a semiconductor structure includes:
s1: providing a
s2: forming a
s3: forming a
s4: forming a
S5-S7: and carrying out heat treatment on the semiconductor stacked structure to form the semiconductor structure.
As an example, the semiconductor structure is to form a metal silicide, which may include titanium silicide (TiSi)2) Cobalt silicide (CoSi)2) Nickel silicide (NiSi), tantalum silicide (TaSi)2) Tungsten silicide (WSi)2) Of a metal silicide, said
The
Referring to fig. 9, in the process of forming the metal silicide by the heat treatment of the thin film stack structure, a large amount of material in the
In the process of forming the
In order to prevent the
In particular, cobalt reacts easily with oxygen and forms cobaltous oxide (CoO), which is difficult to clean during the cleaning process, thereby forming defects (defects) during the metal silicide process, andif cobaltous oxide is formed on the surface of the metal silicide, nucleation sites or barrier layers will be formed, which will greatly affect the cobalt silicide (CoSi)2) Formation, e.g. of CoSi2The crystal planes of the/Si interface being preferably disoriented, e.g. CoSi2(111),CoSi2(100),CoSi2(222) When polycrystalline surfaces are mixedly grown, the interface is not smooth enough, the leakage current is increased abnormally, and the device performance is poor. For this purpose, a
Illustratively, the semiconductor stacked structure formed in this embodiment includes a
In another embodiment, the present embodiment provides a solution for forming the
Further, a
Referring to fig. 5 to 8, the present embodiment provides a method for manufacturing a semiconductor structure, including:
providing a semiconductor stacked structure, wherein the semiconductor stacked structure comprises a substrate, and a transition layer, a metal layer and a capture layer which are sequentially stacked on the substrate;
performing a first anneal on the semiconductor stacked structure;
providing a first cleaning solution, and cleaning the semiconductor stacking structure after the first annealing step;
and carrying out second annealing on the cleaned semiconductor stacking structure to form a semiconductor structure.
In still another embodiment, referring to fig. 5 to 8, a semiconductor stacked structure is provided as an example, the semiconductor stacked structure is a thin film stacked structure subjected to a thermal process, and the semiconductor stacked structure includes a
Referring to fig. 5, 6 and 10, a first annealing process is performed on the semiconductor stacked structure, wherein the first annealing process is, for example, a Rapid Thermal annealing (RTP/Rapid Thermal Processing) process, the first annealing process is performed at a temperature of 380 to 510 degrees, for example, 490 to 495 degrees, and the Processing time is 20 to 40 seconds, for example, 25 to 35 seconds. In the first annealing process, the
referring to fig. 6 and 7, a first cleaning solution is provided to clean the impurity layer 6 (mainly titanium oxide) and the incompletely reacted trapping layer, metal layer and transition layer, which are attached to the surface of the semiconductor stacked structure, wherein the cleaning solution comprises SC-1 (a mixed solution of ammonium hydroxide, hydrogen peroxide and deionized water) and/or SC-2 (a mixed solution of hydrochloric acid, hydrogen peroxide and deionized water), such as a mixed acid solution of SC-1 and SC-2, and a clean cobalt silicide layer 5 is formed after the cleaning.
Referring to fig. 7 and 8, a second annealing process is performed on the semiconductor stack structure, wherein the second annealing process is performed by, for example, a Rapid Thermal annealing (RTP/Rapid Thermal Processing) process, the second annealing process is performed at a temperature of 680 to 890 degrees for a time period of 20 to 40 seconds, for example, 25 to 35 seconds. In the second annealing process, the cobalt silicide layer 5 is formed as a cobalt silicide layer 7, the thickness of the cobalt silicide layer 7 being
ToFor exampleReferring to fig. 12, fig. 12 is an electron microscope image of the semiconductor structure under a 50 nm window, from which: cobalt silicide (CoSi)2) No void generation, smooth surface and low roughness.The first annealing and the second annealing may be performed in an inert gas atmosphere, such as an inert gas or nitrogen. For example, the ambient conditions of the first annealing and the second annealing in the present embodiment may be selected to be a nitrogen ambient.
In still another embodiment, referring to fig. 5 to 8, a semiconductor stacked structure is provided as an example, the semiconductor stacked structure is a thin film stacked structure subjected to a thermal process, and the semiconductor stacked structure includes a
Referring to fig. 5, 6 and 11, a first annealing process is performed on the semiconductor stacked structure, wherein the first annealing process is, for example, a Rapid Thermal annealing (RTP/Rapid Thermal Processing) process, the first annealing process is performed at a temperature of 380 to 510 degrees, for example, 490 to 495 degrees, and a Processing time is, for example, 20 to 40 seconds, and, for example, 25 to 35 seconds. In the first annealing process, silicon ions provided by the
referring to fig. 6 and 7, a first cleaning solution is provided to clean the semiconductor structure, and clean the impurity layer 6 (mainly titanium oxide) and the incompletely reacted trapping layer, metal layer and transition layer attached to the surface of the semiconductor structure, wherein the cleaning solution comprises SC-1 (a mixed solution of ammonium hydroxide, hydrogen peroxide and deionized water) and/or SC-2 (a mixed solution of hydrochloric acid, hydrogen peroxide and deionized water), such as a mixed acid solution of SC-1 and SC-2, and a clean cobalt oxide layer 5 is formed after the cleaning.
Referring to fig. 7 and 8, a second annealing process is performed on the semiconductor stack structure, wherein the second annealing process is performed by, for example, a Rapid Thermal annealing (RTP/Rapid Thermal Processing) process, the second annealing process is performed at a temperature of 680 to 890 degrees for a time period of 20 to 40 seconds, for example, 25 to 35 seconds. In the second annealing process, the cobalt silicide layer 5 is formed as a cobalt silicide layer 7, the thickness of the cobalt silicide layer 7 being
ToFor exampleThe foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.
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