Three-level and two-stage decoupling active NPC converter
阅读说明:本技术 三电平两级解耦有源npc转换器 (Three-level and two-stage decoupling active NPC converter ) 是由 张迪 何江彪 萨钦·玛杜苏德哈南 于 2018-06-05 设计创作,主要内容包括:一种系统包括电压转换器和用于控制电压转换器的操作的控制器。电压转换器包括多个分支,其中每个分支包括第一组和第二组硅(Si)基功率器件。第一组硅基功率器件包括在第一互连节点处彼此连接的第一和第二硅基功率器件,并且第二组硅基功率器件包括在第二互连节点处彼此连接的第三和第四硅基功率器件。第一组和第二组硅基功率器件分别跨第一和第二DC电压源联接。第一组碳化硅(SiC)基功率器件跨第一互连节点和第二互连节点联接。该系统还包括跨第一和第二互连节点连接的缓冲电容器。(A system includes a voltage converter and a controller for controlling operation of the voltage converter. The voltage converter includes a plurality of branches, where each branch includes a first set and a second set of silicon (Si) -based power devices. The first group of silicon-based power devices includes first and second silicon-based power devices connected to each other at a first interconnect node, and the second group of silicon-based power devices includes third and fourth silicon-based power devices connected to each other at a second interconnect node. The first and second groups of silicon-based power devices are coupled across first and second DC voltage sources, respectively. A first set of silicon carbide (SiC) -based power devices is coupled across the first and second interconnect nodes. The system also includes a buffer capacitor connected across the first and second interconnect nodes.)
1. A system, comprising:
a voltage converter having a plurality of branches, each branch comprising:
a first set of silicon (Si) -based power devices coupled across a first Direct Current (DC) voltage source, wherein the first set of silicon-based power devices includes a first silicon-based power device and a second silicon-based power device connected to each other at a first interconnect node;
a second group of silicon-based power devices coupled across a second DC voltage source, wherein the second group of silicon-based power devices includes a third silicon-based power device and a fourth silicon-based power device connected to each other at a second interconnect node;
a first set of silicon carbide (SiC) -based power devices coupled across the first and second interconnect nodes, wherein the first set of silicon carbide-based power devices includes first and second silicon carbide-based power devices connected to each other at a third interconnect node;
a buffer capacitor connected across the first and second interconnect nodes;
wherein the first and second groups of silicon-based power devices are connected to each other at a fourth interconnect node; and
a controller to control operation of the voltage converter.
2. The system of claim 1, wherein the controller controls the gate pulse based on an output current polarity and an output voltage polarity.
3. The system of claim 1, wherein the controller operates the voltage converter in a plurality of operating states including a positive state, a P-type zero state, a negative state, or an N-type zero state at any given time.
4. The system of claim 3, wherein the controller is configured to, during each of the operating states, turn on one silicon-based power device from the first set of silicon-based power devices and turn on another silicon-based power device from the second set of silicon-based power devices.
5. The system of claim 4, wherein the controller is configured to turn on one of the silicon carbide-based power devices such that the one silicon carbide-based power device and the one silicon-based power device that was turned on during the corresponding operating state together carry the load current in series.
6. The system of claim 5, wherein the silicon-based power device and the silicon carbide-based power device carrying the load current in series comprise: i) the first silicon-based power device and the first silicon carbide-based power device during the positive state, ii) the third silicon-based power device and the second silicon carbide-based power device during the P-type zero state, iii) the fourth silicon-based power device and the second silicon carbide-based power device during the negative state, and iv) the second silicon-based power device and the first silicon carbide-based power device during the N-type zero state.
7. The system of claim 6, wherein when the load current is to be commutated from one silicon carbide-based power device to another, the controller is configured to cause the silicon-based power device and the silicon carbide-based power device carrying the load current in series to be turned off simultaneously.
8. The system of claim 7, wherein the controller is configured to turn on the silicon-based power device that has been simultaneously turned off with the silicon carbide-based power device after damping a resonance formed between the snubber capacitor of the voltage converter and the silicon-based power device.
9. The system of claim 7, wherein the controller is configured to cause the silicon-based power device and the silicon carbide-based power device carrying the load current in series to be simultaneously turned off if an output voltage polarity and an output current polarity of the voltage converter are opposite to each other or if the output voltage is zero and the output current polarity is positive.
10. The system of claim 5, wherein the controller is configured to cause the silicon-based power devices and the silicon carbide-based power devices that are turned on to be simultaneously turned off if the output voltage polarity and the output current polarity of the voltage converter are opposite.
11. The system of claim 3, wherein in the positive state, a voltage at the third interconnect node is positive relative to the fourth interconnect node, and in the negative state, the voltage at the third interconnect node is negative.
12. The system of claim 11, wherein in the P-type zero state and the N-type zero state, a voltage at the third interconnect node is zero relative to the fourth interconnect node.
13. The system of claim 12, wherein the controller is configured to turn on the third silicon-based power device in the P-type zero state and to turn on the second silicon-based power device in the N-type zero state.
14. A system, comprising:
a voltage converter having a plurality of branches, each branch comprising:
a first set of silicon (Si) based power devices coupled to a first DC voltage source;
a second set of silicon-based power devices coupled to a second DC voltage source, wherein the first set of silicon-based power devices and the second set of silicon-based power devices are coupled in series;
a first set of silicon carbide (SiC) -based power devices coupled to the first set of silicon-based power devices and the second set of silicon-based power devices;
a snubber capacitor connected across the first set of silicon carbide-based power devices; and
a processor configured to control the switching of each silicon carbide-based power device of the first set of silicon carbide-based power devices and each silicon-based power device of the first set of silicon-based power devices and the second set of silicon-based power devices such that, at any given time, one silicon carbide-based power device of the first set of silicon carbide-based power electronic devices conducts current in series with one silicon-based power electronic device of the first set of silicon-based power electronic devices or the second set of silicon-based power electronic devices.
15. The system of claim 14, wherein when the current is to be commutated from one silicon carbide-based power device to another silicon carbide-based power device, the controller is configured to simultaneously turn off the one silicon carbide-based power device of the first set of silicon carbide-based power electronics and the one silicon-based power electronics of the first or second set that conduct the current in series.
16. The system of claim 15, wherein the controller is configured to turn on one silicon-based power electronic device that has been turned off simultaneously with the one silicon carbide-based power electronic device after damping a resonance formed between the snubber capacitor of the voltage converter and the silicon-based power electronic device.
17. The system of claim 15, wherein the controller causes the one silicon carbide-based power electronic device and the one silicon-based power electronic device that conduct the current in series to be simultaneously turned off if an output voltage polarity and an output current polarity of the voltage converter are opposite to each other or if the output voltage is zero and the output current polarity is positive.
18. The system of claim 15, wherein the controller is configured to cause the silicon-based power electronics and the silicon carbide-based power electronics that are turned on to be simultaneously turned off if the output voltage polarity and the output current polarity of the voltage converter are opposite.
19. The system of claim 14, wherein each of the first and second groups of silicon-based power devices comprises one or more Insulated Gate Bipolar Transistors (IGBTs).
20. The voltage converter of claim 14, wherein the first set of silicon carbide-based power devices comprises one or more Metal Oxide Semiconductor Field Effect Transistors (MOSFETs).
Technical Field
Embodiments of the present technology relate to power converters, and more particularly, to a method of operating a three-level two-stage decoupled active Neutral Point Clamped (NPC) converter.
Background
Turbine electric or hybrid propulsion may improve the energy conversion efficiency of the aircraft, reduce carbon emissions, and reduce reliance on carbon-based fuels. Megawatt (MW) class lightweight, high efficiency, high reliability power converters are important components of hybrid propulsion. Furthermore, to reduce cable weight, the power converter needs to withstand moderate Direct Current (DC) voltage stress. Further, in order to reduce the weight of the motor used in hybrid propulsion, the fundamental output frequency of the power converter needs to be high, for example, higher than 1kHz, and thus the power converter is required to have a higher switching frequency.
Silicon carbide (SiC) is a semiconductor that is increasingly used in power electronic devices such as Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) to meet the high switching frequency and efficiency requirements of power converters. Furthermore, a three-level NPC converter topology is the preferred choice for power converters because it can achieve higher voltage ratings without having to sequence the devices; better harmonic performance to reduce the weight of the filter; and lower switching losses to achieve high efficiency.
In order to design such a three-level converter, the most important challenge is how to minimize the commutation loop inductance. In addition to the commutation loop inductance, SiC MOSFET-based multi-level converters face other challenges compared to Si IGBT modules. SiC MOSFET modules are much more expensive than Si IGBT modules and have an inherent thermal imbalance characteristic. Methods have been proposed to effectively alleviate the thermal imbalance problem. However, such an approach transfers more switching action from the short commutation loop to the long commutation loop. Such an approach will result in higher system level switching losses.
Accordingly, a system and method that addresses the above-mentioned problems is desired.
Disclosure of Invention
In accordance with an embodiment of the present technique, a system is provided having a voltage converter and a controller that controls operation of the voltage converter. The voltage converter includes a plurality of branches, wherein each branch includes first and second sets of silicon (Si) -based power devices connected across first and second Direct Current (DC) voltage sources, respectively, and to each other at a fourth interconnection node. The first group of silicon-based power devices includes first and second silicon-based power devices connected to each other at a first interconnect node. In addition, the second set of silicon-based power devices includes third and fourth silicon-based power devices connected to each other at a second interconnect node. The system also includes a first set of silicon carbide (SiC) -based power devices coupled across the first and second interconnect nodes, wherein the first set of silicon carbide-based power devices includes first and second silicon carbide-based power devices connected to each other at a third interconnect node. The system also includes a buffer capacitor connected across the first and second interconnect nodes.
In accordance with another embodiment of the present technique, a system is provided having a voltage converter and a processor controlling operation of the voltage converter. The voltage converter includes a plurality of branches, wherein each branch includes a first set of silicon (Si) -based power devices coupled to a first DC voltage source and a second set of silicon-based power devices coupled to a second DC voltage source. The first group of silicon-based power devices and the second group of silicon-based power devices are coupled in series. The voltage converter also includes a first set of silicon carbide (SiC) -based power devices coupled with the first set of silicon-based power devices and the second set of silicon-based power devices and a snubber capacitor connected across the first set of silicon carbide-based power devices. The processor is configured to control the switching of each silicon carbide-based power device of the first group of silicon carbide-based power devices and each silicon-based power device of the first group of silicon-based power devices and the second group of silicon-based power devices such that, at any given time, one silicon carbide-based power device of the first group of silicon carbide-based power devices conducts current in series with one silicon-based power electronic device of the first group of silicon-based power electronic devices or the second group of silicon-based power electronic devices.
Drawings
These and other features and aspects of embodiments of the present invention will be better understood when the following detailed description is read with reference to the accompanying drawings in which like characters represent like parts throughout the drawings, wherein:
fig. 1 shows a schematic diagram of a three-level two-stage decoupled active neutral point clamped (3L-TDANPC) converter system according to an embodiment;
FIG. 2 is a diagram of a timing diagram of a voltage signal output by the 3L-TDANPC converter system and a gate signal provided to a switching device in the hybrid converter system of FIG. 1, according to an embodiment;
FIG. 3 illustrates a schematic diagram of four basic operating states (positive, P-type zero, negative, and N-type zero) of a 3L-TDANPC converter according to an embodiment;
FIG. 4 shows a schematic diagram depicting a commutation loop for a 3L-TDANPC converter in accordance with an embodiment;
FIG. 5 shows a schematic diagram depicting a commutation process without damping in a 3L-TDANPC converter, in accordance with an embodiment;
FIG. 6 shows a schematic diagram depicting a commutation process with single pulse damping technique in a 3L-TDANPC converter, in accordance with an embodiment;
FIG. 7 shows a schematic diagram depicting a commutation process without any damping mechanism in a 3L-TDANPC converter with output voltage positive and output current negative, in accordance with an embodiment;
FIG. 8 shows a schematic diagram depicting a commutation process with gate-off active damping technique in a 3L-TDANPC converter, in accordance with an embodiment;
FIG. 9 illustrates a graphical diagram of simulation results for a thermal modeling based 3L-TDANPC converter, according to an embodiment;
FIG. 10 shows a graphical diagram of an efficiency curve of a 3L-TDANPC converter based on simulation results according to an embodiment; and
FIG. 11 shows a schematic diagram depicting fault current in a 3L-TDANPC converter during a short circuit fault, according to an embodiment.
Detailed Description
Unless defined otherwise, technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. As used herein, the terms "first," "second," and the like, do not denote any order, quantity, or importance, but rather are used to distinguish one element from another. Also, the terms "a" and "an" do not denote a limitation of quantity, but rather denote the presence of at least one of the referenced item. The term "or" is intended to be inclusive and mean one, some, or all of the listed items. The use of "including," "comprising," or "having" and variations thereof herein is meant to encompass the items listed thereafter and equivalents thereof as well as additional items. The terms "connected" and "coupled" are not restricted to physical or mechanical connections or couplings, and may include direct or indirect electrical connections or couplings. Further, the terms "circuit" and "circuitry" and "controller" may include a single component or multiple components that are active and/or passive and are connected or otherwise coupled together to provide the described functionality.
As used herein, the term "module" refers to software, hardware or firmware, or any combination thereof, or any system, process or function that performs or facilitates the processes described herein.
A topology is proposed, which is referred to as a three-level two-stage decoupled active neutral point clamped (3L-TDANPC) converter. The 3L-TDANPC converter is internally provided with an IGBT module and a SiC MOSFET module. The commutation loops of the SiC MOSFETs are all within the module to keep switching losses low. In addition, the use of the IGBT module contributes to a significant reduction in system cost, and can limit the short-circuit current flowing through the SiC MOSFET to a very safe level.
By way of introduction, fig. 1 shows a schematic diagram of a three-level two-stage decoupled active neutral point clamped (3L-TDANPC)
In one embodiment, the Si power electronics and SiC power electronics of the 3L-
In some embodiments,
In one embodiment, the first Si IGBT T1 is connected to the second Si IGBT T2 at a
In the same manner, a plurality of
Each
The AC output voltage of
In one embodiment, the switching of
In general, as described above, the
However, when the gate signal is removed from the
In certain embodiments, the
It should be noted that fig. 2 is merely one example of a gate signal and that other methods of generating a gate signal are within the scope of the present technology, as described below. In one embodiment, the
FIG. 3 shows a schematic diagram of four basic operating states of a 3L-TDANPC converter according to an embodiment, namely: a positive (P) state (50); a P-type zero state (52); a negative (N) state (54); and an N-type zero state (56). As previously described, the output voltage of the 3L-TDANPC converter is an AC voltage waveform. Here, the positive state means that the voltage at the
In each operating state, the controller is configured to turn on one silicon-based power device (i.e., switch T1 or switch T2) from the first group of silicon-based power devices and turn on another silicon-based power device (i.e., switch T3 or T4) from the second group of silicon-based power devices. Further, in each operating state, the controller is configured to turn on one of the silicon carbide based power devices, i.e., switch T5 or switch T6, such that one of the silicon carbide based power devices and the turned on one of the silicon based power devices together carry the load current in series.
As can be seen from fig. 3, the silicon-based power device and the silicon carbide-based power device carrying the load current in series comprise: i) switches T1 and T5 during the
When the 3L-TDANPC converter switches from the
When the polarity of the output voltage changes from positive to negative, the P-
Due to parasitic inductances in the converter, resonant currents will be observed during switching of the 3L-TDANPC converter, causing thermal and electromagnetic interference (EMI) problems if not properly damped, especially under heavy load conditions. The parasitic inductance in the converter depends on the system configuration and mechanical layout. Accordingly, a mitigation method of damping such resonances is described herein.
Fig. 5 shows a schematic diagram describing the commutation process in a 3L-TDANPC converter without any damping mechanism. In the case where the output voltage and output current of the 3L-TDANPC converter are both positive, the schematic diagram 80 depicts the "forward" operation of the 3L-TDANPC converter, the schematic diagram 82 depicts the "while commutating" operation of the 3L-TDANPC converter, and the schematic diagram 84 represents the "reverse" operation of the 3L-TDANPC converter. It should be noted that each of the
The diagram 80 shows that before the commutation process starts, i.e. at the current ILBefore commutation from switch T5 to switch T6, switches T1 and T5 carry the load current IL. At a current ILAfter commutation from T5 to T6, the current ILWill continue to flow through switch T1 and charge the
in addition, the voltage variation (Δ V) of the buffer capacitorsnub) Is determined by the value (I) of the load current. For the above case, if the load current value is 600A:
if the DC bus voltage is 1000V, the buffer capacitor voltage will be in the range of 877V to 1123V.
It should be noted that without any damping mechanism, the energy of the LC resonance will eventually be damped due to the impedance in the commutation loop. However, it is desirable to dissipate most of the energy in the Si devices, rather than other components in the commutation loop, because it is much easier to cool the Si GBT module than other components such as buffer capacitors. In addition, to minimize any EMI related issues, it is desirable to damp the resonance as quickly as possible. Thus, according to embodiments of the present technique, a single pulse damping method is used.
Fig. 6 shows a schematic diagram depicting a commutation process with single pulse damping technique in a 3L-TDANPC converter. In the case where both the output voltage and the output current of the 3L-TDANPC converter are positive, the schematic 90 depicts the "forward" operation of the 3L-TDANPC converter, while the schematic 92 depicts the "backward" operation of the 3L-TDANPC converter. It should be noted that each of the
In the single pulse damping method, the
It should be noted that fig. 6 discloses the operation of the 3L-TDANPC converter when the output voltage is positive and the output current is positive. However, in other cases, for example, when the output voltage is zero and the current is positive and when both the output voltage and the current are negative, the same method may be employed. In other words, the single pulse damping method described herein will damp the resonance as long as the output voltage polarity and the output current direction are the same or at least when the output voltage is zero.
Fig. 7 shows a schematic diagram of the commutation process without any damping mechanism in the 3L-TDANPC converter in case the output voltage is positive and the output current is negative. Diagram 100 depicts a "forward" operation of the 3L-TDANPC converter, diagram 102 depicts a "when commutating" operation of the 3L-TDANPC converter, and diagram 104 represents a "backward" operation of the 3L-TDANPC converter. It should be noted that each of the
When the output voltage is positive and the output current is negative, as shown in the diagram 100, the load current ILThrough the
Fig. 8 shows a schematic diagram describing the commutation process in a 3L-TDANPC converter employing Gate-Off active damping (Gate-Off active damping) technique. In the case where the output voltage is positive and the output current is negative, the diagram 110 depicts the "forward" operation of the 3L-TDANPC converter, while the diagram 112 depicts the "backward" operation of the 3L-TDANPC converter. It should be noted that each of the
In the gate-off active damping method, the
It should be noted that the single pulse damping method can also be used in cases where the output voltage polarity is different from the output current polarity if the current direction is unknown, e.g. when the current magnitude is not high enough to determine its direction. In this case, if resonance does occur, the effect is very limited because the current level itself is low.
FIG. 9 shows a
FIG. 10 shows a graphical diagram 130 of an efficiency curve of a 3L-TDANPC converter based on simulation results. The
It should be noted that SiC MOSFETs generally have a weak short-circuit capability compared to Si IGBTs, i.e., SiC MOSFETs cannot withstand short-circuit currents (fault currents) for as long a time as Si IGBTs. For example, if a Si IGBT can withstand 10 μ s of short circuit current, a SiC MOSFET can withstand 1 or 2 μ s of short circuit current. However, in the 3L-TDANPC converter described herein, the SiC MOSFETs, i.e., switches T5 and T6, can withstand fault currents (short circuit currents) in excess of 10 μ s without the need for use in gate drivesAny other short circuit current protection scheme. As shown in fig. 11, during a short circuit condition, the fault current flowing through switch T5 or T6 is composed of two parts: (1) i energy from buffer capacitor1And (2) i from the DC bus capacitor2. During short-circuit faults, i due to low loop inductance1Is very fast, but the energy stored in the buffer capacitor is limited. For example, for the schematic 140 shown in FIG. 11, the total energy is only 2J, and thus the energy dissipated in each module is negligible. Furthermore, the high loop inductance will limit the current i2Di/dt of (1). Furthermore, the current i2Is limited by the saturation current level of the IGBT. For example, for a 600A IGBT, when the gate voltage is 15V, i2Will saturate at 3000A, which is further shared by the two SiC modules. Therefore, it is safe for SiC MOSFETs to carry such low short circuit currents until the fault is cleared by desat protection in the IGBT gate driver.
Advantages of this converter topology include: (1) the small commutation loop is realized due to the addition of the buffer capacitor, so that the switching loss of the IGBT and the SiC MOSFET is low; (2) low cost because SiC MOSFETs are used only on the AC side; (3) in this topology, the heat distribution between the switching devices is balanced; and (4) short-circuit fault capability of the SiC MOSFET due to the IGBT.
This written description uses examples to explain the disclosure, including the best mode, and also to enable any person skilled in the art to practice the disclosure, including making and using any devices or systems and performing any incorporated methods. The patentable scope of the disclosure is defined by the claims, and may include other examples that occur to those skilled in the art. Such other examples are intended to be within the scope of the claims if they have structural elements that do not differ from the literal language of the claims, or if they include equivalent structural elements with insubstantial differences from the literal languages of the claims.
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