阅读说明：本技术 电流积分方法和电路 (Current integration method and circuit ) 是由 弗里多林·米歇尔 于 2018-07-04 设计创作，主要内容包括：使用运算跨导放大器和积分电容器的并联连接,将输入电流(I<Sub>in</Sub>)转换为输出积分电压(V<Sub>out_int</Sub>)。经由产生反馈脉冲的数模转换器通过反馈回路使所述积分电容器反复放电来降低所述输出积分电压,其中,反馈时钟周期(T<Sub>clk_DAC</Sub>)用于定义反馈脉冲的连续上升沿之间的时间间隔。在相隔多个反馈时钟周期(T<Sub>clk_DAC</Sub>)之后,在扩展的反馈时钟周期(T*)期间执行采样。(Inputting a current (I) using a parallel connection of an operational transconductance amplifier and an integrating capacitor in ) Conversion to an output integration voltage (V) out_int ). Reducing the output integrated voltage by repeatedly discharging the integration capacitor through a feedback loop via a digital-to-analog converter generating a feedback pulse, wherein a feedback clock period (T) clk_DAC ) For defining the time interval between successive rising edges of the feedback pulse. At intervals of a number of feedback clock cycles (T) clk_DAC ) In-line with the aboveThereafter, sampling is performed during an extended feedback clock period (T).)

1. A current integration method, comprising:

using an Operational Transconductance Amplifier (OTA) and an integrating capacitor (C)_int) Is connected in parallel, to input a current (I)_in) Conversion to an output integration voltage (V)_{out_int})，

-passing the integrating capacitor (C) through a feedback loop via a digital-to-analog converter (DAC, SC DAC1) generating a feedback pulse_int) Repeatedly discharging to reduce the output integration voltage (V)_{out_int}) In which the clock period (T) is fed back_{clk_DAC}) For defining a time interval between successive rising edges of said feedback pulse, an

At intervals of a number of feedback clock cycles (T)_{clk_DAC}) Thereafter, sampling is performed during an extended feedback clock period (T).

2. The method of claim 1, wherein

The extended feedback clock period (T) is the feedback clock period (T)_{clk_DAC}) Is N times longer.

3. The method of claim 1 or 2, further comprising:

reducing a gain-bandwidth product (GBW) of the Operational Transconductance Amplifier (OTA) during sampling.

4. The method according to one of claims 1 to 3, the method further comprising:

integrating voltage (V) to output before sampling_{out_int}) A range check is performed, the range check being based on a plurality of feedback pulses prior to sampling.

5. Method according to one of claims 1 to 4, wherein

The digital-to-analog converters (DAC, SC DAC1) are switched capacitor digital-to-analog converters.

6. Method according to one of claims 1 to 4, wherein

The digital-to-analog converter (DAC) is a switched current source digital-to-analog converter.

7. The method according to one of claims 1 to 6, the method further comprising:

by applying a further digital-to-analog converter (SC DAC2) in the feedback loop, further feedback pulses are generated between the feedback pulses generated by said digital-to-analog converter (SC DAC 1).

8. A current integration method, comprising:

using an Operational Transconductance Amplifier (OTA) and an integrating capacitor (C)_int) Is connected in parallel, to input a current (I)_in) Conversion to an output integration voltage (V)_{out_int})，

-passing the integrating capacitor (C) through a feedback loop via a digital-to-analog converter (DAC, SC DAC1) generating a feedback pulse_int) Repeatedly discharging to reduce the output integration voltage (V)_{out_int})，

Applying electrical power (P) to the Operational Transconductance Amplifier (OTA), an

Only at the sampling time (T)_sample) During which the applied electrical power (P) is increased for sampling.

9. A circuit for current integration, comprising:

integrating capacitor (C)_int) A parallel connection of an Operational Transconductance Amplifier (OTA) and a feedback loop, wherein the Operational Transconductance Amplifier (OTA) is configured to couple an input current (I)_in) Conversion to an output integration voltage (V)_{out_int})，

A digital-to-analog converter (DAC, SC DAC1) in the feedback loop, the digital-to-analog converter (DAC, SC DAC1) configured to generate the trigger the integrating capacitor (C)_int) Feedback pulse of discharge, wherein the feedback clock period (T)_{clk_DAC}) For defining a time interval between successive rising edges of said feedback pulse, an

A controller configured to be spaced apart by a plurality of feedback clock periods (T)_{clk_DAC}) Thereafter providing the extensionIs fed back to the clock cycle (T).

10. The circuit of claim 9, wherein:

the controller is configured to integrate the voltage (V) into the output before sampling_{out_int}) A range check is performed, the range check being based on a number of feedback pulses prior to sampling.

11. A circuit according to claim 9 or 10, wherein

The digital-to-analog converters (DAC, SC DAC1) are switched capacitor digital-to-analog converters.

12. A circuit according to claim 9 or 10, wherein

The digital-to-analog converter (DAC) is a switched current source digital-to-analog converter.

13. The circuit of one of claims 9 to 12, further comprising:

a further digital-to-analog converter (SC DAC2) in a feedback loop, wherein the controller is configured to alternate operation of the digital-to-analog converter (SC DAC1) and the further digital-to-analog converter (SC DAC 2).

14. A circuit for current integration, comprising:

integrating capacitor (C)_int) A parallel connection of an Operational Transconductance Amplifier (OTA) configured to couple an input current (I) and a feedback loop_in) Conversion to an output integration voltage (V)_{out_int})，

A digital-to-analog converter (DAC, SC DAC1) in the feedback loop, the digital-to-analog converter (DAC, SC DAC1) configured to generate the trigger the integrating capacitor (C)_int) The feedback pulse of the discharge is sent back to the discharge,

a power supply for the electrical power (P) of the Operational Transconductance Amplifier (OTA), and

a controller configured to increase the applied electrical power (P) only during the sampling time.