阅读说明：本技术 电源输入控制电路 (Power input control circuit ) 是由 傅丰文 于 2018-08-30 设计创作，主要内容包括：一种电源输入控制电路,适用于具有二个电源输入端口的一电子装置,电源输入控制电路具有切换电路、二极管以及电压转换元件耦接于二个电源输入埠之间。当电压转换元件被致能(enable)时,将第二电源输入端口的主电源电压转换为副电源电压,且经由二极管传送至电子装置的副电源输入节点。而当电压转换元件被失能(disable)时,不输出副电压位准。切换电路根据第一电源输入端口的讯号决定是否致能电压转换元件被致能。藉此隔离二电源输入埠的电源供给,避免短路而使电子元件损坏。(A power input control circuit is suitable for an electronic device with two power input ports, and the power input control circuit is provided with a switching circuit, a diode and a voltage conversion element which are coupled between the two power input ports. When the voltage conversion element is enabled, the main power voltage of the second power input port is converted into a secondary power voltage, and the secondary power voltage is transmitted to a secondary power input node of the electronic device through the diode. When the voltage conversion device is disabled, the sub-voltage level is not outputted. The switching circuit determines whether the enable voltage conversion element is enabled according to a signal of the first power input port. Thereby isolating the power supply of the two power input ports and avoiding the damage of the electronic device caused by short circuit.)

1. A power input control circuit, suitable for an electronic device having a first power input port and a second power input port, wherein when the first power input port is connected to a first power supply unit, the first power supply unit provides a main power voltage to a first main voltage terminal of the first power input port and provides a sub power voltage to a first sub voltage terminal of the first power input port, and when the second power input port is connected to a second power supply unit, the second power supply unit provides the main power voltage to a second main voltage terminal of the second power input port, the power input control circuit comprising:

a main power input node coupled to the first main voltage terminal for receiving the main power voltage;

a secondary power input node coupled to the first secondary voltage terminal for receiving the secondary power voltage;

a diode having a cathode coupled to the secondary power input node;

a voltage conversion element coupled between the second main voltage terminal and the anode of the diode and having an enable pin, wherein when the enable pin receives an enable signal, the main power voltage provided by the second main voltage terminal is converted into the auxiliary power voltage to be output to the anode of the diode, and when the enable pin receives a disable signal, the auxiliary power voltage is not output;

a switching circuit, coupled to the enable pin of the voltage converting device and a first power start terminal of the first power input port, for providing the disable signal to the enable pin of the voltage converting device when receiving a first power start signal of the first power start terminal, and for providing the enable signal to the enable pin of the voltage converting device when not receiving the first power start signal of the first power start terminal; and

and a switching unit coupled between the second main voltage terminal and the main power input node for selectively connecting the second main voltage terminal to the main power input node according to a control signal.

2. The power input control circuit of claim 1, wherein the switching circuit further comprises:

a first MOS transistor, the gate of which is coupled to the first power start terminal, the drain of which is coupled to the enable pin of the voltage conversion device, and the source of which is coupled to the ground terminal;

a first resistor coupled between the gate of the first MOS transistor and the ground terminal;

a second resistor coupled between the drain of the first MOS transistor and the second main voltage terminal;

a third resistor coupled between the drain of the first MOS transistor and ground; and

and the capacitor is coupled between the drain of the first MOS transistor and the grounding end.

3. The power input control circuit of claim 1, wherein the switching unit is a second MOS transistor, a drain of the second MOS transistor is coupled to the second main voltage terminal, a source of the second MOS transistor is coupled to the main power input node, and the control signal is input to a gate of the second MOS transistor.

4. The power input control circuit of claim 3, wherein the control signal is provided by one of a baseboard management controller, a jumper, and a complex programmable logic device.

5. The power input control circuit of claim 1, wherein the gate of the second MOS transistor receives a control signal of a low voltage level or a ground voltage when the first power input port is connected to the first power supply unit.

6. The power input control circuit of claim 1, wherein when the power supply unit provides the main power voltage to the first main voltage terminal of the first power input port, the first power supply unit further provides the first power enable signal to the first power enable terminal.

7. The power input control circuit of claim 1, wherein the power input control circuit is disposed in an electronic device, the primary power input node is configured to provide system power for the electronic device, and the secondary power input node is configured to provide standby power for the electronic device.

8. The power input control circuit of claim 7, wherein the system power of the electronic device is a main power voltage and the standby power of the electronic device is a sub power voltage.

9. The power input control circuit of claim 1 wherein the diode is a schottky diode.

[ technical field ] A method for producing a semiconductor device

The present invention relates to a power input control circuit, and more particularly to a power input control circuit for an electronic device having two power input ports.

[ background of the invention ]

Conventionally, in an electronic device having two power input ports, Back-to-Back field effect transistors (Back-to-Back MOSFETs) are usually provided to prevent the power of the two power input ports from affecting each other. As shown in FIG. 1, an electronic device 10 with two power input ports includes power input ports P1 and P2 for connecting to power supply units PW1 and PW2, respectively. The MOS transistors Q2, Q3 form back-to-back field effect transistors disposed between the power input ports P1, P2 to prevent the power inputs of the two power input ports P1, P2 from affecting each other.

In detail, when the power input port P1 is connected to the power supply unit PW1, a controller or a processing unit (not shown) of the electronic device generates a control signal to the gates of the MOS transistors Q1, Q2, and Q3, and turns off the MOS transistors Q1, Q2, and Q3 (turn off), so as to prevent the power supply unit PW2 is connected to the power input port P2 at the same time, so that the power supplied by the power supply unit PW2 is conducted to the power supply unit PW1 to cause an abnormality. Therefore, the main power voltage (e.g., 12V) provided by the main voltage terminal Vm1 of the power input port P1 is conducted to the main power input node Nm to provide the system power for the electronic device after startup, and the sub power voltage (e.g., 5V) provided by the sub voltage terminal Vs1 of the power input port P1 is conducted to the sub power input node Ns to provide the standby power for the electronic device.

On the other hand, when the power input port P1 is not connected to the power supply unit PW1, the controller or the processing unit of the electronic device generates control signals to turn on the MOS transistors Q1, Q2, and Q3, respectively (turn on). At this time, if the power supply unit PW2 is connected to the power input port P2, the main power voltage of the main voltage terminal Vm2 of the power input port P2 is conducted to the main power input node Nm through the MOS transistor Q1 to provide the system power for the electronic device after being started, and is converted into the sub power voltage through the voltage conversion device 11 and then conducted to the sub power input node Ns through the MOS transistors Q2 and Q3 to provide the standby power for the electronic device.

However, by isolating the two Power input terminals through the back-to-back field effect transistors, the current at the two Power input terminals is larger, which not only causes more Power Dissipation (Power Dissipation) of the MOS transistors, but also increases the risk of instantaneous current breakdown of the back-to-back field effect transistors. In addition, the design of the back-to-back field effect transistor traditionally occupies more hardware space, and also increases the manufacturing cost. Therefore, there is a need for an improved power input control circuit.

[ summary of the invention ]

The present invention provides a power input control circuit, which can isolate the power supply of two power input ports to avoid the damage of electronic devices due to short circuit.

To solve the above technical problem, the power input control circuit of the present invention is applicable to an electronic device having a first power input port and a second power input port, wherein when the first power input port is connected to a first power supply unit, the first power supply unit provides a main power voltage to a first main voltage terminal of the first power input port and provides a sub power voltage to a first sub voltage terminal of the first power input port, and when the second power input port is connected to a second power supply unit, the second power supply unit provides the main power voltage to a second main voltage terminal of the second power input port, the power input control circuit includes: a main power input node coupled to the first main voltage terminal for receiving the main power voltage; a secondary power input node coupled to the first secondary voltage terminal for receiving the secondary power voltage; a diode (diode) having a cathode coupled to the auxiliary power input node; a voltage conversion device (MPS1495) coupled between the second main voltage terminal and the anode of the diode and having an enable pin, wherein when the enable pin receives an enable signal, the main power voltage provided by the second main voltage terminal is converted into the auxiliary power voltage to be output to the anode of the diode, and when the enable pin receives a disable signal, the auxiliary power voltage is not output; a switching circuit, coupled to the enable pin of the voltage converting device and a first power source start terminal of the first power source input port, for providing the disable signal (disable) to the enable pin of the voltage converting device when receiving a first power source start signal of the first power source start terminal, and for providing the enable signal to the enable pin of the voltage converting device when not receiving the first power source start signal of the first power source start terminal; and a switching unit coupled between the second main voltage terminal and the main power input node for selectively connecting the second main voltage terminal and the main power input node according to a control signal.

Preferably, the switching circuit further includes: a first MOS transistor, the gate of which is coupled to the first power start terminal, the drain of which is coupled to the enable pin of the voltage conversion device, and the source of which is coupled to the ground terminal; a first resistor coupled between the gate of the first MOS transistor and the ground terminal; a second resistor coupled between the drain of the first MOS transistor and the second main voltage terminal; a third resistor coupled between the drain of the first MOS transistor and ground; and a capacitor coupled between the drain of the first MOS transistor and ground.

Preferably, the switching unit is a second MOS transistor, a drain of the second MOS transistor is coupled to the second main voltage terminal, a source of the second MOS transistor is coupled to the main power input node, and the control signal is input to a gate of the second MOS transistor. In some preferred embodiments, the control signal is provided by one of a Baseboard Management Controller (BMC), a Jumper (Jumper), and a complex programmable logic device (CPLE). In some preferred embodiments, when the first power input port is connected to the first power supply unit, the gate of the second MOS transistor receives a control signal of a low voltage level or a ground voltage.

Preferably, when the power supply unit provides the main power voltage to the first main voltage terminal of the first power input port, the first power supply unit further provides the first power start signal to the first power start terminal.

Preferably, the power input control circuit is disposed in an electronic device, the main power input node is used for providing a system power of the electronic device, and the auxiliary power input node is used for providing a standby power of the electronic device. In some embodiments, the system power of the electronic device is a main cell voltage and the standby power of the electronic device is a sub-power voltage.

Preferably, the diode is a Schottky diode (Schottky diode).

Compared with the prior art, the invention replaces the back-to-back field effect transistor arranged between the power input ports by the arrangement of the switching circuit and the diode, thereby avoiding the mutual influence of the power inputs of the two power input ports.

[ description of the drawings ]

Fig. 1 is a schematic diagram of a conventional power input control circuit.

Fig. 2 is a schematic diagram of a power input control circuit according to an embodiment of the invention.

[ detailed description ] embodiments

The embodiments or examples shown in the figures are expressed in a particular manner as set forth below. It is to be understood that the embodiment or examples are not to be construed as limiting. Any alterations and modifications in the described embodiments, and any further applications of the principles of the invention as described herein are contemplated as would normally occur to one skilled in the art to which the invention relates.

Fig. 2 is a schematic diagram of a power input control circuit 20 according to an embodiment of the invention. The power input control circuit 20 is disposed in an electronic device 200 having two power input ports P1 and P2. As shown in fig. 2, the power input control circuit 20 may be electrically connected to the power supply unit PW1 through the power input port P1, and the power input control circuit 20 may also be electrically connected to the power supply unit PW2 through the power input port P2. In addition, the power supply unit PW1 provides a main power voltage (e.g., 12V) for system power of the electronic apparatus 200 to be provided to a central processing unit, a memory, a network card, etc., and a sub power voltage (e.g., 5V) for standby power of the electronic apparatus 200. The power supply unit PW2 is a voltage source for providing only the main power voltage, and in order to provide the sub power voltage to the electronic device 200, the power input control circuit 20 further provides a voltage conversion element 21 for converting the main power voltage outputted by the power supply unit PW2 into the sub power voltage to be provided to the sub power input node Ns. In some embodiments of the present invention, the power input port P1 has 24 pins (e.g., 24-Pin power connector under ATX12V standard), and the power input port P2 has 4 pins (e.g., 4-Pin power connector under ATX12V standard).

In some embodiments of the present invention, when the power input port P1 is connected to the power supply unit PW1, the main power voltage of the power supply unit PW1 is provided to the main voltage terminal Vm1 of the power input port P1, and the sub power voltage is provided to the sub voltage terminal Vs1 of the power input port P1. When the power input port P2 is connected to the power supply unit PW2, the power supply unit PW2 provides the main power voltage to the main voltage terminal Vm2 of the power input port P2.

In some embodiments of the present invention, the power input control circuit 20 includes a main power input node Nm, a sub power input node Ns, a diode Ds, a voltage conversion element 21, a switching circuit 22, and a switching unit SW. The main power voltage outputted by the power supply unit PW1 or PW2 is provided to the electronic apparatus 200 as a system power for the electronic apparatus 200 to use as a power source during operation, via a main power input node Nm, which is disposed between the switching unit SW and the main voltage terminal Vm1 of the power input port P1 and is coupled to a component (e.g., a central processing unit, a memory, a network card, etc.) of the electronic apparatus 200 that requires the main power voltage. In addition, the sub-power voltage outputted by the power supply unit PW1 or the sub-power voltage outputted by the voltage converting element 21 is provided to the electronic device 200 as a standby power through the sub-power input node Ns disposed between the Cathode (Cathode) of the diode Ds and the sub-voltage terminal Vs1 of the power input port P1 for the standby of the electronic device 200.

In some embodiments of the present invention, the switching unit SW is switched by a control signal provided by a Baseboard Management Controller (BMC), a Jumper (Jumper) or a Complex Programmable Logic Device (CPLD), when the power input port P1 is connected to the power supply unit PW1, the provided control signal turns Off (Turn Off) the switching unit SW to open the connection between the node Nm and the main voltage terminal Vm2, thereby preventing the current of the main voltage power provided by the main voltage terminal Vm1 of the power input port P1 from flowing to the main voltage terminal Vm2 and being fed back to the sub-voltage terminal Vs1 of the power input port P1 through the voltage conversion device 21 and the diode Ds to cause damage. On the contrary, when the power input port P1 is not connected to the power supply unit PW1, the provided control signal turns On the switching unit SW (Turn On) to short-circuit the node Nm and the main voltage terminal Vm2, so that the main voltage outputted from the main voltage terminal Vm2 of the power supply unit PW2 can be provided to the electronic device 200 through the main power input node Nm for use as the system power. For the embodiment of fig. 2, the switching unit SW can be a MOS transistor, a Drain (Drain) of the MOS transistor is coupled to the main voltage terminal Vm2 of the power input port P2, a Source (Source) of the MOS transistor is coupled to the main voltage terminal Vm1 of the power input port P1, and a control signal is inputted to a Gate (Gate) of the MOS transistor to switch the MOS transistor on or off. It should be understood that the MOS transistor is only an example, and the switching unit SW of the present invention is not limited thereto.

In some embodiments, the diode Ds is a Schottky diode (Schottky diode). The cathode of the diode Ds is coupled to the sub-voltage terminal Vs1 of the power input port P1, and the anode of the diode Ds is coupled to the voltage conversion device 21. The input terminal of the voltage conversion device 21 is coupled to the main voltage terminal Vm2 of the power input port P2, and the output terminal of the voltage conversion device 21 is coupled to the anode of the diode Ds. The voltage conversion device 21 further has an Enable pin EN, and when the Enable pin EN receives an Enable signal (Enable) with a high voltage level, the main power voltage provided by the main voltage terminal Vm2 is converted into a sub power voltage (for example, 12V to 5V), and is outputted from the output terminal to the anode of the diode Ds. On the contrary, when the enable pin EN receives the Disable signal (Disable) of the low voltage level or the ground voltage, the output terminal of the voltage converting element 21 does not output a signal. In some embodiments of the present invention, the voltage converting element 21 may be a voltage dropping circuit or a voltage dropping element (e.g., the circuit chip MPS 1495).

The switch circuit 22 is coupled to the enable pin EN of the voltage conversion device 21 and the power enable PW-OK of the power input port P1. The switching circuit 22 is used for selectively outputting an enable signal or a disable signal to the enable pin EN of the voltage conversion element according to the signal of the power start terminal PW-OK. In some embodiments, after the power supply unit PW1 is connected to the power input port P1, when the power supply unit PW1 starts to provide the main power voltage, the power supply unit PW1 provides a power-on signal (e.g., a high voltage level) to the power-on terminal PW-OK. On the contrary, when the power supply unit PW1 does not output the main power voltage, the power up terminal PW-OK is at a low voltage level or ground voltage.

Thus, when the switching circuit 22 receives the power-on signal from the power-on terminal PW-OK, the switching circuit 22 correspondingly provides the disable signal to the enable pin EN of the voltage converting element 21, so that the voltage converting element 21 stops outputting the sub-power voltage. When the switching circuit 22 does not receive the power-up signal from the power-up terminal, the switching circuit 22 correspondingly provides an enable signal to the enable pin EN of the voltage converting device 21, so that the voltage converting device 21 converts the main power voltage provided by the main voltage terminal Vm2 and starts to output the sub-power voltage.

In some embodiments of the present invention, the switching circuit 22 includes resistors R1, R2, R3, a capacitor C, and a MOS transistor Q4. One end of the resistor R1 is coupled to the gate of the MOS transistor Q4 and the power-on terminal PW-OK, and the other end of the resistor R1 is coupled to the ground terminal. One end of the resistor R2 is coupled to the drain of the MOS transistor Q4, the resistor R3, the capacitor C, and the enable pin EN, and the other end of the resistor R2 is coupled to the main voltage terminal Vm 2. One end of the resistor R3 is coupled to the drain of the MOS transistor Q4, the resistor R2, the capacitor C, and the enable pin EN, and the other end of the resistor R3 is coupled to the ground. One end of the capacitor C is coupled to the drain of the MOS transistor Q4, the resistors R2, R3, and the enable pin EN, and the other end of the capacitor C is coupled to the ground.

For clarity of the present invention, the operation of the relevant elements in the power input control circuit 20 when the power input port P1 is connected to the power supply unit PW1 is described below with reference to FIG. 2. When the power supply unit PW1 is coupled to the power input port P1, the bmc or the jumper will provide a control signal to turn off the switching unit SW, so as to prevent the power supply unit PW2 from being simultaneously connected to the power input port P2, and the main power voltages provided by the power supply units PW1 and PW2 form short circuits through the main voltage terminals Vm1 and Vm2 and the switching unit SW, respectively, thereby generating a collision that the dual power supplies simultaneously flow through Nm to cause damage to the circuit or the electronic components flowing through.

On the other hand, when the power supply unit PW1 starts to provide the main power voltage to the main voltage terminal Vm1 of the power input port P1, the power supply unit PW1 will provide the power-on signal with a high voltage level to the power-on terminal PW-OK. Then, after the MOS transistor Q4 of the switching circuit 22 receives the power-on signal with the high voltage level, the MOS transistor Q4 is turned on, so that the enable pin EN of the voltage converting device 21 is electrically connected to the ground terminal. Thereby controlling the output terminal of the voltage conversion device 21 not to output a signal and making the diode Ds non-conductive. Therefore, the sub-power voltage output by the voltage conversion element 21 converting the main power voltage of the power supply unit PW2 is prevented from forming a short circuit with the voltage terminal Vs1 provided by the power supply unit PW 1. It should be appreciated that if a short circuit is formed, the current input of the sub power voltage provided from the main voltage terminal Vm2 of the power input port P2 through the voltage conversion device 21 and the current input of the sub power voltage provided from the sub voltage terminal Vs1 of the power input port P1 will flow into the sub power input node Ns at the same time, and the excessive current flow will cause the electronic components at the rear end of the sub power input node Ns to be damaged. Finally, the main power voltage provided by the power supply unit PW1 is provided to the electronic apparatus 200 via the main voltage terminal Vm1 and the main power input node Nm, and the sub-power voltage provided by the power supply unit PW1 is provided to the electronic apparatus 200 via the sub-voltage terminal Vs1 and the sub-power input node Ns.

It should be appreciated that, in some cases, the switching unit SW may be erroneously turned on by other voltage sources, for example, when the power supply unit PW1 is coupled to the power input port P1, if the instantaneous voltage or current of the main power voltage provided by the power supply unit PW1 is too large, the main power voltage at the main voltage terminal Vm1 may pass through the switching unit SW and the resistor R2 to the enable pin EN of the voltage conversion element 21, and since the time when the power supply unit PW1 provides the power-on signal to the power-on terminal PW-OK is slightly later than the main power voltage, the disabling signal cannot be timely provided to the enable pin EN to turn off the voltage conversion element 21. Finally, the voltage conversion device 21 may convert the main power voltage of the main voltage terminal Vm1 and output the sub power voltage, and the diode Ds is turned on to form a short circuit with the voltage terminal Vs1 provided by the power supply unit PW1, thereby causing damage to the electronic device. To avoid this, the switching circuit 22 of the present invention further provides a capacitor C at the node connected to the enable pin EN of the voltage conversion device 21, so that even if the main power voltage of the main voltage terminal Vm1 passes through the switching unit SW, a high voltage level (i.e., an enable signal) is not immediately generated at the enable pin EN. It should be appreciated that, since the enable pin EN is connected to the capacitor C, the main power voltage from the main voltage terminal Vm1 to the enable pin EN through the switching unit SW and the resistor R2 charges the capacitor C connected to the enable pin EN at the same time, so that the delay of the time point when the voltage on the enable pin EN rises to the level of the enabled (enable) voltage conversion element 21 is later than the time point when the power supply unit PW1 provides the main power voltage and the power enable signal provided together is coupled to the enable pin EN through the power enable terminal PW-OK so that the enable pin EN receives the Disable signal (Disable) of the low voltage level or the ground voltage. In detail, before the time point when the main power voltage from the main voltage terminal Vm1 to the enable pin EN through the switching unit SW and the resistor R2 causes the voltage on the enable pin EN to rise to the voltage conversion element 21, the voltage of the enable pin EN will first cause the power supply unit PW1 to provide the power-on signal to the power-on terminal PW-OK to turn on the MOS transistor Q4 to ground and cause the enable pin EN to receive the Disable signal (Disable) of the low voltage level or the ground voltage, so that the output terminal of the voltage conversion element 21 does not output the signal, that is, before the time point when the main power voltage from the main voltage terminal Vm1 to the enable pin EN through the switching unit SW and the resistor R2 causes the voltage on the enable pin EN to rise to the voltage conversion element 21 of the enable (enable), the enable pin EN will receive the Disable signal (Disable) of the low voltage level or the ground voltage, further, the voltage conversion element 21 is not activated and the sub power supply voltage is not outputted. In other words, in the case that the switching unit SW is turned on, even when the power supply unit PW1 starts to provide the main power voltage to the main voltage terminal Vm1 of the power input port P1, the time point when the power supply unit PW1 provides the power-on signal with the high voltage level to the power-on terminal PW-OK is earlier than the time point when the capacitor C is charged by the main power voltage to the enable voltage conversion element 21. Therefore, the sub-power voltage converted by the voltage conversion element 21 and the sub-power voltage provided by the power supply unit PW1 are prevented from forming a short circuit and causing damage to the electronic device.

On the other hand, the following description will be made with reference to fig. 2, wherein the relevant elements in the power input control circuit 20 operate after the power input port P2 is connected to the power supply unit PW2 when the power input port P1 is not connected to the power supply unit PW 1. When the power supply unit PW2 is coupled to the power input port P2, the bmc or the jumper will provide a control signal to turn on the switching unit SW, so that the main power voltage provided by the power supply unit PW2 is provided to the electronic device 200 via the main voltage terminal Vm2, the switching unit SW and the main power input node Nm.

On the other hand, since the power input port P1 is not connected to the power supply unit PW1, the MOS transistor Q4 of the switching circuit 22 is coupled to the ground terminal via the resistor R1, the MOS transistor Q4 is not turned on, and then the capacitor C is charged by the main power voltage provided by the power supply unit PW2, so that the (enable) voltage converting element 21 is enabled to convert the main power voltage at the main voltage terminal Vm1 and output the sub power voltage, which is provided to the electronic device 200 via the diode Ds and the sub power input node Ns.

In summary, the switching circuit 22 and the diode Ds are disposed to replace the back-to-back field effect transistor disposed between the power input ports P1 and P2, so as to prevent the power inputs of the two power input ports P1 and P2 from affecting each other. On the other hand, the invention omits a back-to-back field effect transistor of two MOS transistors, thereby greatly reducing power dissipation (PowerDissipation), and the arrangement of the diode Ds also reduces the risk of instantaneous current breakdown.

The methods of the present invention, or certain aspects or portions thereof, may take the form of program code. The program code may be embodied in tangible media, such as floppy diskettes, cd-roms, hard drives, or any other machine-readable storage medium, wherein, when the program code is loaded into and executed by a machine, such as a computer, the machine thereby becomes an apparatus for practicing the invention. The program code may also be transmitted over some transmission medium, such as over electrical wiring or cabling, through fiber optics, or via any other form of transmission, wherein, when the program code is received and loaded into and executed by a machine, such as a computer, the machine becomes an apparatus for practicing the invention. When implemented in a general-purpose processing unit, the program code combines with the processing unit to provide a unique apparatus that operates analogously to specific logic circuits.

While the present invention has been described with reference to the preferred embodiments, it is to be understood that the above disclosure is not intended to limit the embodiments. On the contrary, it is intended to cover various modifications and similar arrangements (as would be apparent to those skilled in the art). Furthermore, the appended claims are to be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.