Switching control circuit of radio frequency switch

文档序号：141463 发布日期：2021-10-22 浏览：29次中文

阅读说明：本技术 射频开关切换控制电路 (Switching control circuit of radio frequency switch ) 是由戴若凡于 2021-06-28 设计创作，主要内容包括：本申请涉及射频开关技术领域,具体涉及射频开关切换控制电路,包括：边沿检测延迟电路,用于在电源电压信号和射频切换控制输入信号的上升沿或下降沿,使得输出的时延脉冲信号产生高电平；稳压电路,用于对电源电压信号进行稳压,通过时延脉冲信号进行增压调整,输出稳定的增压电源信号；振荡电路,用于输出具有对应频率及幅度的振荡信号；振荡信号包括：对应时延脉冲信号的高电平期间的第一振荡信号,和对应时延脉冲信号低电平区间的第二振荡信号,第一振荡信号的频率及幅度大于第二振荡信号的频率及幅度；负电荷泵电路,被配置为能够实现负压快速建立并增加负压输出；射频电路利能够进行快速充放电实现射频开关的快速切换。(The application relates to radio frequency switch technical field, concretely relates to radio frequency switch switches control circuit, include: the edge detection delay circuit is used for switching and controlling the rising edge or the falling edge of the input signal between the power supply voltage signal and the radio frequency so as to enable the output time delay pulse signal to generate a high level; the voltage stabilizing circuit is used for stabilizing the voltage of the power supply voltage signal, performing boosting adjustment through the time delay pulse signal and outputting a stable boosted power supply signal; an oscillation circuit for outputting an oscillation signal having a corresponding frequency and amplitude; the oscillation signal includes: the frequency and the amplitude of the first oscillating signal are greater than those of the second oscillating signal; a negative charge pump circuit configured to enable rapid negative pressure build-up and increase negative pressure output; the radio frequency circuit can be charged and discharged quickly to realize quick switching of the radio frequency switch.)

1. A radio frequency switch switching control circuit, the radio frequency switch switching control circuit comprising:

the edge detection delay circuit is used for switching and controlling the rising edge or the falling edge of the input signal between the power supply voltage signal and the radio frequency so as to enable the output time delay pulse signal to generate a high level;

the output voltage adjusting end of the voltage stabilizing circuit is configured to receive the time delay pulse signal, and is used for stabilizing the voltage of the power supply voltage signal and outputting a stable boosted power supply signal by performing boosting adjustment during the high level period of the time delay pulse signal;

the amplitude-frequency adjusting end of the oscillating circuit is configured to receive the time delay pulse signal and is used for outputting an oscillating signal with corresponding frequency and amplitude according to the time delay pulse signal; the oscillation signal includes: a first oscillation signal corresponding to a high level period of the time delay pulse signal and a second oscillation signal corresponding to a low level interval of the time delay pulse signal; the first oscillating signal has a first oscillating frequency and a first voltage amplitude, and the second oscillating signal has a second oscillating frequency and a second voltage amplitude; the first oscillation frequency is greater than the second oscillation frequency, and the first voltage amplitude is greater than the second voltage amplitude;

a negative charge pump circuit configured to perform fast charging and discharging according to the oscillation signal, so that a negative voltage is quickly established and a negative voltage is quickly increased to generate a charge pump output signal;

and the radio frequency circuit is configured to control a radio frequency switch to switch rapidly according to the charge pump output signal and the boosting power supply signal.

2. The radio frequency switch switching control circuit of claim 1, wherein a first one of the oscillating signals is configured to cause the negative charge pump circuit to charge, discharge, and output a first negative voltage at a first switching frequency and amplitude;

a second oscillation signal of the oscillation signals configured to cause the negative charge pump circuit to charge, discharge, and output a second negative voltage at a second conversion frequency and amplitude;

the first conversion frequency and the amplitude are both larger than the second conversion frequency and the amplitude, and the amplitude of the first negative pressure is larger than the amplitude of the second negative pressure.

3. The radio frequency switch switching control circuit of claim 1, wherein the edge detection delay circuit comprises:

the edge detection circuit is used for detecting the rising edge or the falling edge of the power supply voltage signal and the radio frequency switching control input signal and outputting a short pulse signal;

and the delay control circuit is used for carrying out pulse width delay control on the short pulse signal and generating a delay pulse signal with fixed high level width.

4. The radio frequency switch switching control circuit of claim 3, wherein the edge detection circuit includes an OR gate, a first detection branch, and a second detection branch;

the output end of the first detection branch and the output end of the second detection branch are respectively connected with one input end of the or gate, and the output end of the or gate is the output end of the edge detection circuit;

the first detection branch comprises a first buffer and a first exclusive-or gate, an input end of the first buffer and an input end of the first exclusive-or gate are configured to receive the power supply voltage signal, an output end of the first buffer is connected with another input end of the first exclusive-or gate, and an output end of the first exclusive-or gate is an output end of the first detection branch;

the second detection branch comprises a second buffer and a second exclusive-or gate, an input end of the second buffer and an input end of the second exclusive-or gate are configured to receive the radio frequency switching control input signal, an output end of the second buffer is connected to another input end of the second exclusive-or gate, and an output end of the second exclusive-or gate is an output end of the second detection branch.

5. The radio frequency switch switching control circuit of claim 3, wherein the delay control circuit comprises: the MOS transistor comprises a first NMOS transistor, a second MOS transistor, a variable resistor, a variable polarity capacitor and a first phase inverter;

the grid electrode of the first NMOS tube is connected with the output end of the edge detection circuit, the drain electrode of the first NMOS tube is connected with one end of the variable resistor, the source electrode of the first NMOS tube is grounded, and the other end of the variable resistor is configured to receive the boosting power supply signal;

the grid electrode of the second MOS tube, the positive electrode of the variable polarity capacitor and the input end of the first phase inverter are connected and connected with the drain electrode of the first NMOS tube, the source electrode and the drain electrode of the second MOS tube, and the negative electrode of the variable polarity capacitor are connected and connected with the source electrode of the first NMOS tube;

the output end of the first inverter is the output end of the delay control circuit.

6. The radio frequency switch switching control circuit according to claim 1, wherein the oscillation circuit includes n stages of oscillation units in inverted cascade, an output terminal of a last stage of oscillation unit being connected to an input terminal of a first stage of oscillation unit in inverted phase; wherein n is an odd number greater than 1;

any one of the oscillating units comprises an input end, an output end and an amplitude-frequency adjusting end;

the output end of the previous stage oscillation unit is reversely connected with the input end of the next stage oscillation unit, and the output end of the last stage oscillation unit is reversely connected with the input end of the first stage oscillation unit;

the amplitude-frequency adjusting end is configured to receive a time delay pulse signal generated by the edge detection delay circuit;

and the output end of the last-stage oscillation unit is connected with the input end of a fourth phase inverter in an inverted manner, and the output end of the fourth phase inverter is the output end of the oscillation circuit.

7. The radio frequency switch switching control circuit according to claim 6, wherein any of the oscillating units comprises: the NMOS transistor comprises a first PMOS transistor, a second phase inverter, a third NMOS transistor and a fourth NMOS transistor;

the input end of the oscillation unit is connected with the input end of the second phase inverter, the grid electrode of the first PMOS tube and the grid electrode of the third NMOS tube, and the output end of the second phase inverter, the drain electrode of the first PMOS tube and the drain electrode of the third NMOS tube are connected and connected with the output end of the oscillation unit;

the amplitude-frequency adjusting end is connected with the input end of a third phase inverter and the grid electrode of a fourth NMOS transistor, the output end of the third phase inverter is connected with the grid electrode of a second PMOS transistor, the drain electrode of the second PMOS transistor is connected with the source electrode of the first PMOS transistor, and the source electrode of the second PMOS transistor is configured to receive the boosting power supply signal;

the drain electrode of the fourth NMOS tube is connected with the source electrode of the third NMOS tube, and the source electrode of the fourth NMOS tube is grounded.

8. The radio frequency switch switching control circuit of claim 1, wherein the voltage regulator circuit includes a bandgap reference circuit, an error amplifier, a third PMOS transistor, and an output voltage regulator circuit;

the input end of the band-gap reference circuit is configured to obtain the power supply voltage signal, and the output end of the band-gap reference circuit outputs a reference voltage signal;

the input end of the output voltage adjusting circuit is configured to receive the boosting power supply signal, the output voltage adjusting end is configured to receive the time-delay pulse signal, and a feedback signal is output according to the boosting power supply signal and the time-delay pulse signal;

the input end of the error amplifier is configured to receive the reference voltage signal and the feedback signal respectively, the output end of the error amplifier is connected to the gate of the third PMOS transistor, the drain of the third PMOS transistor is the output end of the voltage stabilizing circuit, and the source of the third PMOS transistor is configured to receive the supply voltage signal.

9. The radio frequency switch switching control circuit of claim 8, wherein the output voltage adjustment circuit comprises a first resistance adjustment unit and a second resistance adjustment unit connected in series;

the connected node of the first resistance adjusting unit and the second resistance adjusting unit is used for outputting the feedback signal;

the first resistance adjusting unit comprises a first output voltage adjusting end, and the second resistance adjusting unit comprises a second output voltage adjusting end; the first output voltage adjustment terminal and the second output voltage adjustment terminal are configured to receive the time-delayed pulse signal;

the resistance value of the first resistance adjusting unit is adjusted to be increased by the time delay pulse signal, and the resistance value of the second resistance adjusting unit is adjusted to be decreased by the time delay pulse signal.

10. The radio frequency switch switching control circuit of claim 9, wherein the first resistance adjustment unit comprises: the NMOS transistor comprises a first adjusting resistor, a second adjusting resistor, a first adjusting NMOS transistor and a first adjusting PMOS transistor;

the grid electrode of the first adjusting NMOS tube is connected with the grid electrode of the first adjusting PMOS tube and serves as the first output voltage adjusting end; the source electrode of the first adjusting NMOS tube is connected with the drain electrode of the first adjusting PMOS tube and is used as a connection node of the first resistance adjusting unit and the second resistance adjusting unit;

one end of the first adjusting resistor is connected with one end of the second adjusting resistor and configured to receive the boosting power supply signal, the other end of the first adjusting resistor is connected with the drain electrode of the first adjusting NMOS tube, and the other end of the second adjusting resistor is connected with the source electrode of the first adjusting PMOS tube.

11. The radio frequency switch switching control circuit of claim 9, wherein the second resistance adjustment unit comprises: a third adjusting resistor, a fourth adjusting resistor and a second adjusting NMOS tube;

the grid electrode of the second adjustment NMOS tube is the second output voltage adjustment end, and the drain electrode of the second adjustment NMOS tube is used as a connection node of the first resistance adjustment unit and the second resistance adjustment unit;

and the two ends of the third adjusting resistor are respectively connected with the source electrode and the drain electrode of the second adjusting NMOS tube, the source electrode of the second adjusting NMOS tube is also connected with one end of the fourth adjusting resistor, and the other end of the fourth adjusting resistor is grounded.

Technical Field

The application relates to the technical field of radio frequency switches, in particular to a radio frequency switch switching control circuit capable of improving starting and switching speeds of a radio frequency switch.

Background

The rf switch is a commonly used device in the rf path, and is used to control the rf signal transmission path and the signal size, and its performance indexes include isolation, insertion loss, and switching time.

In the related art, the rf switching time of the device includes the rf switch transient time and the rf switch switching time. The radio frequency switch transient is used as follows: when the radio frequency switch is turned on, the radio frequency output is increased from 10% to 90% of the required time (when the radio frequency switch is started), or when the radio frequency switch is turned on, the radio frequency output is decreased from 90% to 10% of the required time (when the radio frequency switch is turned off). The switching time of the radio frequency switch is as follows: when the radio frequency switch is turned on, the time required from the control voltage being at 50% point to the radio frequency output increasing to 90%, or when the radio frequency switch is turned off, the time required from the control voltage being at 50% point to the radio frequency output decreasing to 10%

However, in the related art, the size of the rf switch device, the gate bias resistance, and the body bias resistance are set, which requires compromises and balances in terms of isolation and insertion loss of the device, and in terms of the rf switching time of the device, making it difficult to shorten the rf switch transient time and to switch the rf switch.

Disclosure of Invention

The application provides a radio frequency switch switching control circuit capable of improving starting and switching speeds of a radio frequency switch, and can solve the problem that the radio frequency switch is difficult to switch when transient use of the radio frequency switch is shortened in the related technology.

The application provides a radio frequency switch switches control circuit, radio frequency switch switches control circuit includes:

a radio frequency circuit configured to control a radio frequency switch to switch fast according to the charge pump output signal and the charge pump output signal.

Optionally, a first oscillation signal of the oscillation signals is configured to cause the negative charge pump circuit to charge and discharge at a first conversion frequency and amplitude, and output a first negative voltage;

the first conversion frequency and amplitude are larger than the second conversion frequency and amplitude, and the amplitude of the first negative pressure is larger than the amplitude of the second negative pressure.

Optionally, the edge detection delay circuit comprises:

and the delay control circuit is used for carrying out pulse width delay control on the short pulse signal and generating a delay pulse signal with fixed high level width.

Optionally, the edge detection circuit includes an or gate, a first detection branch and a second detection branch;

Optionally, the delay control circuit comprises: the MOS transistor comprises a first NMOS transistor, a second MOS transistor, a variable resistor, a variable polarity capacitor and a first phase inverter;

the output end of the first inverter is the output end of the delay control circuit.

Optionally, the oscillation circuit includes n stages of oscillation units in inverse cascade, and an output end of the last stage of oscillation unit is connected to an input end of the first stage of oscillation unit in inverse phase; wherein n is an odd number greater than 1;

any one of the oscillating units comprises an input end, an output end and an amplitude-frequency adjusting end;

the amplitude-frequency adjusting end is configured to receive a time delay pulse signal generated by the edge detection delay circuit;

Optionally, any of the oscillation units comprises: the NMOS transistor comprises a first PMOS transistor, a second phase inverter, a third NMOS transistor and a fourth NMOS transistor;

the drain electrode of the fourth NMOS tube is connected with the source electrode of the third NMOS tube, and the source electrode of the fourth NMOS tube is grounded.

Optionally, the voltage stabilizing circuit includes a bandgap reference circuit, an error amplifier, a third PMOS transistor, and an output voltage adjusting circuit;

the input end of the band-gap reference circuit is configured to obtain the power supply voltage signal, and the output end of the band-gap reference circuit outputs a reference voltage signal;

Optionally, the output voltage adjusting circuit includes a first resistance adjusting unit and a second resistance adjusting unit connected in series;

the connected node of the first resistance adjusting unit and the second resistance adjusting unit is used for outputting the feedback signal;

Optionally, the first resistance adjustment unit includes: the NMOS transistor comprises a first adjusting resistor, a second adjusting resistor, a first adjusting NMOS transistor and a first adjusting PMOS transistor;

Optionally, the second resistance adjustment unit includes: a third adjusting resistor, a fourth adjusting resistor and a second adjusting NMOS tube;

The technical scheme at least comprises the following advantages: the method comprises the steps of detecting the power-on starting time of a power supply voltage signal and the switching time of a radio frequency switching control input signal through an edge detection delay circuit, and generating a time delay pulse signal with fixed-width time delay, wherein the time delay pulse signal is at a high level at the power-on starting time of the power supply voltage signal and the switching time of the radio frequency switching control input signal. The output of the voltage stabilizing circuit can be increased during the high level period of the time delay pulse signal to generate a boosting power supply signal, and the oscillation circuit can generate a first conversion frequency signal and a second conversion frequency signal which are alternately generated, wherein the first conversion frequency is higher than the second conversion frequency, so that the negative charge pump circuit can be quickly increased during the first conversion frequency period, the charge pump output signal VSS generated by the negative charge pump circuit can quickly reach the required voltage, the charging and discharging time of the negative charge pump circuit is shortened, and the quick start of the negative charge pump circuit and the quick switching of the radio frequency switch are realized.

Drawings

In order to more clearly illustrate the detailed description of the present application or the technical solutions in the prior art, the drawings needed to be used in the detailed description of the present application or the prior art description will be briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative efforts.

Fig. 1 illustrates a schematic diagram of a switching control circuit of a radio frequency switch according to an embodiment of the present application;

FIG. 2 shows a timing diagram of the signals in the embodiment of FIG. 1;

FIG. 3 illustrates a circuit schematic of an embodiment of an edge detect delay circuit;

FIG. 4 illustrates a schematic diagram of an oscillator circuit provided by an embodiment of the present application; .

Fig. 5 shows a schematic circuit diagram of an embodiment of one of the oscillator units OSC Cell of fig. 4;

FIG. 6 illustrates a circuit schematic of one embodiment of a voltage regulator circuit;

fig. 7 shows a circuit schematic of an embodiment of the output voltage adjustment circuit shown in fig. 6.

Detailed Description

The technical solutions in the present application will be described clearly and completely with reference to the accompanying drawings, and it is obvious that the described embodiments are some, but not all embodiments of the present application. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

In the description of the present application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are only for convenience of description and simplicity of description, and do not indicate or imply that the device or element being referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus, should not be construed as limiting the present application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.

In the description of the present application, it is to be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; the connection can be mechanical connection or electrical connection; the two elements may be directly connected or indirectly connected through an intermediate medium, or may be communicated with each other inside the two elements, or may be wirelessly connected or wired connected. The specific meaning of the above terms in the present application can be understood in a specific case by those of ordinary skill in the art.

In addition, the technical features mentioned in the different embodiments of the present application described below may be combined with each other as long as they do not conflict with each other.

Fig. 1 shows a schematic diagram of a switching control circuit of a radio frequency switch according to an embodiment of the present application, and referring to fig. 1, it can be seen that the switching control circuit of the radio frequency switch includes: a stabilizing circuit 110, an edge-detect delay circuit 120, an oscillator circuit 130, a negative charge pump circuit 140, and a radio frequency circuit 150.

The edge-detect delay circuit 120 is configured to receive a supply voltage signal VDD and a radio frequency switching control input signal VC, and output a time-delayed pulse signal VDP according to the supply voltage signal VDD and the radio frequency switching control input signal VC. At the time of the rising edge or the falling edge of the power supply voltage signal VDD and the rf switching control input signal VC, the edge detection delay circuit 120 generates the high level of the delay pulse signal VDP, otherwise, the edge detection delay circuit 120 generates the low level of the delay pulse signal VDP. Wherein, the high level of the time delay pulse signal VDP has an adjustable fixed pulse width. The rf switch control input signal VC and the power supply voltage signal VDD are provided by other external circuit inputs (not shown).

The output voltage adjusting terminal of the voltage stabilizing circuit 110 is configured to receive the delay pulse signal VDP, and is configured to stabilize the power supply voltage signal VDD, and output a stable boosted power supply signal VCC by performing a boosting adjustment when the delay pulse signal VDP is at a high level.

The amplitude-frequency adjustment end of the oscillation circuit 130 is configured to receive the time-delayed pulse signal VDP, and output an oscillation signal CLK with a corresponding frequency and amplitude according to the time-delayed pulse signal VDP. Referring to fig. 2, which shows a timing diagram of signals in the embodiment shown in fig. 1, as can be seen from fig. 2, the oscillation signal CLK includes: a first oscillation signal C1 corresponding to the high level period DH of the delayed pulse signal VDP, and a second oscillation signal C2 corresponding to the low level period DL of the delayed pulse signal VDP. The first oscillating signal C1 has a first oscillating frequency f1 and a first voltage amplitude V1, and the second oscillating signal C2 has a second oscillating frequency f2 and a second voltage amplitude V2. The first oscillation frequency f1 of the first oscillation signal C1 is greater than the second oscillation frequency f2 of the second oscillation signal C2, and the first voltage amplitude V1 of the first oscillation signal C1 is greater than the second voltage amplitude V2 of the second oscillation signal C2.

The negative charge pump circuit 140 is configured to receive the oscillation signal CLK output by the oscillation circuit 130 and the boost power supply signal VCC, and is configured to perform fast charging and discharging according to the frequency and amplitude of the oscillation signal CLK to implement fast negative voltage establishment and increase the negative voltage output to generate the charge pump output signal VSS. In this embodiment, the first oscillation frequency f1 and the first voltage amplitude V1 of the oscillation signal CLK enable the negative charge pump circuit 140 to perform charging and discharging at a first conversion frequency and amplitude and output a first negative voltage, and the second oscillation frequency f2 and the second voltage amplitude V2 of the oscillation signal CLK enable the negative charge pump circuit 140 to perform charging and discharging at a second conversion frequency and amplitude and output a second negative voltage, where the first conversion frequency and amplitude are both greater than the second conversion frequency and amplitude, and the first negative voltage is greater than the second negative voltage, so that the charge pump output signal VSS generated by the negative charge pump circuit 140 can quickly establish a required voltage, shorten the charging and discharging time of the negative charge pump circuit 140, and realize quick start of the negative charge pump circuit 140.

The rf circuit 150 is configured to receive the charge pump output signal VSS output by the negative charge pump circuit 140 and the boost power supply signal VCC output by the voltage stabilizing circuit 110, and perform fast charging and discharging of all actual control signals in the rf switch by using the boost power supply signal VCC and the charge pump output signal VSS with increased negative voltage, so as to realize fast switching of the rf switch.

In this embodiment, the edge detection delay circuit 120 detects the power-on start time of the power supply voltage signal VDD and the switching time of the radio frequency switching control signal VC, and generates a delay pulse signal VDP with adjustable fixed-width delay, where the delay pulse signal VDP is at a high level at the power-on start time of the power supply voltage signal VDD and the switching time of the radio frequency switching control input signal VC. The high-level period DH of the time-delay pulse signal VDP can boost the output of the voltage regulator circuit 110 to generate the boosted power supply signal VCC, and on the other hand, the oscillation circuit 130 can generate the first oscillation signal C1 and the second oscillation signal C2 which are alternately generated, the first oscillation frequency f1 of the first oscillation signal C1 is greater than the second oscillation frequency f2 of the second oscillation signal C2, and the first voltage amplitude V1 of the first oscillation signal C1 is greater than the second voltage amplitude V2 of the second oscillation signal C2, so that the negative charge pump circuit 140 can boost and output the increased negative voltage quickly during the first conversion frequency f1, and the charge pump output signal VSS generated by the negative charge pump circuit 140 can reach the required voltage quickly, thereby shortening the charging and discharging time of the negative charge pump circuit 140, and realizing the quick start of the negative charge pump circuit 140 and the quick switching of the radio frequency switch.

With continued reference to fig. 1, the edge detection delay circuit 120 includes an edge detection circuit 121 and a delay control circuit 122.

The edge detection circuit 121 is configured to receive a power supply voltage signal VDD and a radio frequency switching control input signal VC, and is configured to detect a power-on start time of the power supply voltage signal VDD and a switching time of the radio frequency switching control input signal VC, and output a short pulse signal VP, where the output short pulse signal VP is at a high level with a narrow width at a rising edge or a falling edge of the power supply voltage signal VDD and the radio frequency switching control input signal VC.

As can be seen from fig. 2, at the power-on starting time of the power supply voltage signal VDD, i.e. at the power-on starting time, the power supply voltage signal VDD generates a rising edge, and the short pulse signal VP forms a high level with a narrow width; at the switching instant of the rf switching control input signal VC, i.e. the falling edge of the rf switching control input signal VC shown in fig. 2, the short pulse signal VP also forms a high level with a narrow width.

The delay control circuit 122 is configured to receive the short pulse signal VP generated by the edge detection circuit 121, and perform pulse width delay adjustable control on the short pulse signal VP to generate a delay pulse signal VDP with a fixed and adjustable high level width.

With continued reference to fig. 2, comparing the short pulse signal VP and the delayed pulse signal VDP in fig. 2, it can be seen that the delayed pulse signal VDP delays and widens the high level of the short pulse signal VP to form a high level period DH with a wide width in the delayed pulse signal VDP.

With continued reference to fig. 1, the rf circuit 150 includes a logic decoding level shift circuit 151 and an rf switch circuit 152. The logic decoding level shift circuit 151 is configured to receive the rf switching control input signal VC, the charge pump output signal VSS, and the boost power signal VCC, and output an rf switching level shift signal. The rf switching level shift signal is used to control the rf switch in the rf switch circuit 152 to perform a switching operation, which can establish different transmission paths between the rf input terminal RFin and the rf output terminal RFout.

Fig. 3 shows a schematic circuit diagram of an embodiment of the edge detection delay circuit, and as can be seen from fig. 3, the edge detection delay circuit 120 includes an edge detection circuit 121 and a delay control circuit 122.

The edge detection circuit 121 includes an OR gate OR, a first detection branch 310, and a second detection branch 320.

The output terminal of the first detecting branch 310 and the output terminal of the second detecting branch 320 are respectively connected to an input terminal of the OR gate OR, and the output terminal of the OR gate OR is the output terminal of the edge detecting circuit 121, and is used for outputting the short pulse signal VP.

The first detection branch 310 comprises a first buffer 311 and a first exclusive or gate XOR1, an input of the first buffer 311 and an input of the first exclusive or gate XOR1 being configured to receive the supply voltage signal VDD. An output terminal of the first buffer 311 is connected to another input terminal of the first exclusive or gate XOR1, and an output terminal of the first exclusive or gate XOR1 is an output terminal of the first detection branch 310.

The second detection branch 320 comprises a second buffer 312 and a second exclusive or gate XOR2, an input of the second buffer 312 and an input of the second exclusive or gate XOR2 being configured to receive the radio frequency switching control input signal VC, an output of the second buffer 312 being connected to another input of the second exclusive or gate XOR2, an output of the second exclusive or gate XOR2 being an output of the second detection branch 320.

The delay control circuit 122 includes: the circuit comprises a first NMOS transistor N1, a second MOS transistor N2, a variable resistor R1, a variable polarity capacitor C1 and a first inverter INV 1.

The gate of the first NMOS transistor N1 is connected to the output terminal of the edge detection circuit 121, the drain of the first NMOS transistor N1 is connected to one end of the variable resistor R1, the source of the first NMOS transistor N1 is grounded, and the other end of the variable resistor R1 is configured to receive the boost power signal VCC.

The grid electrode of the second MOS tube N2, the positive electrode of the variable polarity capacitor C1 and the input end of the first inverter INV1 are connected with the drain electrode of the first NMOS tube N1, the source electrode and the drain electrode of the second MOS tube N2 and the negative electrode of the variable polarity capacitor C1 are connected with the source electrode of the first NMOS tube N1.

An output end of the first inverter INV1 is an output end of the delay control circuit 122, and is configured to output the high-level fixed-width delayed pulse signal VDP.

Fig. 4 shows a schematic diagram of an oscillation circuit provided in an embodiment of the present application, and referring to fig. 4, it can be seen that the oscillation circuit 130 includes n stages of inverting cascaded oscillation cells OSC Cell, where n is an odd number greater than 1.

Any of the oscillation cells OSC Cell in fig. 4 includes: an input end IN, an output end OUT and an amplitude-frequency adjusting end AD; the output end OUT of the previous stage of the oscillator unit OSC Cell is connected IN an inverted manner to the input end IN of the next stage of the oscillator unit OSC Cell, the output end OUT of the last stage of the oscillator unit OSC Cell is connected IN an inverted manner to the input end IN of the first stage of the oscillator unit OSC Cell, the amplitude and frequency adjustment end AD is configured to receive the time delay pulse signal VDP generated by the edge detection delay circuit 120, and the output end of the last stage of the oscillator unit OSC Cell, i.e., the third stage of the oscillator unit OSC Cell3, is also connected with the input end of a fourth inverter INV4 after being inverted, and the output end of the fourth inverter INV4 is the output end of the oscillator circuit 130, and is used for outputting the oscillator signal CLK IN which the first oscillator signal C1 and the second oscillator signal C2 alternate.

In the present embodiment, n is 3, that is, the oscillation circuit 130 of the present embodiment includes three stages of the oscillation cells OSC Cell1, namely, the first stage oscillation Cell OSC Cell1, the second stage oscillation Cell OSC Cell2, and the third stage oscillation Cell OSC Cell 3.

Fig. 5 shows a schematic circuit diagram of an embodiment of the oscillator unit OSC Cell of fig. 4, and as can be seen from fig. 5, the oscillator unit OSC Cell includes a first PMOS transistor P1, a second PMOS transistor P2, a second inverter INV2, a third inverter INV3, a third NMOS transistor N3, and a fourth NMOS transistor N4. An input end IN of the oscillation unit OSC Cell is connected to the input end of the second inverter INV2, the gate of the first PMOS transistor P1, and the gate of the third NMOS transistor N3. The output end of the second inverter INV2, the drain of the first PMOS transistor P1, and the drain of the third NMOS transistor N3 are connected to the output end OUT of the oscillation unit OSC Cell.

An amplitude-frequency adjustment end AD of the oscillation unit OSC Cell is connected to an input end of the third inverter INV3 and a gate of the fourth NMOS transistor N4, an output end of the third inverter INV3 is connected to a gate of the second PMOS transistor P2, a drain of the second PMOS transistor P2 is connected to a source of the first PMOS transistor P1, and a source of the second PMOS transistor P2 is configured to receive the boost power supply signal VCC.

The drain of the fourth NMOS transistor N4 of the oscillator unit OSC Cell is connected to the source of the third NMOS transistor N3, and the source of the fourth NMOS transistor N4 is grounded.

Fig. 6 shows a schematic circuit diagram of an embodiment of the voltage regulator circuit 110, and as can be seen from fig. 6, the voltage regulator circuit 110 includes a bandgap reference circuit 610, an error amplifier 620, a third PMOS transistor P3, and an output voltage regulator circuit 630.

The input terminal of the bandgap reference circuit 610 is configured to obtain the power voltage signal VDD, and the output terminal thereof outputs a reference voltage signal Vref.

The input terminal of the output voltage adjusting circuit 630 is configured to receive the boosted power signal VCC, and the output voltage adjusting terminal is configured to receive the delayed pulse signal VDP, and output a feedback signal Vf according to the boosted power signal VCC and the delayed pulse signal VDP.

The input terminal of the error amplifier 320 is configured to receive the reference voltage signal Vref and the feedback signal Vf, respectively, the output terminal of the error amplifier 320 is connected to the gate of the third PMOS transistor P3, the drain of the third PMOS transistor P3 is the output terminal of the regulator circuit 110, and the source of the third PMOS transistor P3 is configured to receive the power voltage signal VDD.

Fig. 7 shows a schematic circuit diagram of an embodiment of the output voltage adjusting circuit shown in fig. 6, and as can be seen from fig. 7, the output voltage adjusting circuit 630 includes a first resistance adjusting unit 631 and a second resistance adjusting unit 632 connected in series, and a connection node of the first resistance adjusting unit 631 and the second resistance adjusting unit 632 is used for outputting the feedback signal Vf.

The first resistance adjusting unit 631 comprises a first output voltage adjusting terminal, and the second resistance adjusting unit 632 comprises a second output voltage adjusting terminal; the first output voltage adjustment terminal and the second output voltage adjustment terminal are configured to receive a time-delayed pulse signal VDP.

The resistance value of the first resistance adjusting unit 631 is adjusted to increase by the delay pulse signal VDP, and the resistance value of the second resistance adjusting unit 632 is adjusted to decrease by the delay pulse signal VDP.

With reference to fig. 7, the first resistance adjusting unit 631 includes a first adjusting resistor R11, a second adjusting resistor R12, a first adjusting NMOS transistor N11, and a first adjusting PMOS transistor P11.

The grid electrode of the first adjusting NMOS tube N11 is connected with the grid electrode of the first adjusting PMOS tube P11 to be used as the first output voltage adjusting end. The source of the first adjustment NMOS transistor N11 is connected to the drain of the first adjustment PMOS transistor P11, and serves as the connection node between the first resistance adjustment unit 631 and the second resistance adjustment unit 632;

one end of the first adjusting resistor R11 is connected to one end of the second adjusting resistor R12, and is configured to receive the boost power supply signal VCC, the other end of the first adjusting resistor R11 is connected to the drain of the first adjusting NMOS transistor N11, and the other end of the second adjusting resistor R12 is connected to the source of the first adjusting PMOS transistor P11.

With continued reference to fig. 7, the second resistance adjustment unit 632 includes: a third adjusting resistor R21, a fourth adjusting resistor R22 and a second adjusting NMOS transistor N21;

the gate of the second adjustment NMOS transistor N21 is the second output voltage adjustment terminal. The drain of the second adjustment NMOS transistor N21 is used as the connection node between the first resistance adjustment unit 631 and the second resistance adjustment unit 632;

the two ends of the third adjusting resistor R21 are respectively connected to the source and the drain of the second adjusting NMOS transistor N21, the source of the second adjusting NMOS transistor N21 is further connected to one end of the fourth adjusting resistor R22, and the other end of the fourth adjusting resistor R22 is grounded to GND.

It should be understood that the above examples are only for clarity of illustration and are not intended to limit the embodiments. Other variations and modifications will be apparent to persons skilled in the art in light of the above description. And are neither required nor exhaustive of all embodiments. And obvious variations or modifications of this invention are intended to be covered by the scope of the invention as expressed herein.

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