Adaptive multi-level gate driver circuit and method for switching half-bridge circuit
阅读说明:本技术 自适应多电平栅极驱动器电路和用于切换半桥电路的方法 (Adaptive multi-level gate driver circuit and method for switching half-bridge circuit ) 是由 安德烈娅·路易吉·马里孔蒂 沃尔夫冈·弗兰克 克里斯蒂安·洛卡泰利 迭戈·拉福 达维德·雷斯 于 2019-08-26 设计创作,主要内容包括:公开了用于驱动功率开关的栅极驱动器电路和用于切换包括高侧器件和低侧器件的半桥电路的方法。该栅极驱动器电路包括:栅极驱动器,其具有用于接收输入信号的第一输入端和被耦接至功率开关的输出端,该栅极驱动器提供主栅极电流和辅助栅极电流;和差分电压传感器,其具有用于接收输入信号的第一输入端、被耦接至电源电压的第二输入端、被耦接至功率开关的端子的第三输入端和被耦接至栅极驱动器的第二输入端的输出端。(A gate driver circuit for driving a power switch and a method for switching a half bridge circuit including a high side device and a low side device are disclosed. The gate driver circuit includes: a gate driver having a first input for receiving an input signal and an output coupled to the power switch, the gate driver providing a main gate current and an auxiliary gate current; and a differential voltage sensor having a first input for receiving an input signal, a second input coupled to a supply voltage, a third input coupled to a terminal of the power switch, and an output coupled to the second input of the gate driver.)
1. A gate driver circuit for driving a power switch, comprising:
a gate driver having a first input for receiving an input signal and an output coupled to a power switch, the gate driver configured to provide a main gate current and an auxiliary gate current; and
a differential voltage sensor having a first input for receiving the input signal, a second input coupled to a supply voltage, a third input coupled to a terminal of the power switch, and an output coupled to the second input of the gate driver.
2. The gate driver circuit of claim 1, wherein the gate driver comprises:
a main driver configured to provide the main gate current; and
an auxiliary driver configured to provide the auxiliary gate current.
3. The gate driver circuit of claim 2, wherein the main driver is coupled to a first input of the gate driver and the auxiliary driver is coupled to a second input of the gate driver.
4. The gate driver circuit of claim 1, wherein the differential voltage sensor comprises:
a differentiator having an input coupled to the input of the differential voltage sensor and an input coupled to a differentiator reference voltage;
a comparator having an input coupled to the output of the differentiator, an input coupled to a comparator reference voltage, and an output; and
a logic circuit having a first input coupled to the output of the comparator, a second input for receiving the input signal, and an output coupled to the output of the differential voltage sensor.
5. The gate driver circuit of claim 4, wherein the differential voltage sensor further comprises an input stage for generating the differentiator reference voltage and the comparator reference voltage.
6. The gate driver circuit of claim 1, further comprising a diode coupled between the second input of the differential voltage sensor and the supply voltage.
7. The gate driver circuit of claim 1, further comprising a diode coupled between a third input of the differential voltage sensor and a terminal of the power switch.
8. A gate driver circuit for driving a power switch, comprising:
a first main driver having an input terminal for receiving a first input signal and an output terminal for providing a first gate current;
a first auxiliary driver having an input and an output for providing a first auxiliary gate current;
a first differential voltage sensor having a first input for receiving the first input signal, a second input coupled to a first supply voltage, a third input coupled to a terminal of the power switch, and an output coupled to an input of the first auxiliary driver;
a second main driver having an input terminal for receiving a second input signal and an output terminal for providing a second gate current;
a second auxiliary driver having an input and an output for providing a second auxiliary gate current; and
a second differential voltage sensor having a first input for receiving the second input signal, a second input coupled to a second supply voltage, a third input coupled to a terminal of the power switch, and an output coupled to an input of the second auxiliary driver.
9. The gate driver circuit of claim 8, wherein the first differential voltage sensor comprises:
a differentiator having an input coupled to the input of the first differential voltage sensor and an input coupled to a differentiator reference voltage;
a comparator having an input coupled to the output of the differentiator and an input coupled to a comparator reference voltage; and
a logic circuit having a first input coupled to the output of the comparator, a second input for receiving the first input signal, and an output coupled to the output of the first differential voltage sensor.
10. The gate driver circuit of claim 9, wherein the first differential voltage sensor further comprises an input stage for generating the differentiator reference voltage and the comparator reference voltage.
11. The gate driver circuit of claim 9, wherein the logic circuit comprises first and second outputs for driving first and second inputs of the first auxiliary driver.
12. The gate driver circuit of claim 8, wherein the second differential voltage sensor comprises:
a differentiator having an input coupled to the input of the second differential voltage sensor and an input coupled to a differentiator reference voltage;
a comparator having an input coupled to the output of the differentiator and an input coupled to a comparator reference voltage; and
a logic circuit having a first input coupled to the output of the comparator, a second input for receiving the second input signal, and an output coupled to the output of the second differential voltage sensor.
13. The gate driver circuit of claim 12, wherein the second differential voltage sensor further comprises an input stage for generating the differentiator reference voltage and the comparator reference voltage.
14. The gate driver circuit of claim 12, wherein the logic circuit comprises first and second outputs for driving first and second inputs of the second auxiliary driver.
15. A method for switching a half bridge circuit including a high side device and a low side device, the method comprising:
driving a control node of the high-side device with a first current pulse having a first pulse width;
driving a control node of the high-side device with a second current pulse during a duration of the first current pulse, the second current pulse having a second pulse width shorter than the first pulse width;
driving a control node of the low side device with a third current pulse having a third pulse width; and
driving a control node of the low side device with a fourth current pulse having a fourth pulse width shorter than the third pulse width during a duration of the third current pulse.
16. The method of claim 15, wherein the first current pulse occurs during a first portion and a second portion of a conduction event of the high-side device, and the second current pulse occurs only during the second portion of the conduction event of the high-side device.
17. The method of claim 15, wherein the first current pulse occurs during a first portion and a second portion of a turn-off event of the high-side device, and the second current pulse occurs only during the first portion of the turn-off event of the high-side device.
18. The method of claim 15, wherein the third current pulse occurs during a first portion and a second portion of a conduction event of the low side device, and the fourth current pulse occurs only during the second portion of the conduction event of the low side device.
19. The method of claim 15, wherein the third current pulse occurs during a first portion and a second portion of a turn-off event of the low side device, and the fourth current pulse occurs only during the first portion of the turn-off event of the low side device.
20. The method of claim 15, wherein the second pulse width is determined by sensing and differentiating a voltage across the high-side device, and wherein the fourth pulse width is determined by sensing and differentiating a voltage across the low-side device.
Technical Field
The present invention generally relates to systems and methods for adaptive multi-level gate drivers.
Background
FIG. 1A is a schematic 100 of an insulated gate bipolar transistor ("IGBT") 102, the insulated gate bipolar transistor ("IGBT") 102 including a parasitic capacitance C coupled between a gate and a collectorGCC coupled between the grid and the emitterGEAnd C coupled between the collector and the emitterCE。
FIG. 1B is a graph of the value of the parasitic capacitance shown in FIG. 1A versus the collector-emitter voltage, where CISSRepresents a capacitor CMAnd CGEAnd, COSSRepresents a capacitor CMAnd CCEAnd C isMRepresenting a miller capacitor that is highly non-linear due to the gain of the
Fig. 2A is a schematic diagram 200 of a prior art power switch including a high-side driver 206 and a low-side driver 204, a high-side gate resistor RgHS and a low-side gate resistor RgLS, and a high-side power transistor T1 and a low-side power transistor T2. The voltage V is shown in FIG. 2ACE(collector-to-emitter voltage), VG(gate voltage) and VOUT(voltage from low side gate driver) and current I associated with low side driverG(gate current) and IC(collector current).
For a given gate resistor, it takes a relatively long time to charge and discharge the parasitic capacitance shown in fig. 1A. Therefore, the propagation delay of the power transistor shown in fig. 2A is also relatively high. The portion of the propagation delay of the power transistor is referred to as the "dead time" which must be taken into account in half bridge applications to avoid cross conduction. Large propagation delays of the high-side and low-side devices of a half-bridge power switch occur mainly when turning off with low collector-to-emitter voltages ("VCE") or drain-to-source voltages ("VDS"). As shown in fig. 1B, the miller capacitance is very high in this case. Long propagation delays result in large dead time because the propagation delay at turn-on is short. This leads to disadvantages in terms of efficiency and accurate timing.
One solution for addressing propagation delay is by appropriate selection of the gate resistors RgLS and RgHS. The lower the gate resistance, the shorter the propagation delay. However, the gate resistance also dictates the switching speed. Therefore, the choice of gate resistor Rg is limited by other design constraints, such as the dv/dt limit of electromagnetic interference ("EMI") limits.
FIG. 2B is a timing diagram associated with the power switch of FIG. 2A, showing V for a given value of RgHS and RgLSOUT、VG、IG、VCEAnd ICThe waveform of (2). Also shown in FIG. 2B is I as the off currentOFFAnd (4) waveform.
Fig. 3A is a more detailed timing diagram associated with the on phase of the low side of the power switch in fig. 2A, and fig. 3B is a more detailed timing diagram associated with the off phase of the low side of the power switch in fig. 2A. The waveforms shown in fig. 3A and 3B include the gate voltage (V)G) Output voltage (V)S) Gate current (I)G) Collector current (I)C) And energy loss (E). The time parameters along the horizontal time axis of these waveforms include: t is tTH(time to reach threshold voltage), t1(time of Miller stage Start), t2(time of tail start in on mode or end in off mode) and t3(time of miller plateau end).
In the waveforms in fig. 3A and 3B showing the energy loss (E), consumed during switching of the power transistorEnergy is marked as ESWAnd the energy dissipated by conduction is labeled ECOND. Note that the energy consumed during switching of the power transistor includes a spike portion and a long "tail" portion. At the output voltage (V)S) An elongated tail can be seen in the visibly marked arrow portion of the waveform. The energy loss indicated by the tail results in large power switching losses.
It is therefore an object of the present invention to reduce propagation delay and power switching losses during switching of a power switch.
Disclosure of Invention
According to the method and circuit of the embodiment, both dead time and tail phenomenon are minimized, which in turn improves switching efficiency and allows more accurate switching timing of the power switch.
According to an embodiment, a gate driver circuit for driving a power switch includes: a gate driver having a first input for receiving an input signal and an output coupled to the power switch, the gate driver configured to provide a main gate current and an auxiliary gate current; and a differential voltage sensor having a first input for receiving an input signal, a second input coupled to a supply voltage, a third input coupled to a terminal of the power switch, and an output coupled to the second input of the gate driver.
Drawings
For a more complete understanding of the present invention and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which:
fig. 1A is a schematic diagram of an IGBT including parasitic capacitances as is known in the prior art;
FIG. 1B is a graph of the value of the parasitic capacitance shown in FIG. 1A versus the collector-emitter voltage;
fig. 2A is a schematic diagram 200 of a prior art power switch including high and low side drivers and high and low side gate resistors;
FIG. 2B is a timing diagram associated with the power switch of FIG. 2A;
fig. 3A is a timing diagram associated with the conduction phase of the low side of the power switch in fig. 2A;
fig. 3B is a timing diagram associated with the turn-off phase of the low side of the power switch in fig. 2A;
fig. 4A is a timing diagram associated with a conduction phase of a low side of a power switch, according to an embodiment;
fig. 4B is a timing diagram associated with a turn-off phase of a low side of a power switch, according to an embodiment;
fig. 5A is a block diagram of an integrated circuit gate driver and half-bridge power switches of a power switch system according to an embodiment;
FIG. 5B is a block diagram of a gate driver, a differential voltage sensor, and a single transistor power switch referenced to a first supply voltage, according to an embodiment;
fig. 5C is a block diagram of a gate driver, a differential voltage sensor, and a single transistor power switch referenced to a second supply voltage, according to an embodiment;
fig. 6 is a block diagram of a low side differential voltage sensor associated with the power switching system of fig. 5A;
fig. 7 is a timing diagram associated with the low side differential voltage sensor of fig. 6 during a turn-on event;
fig. 8 is a timing diagram associated with the low side differential voltage sensor of fig. 6 during a shutdown event;
fig. 9 is a timing diagram associated with the low side differential voltage sensor of fig. 6 during an on event and an off event;
FIG. 10 is a block diagram of a high-side differential voltage sensor associated with the power switching system of FIG. 5A;
FIG. 11 is a timing diagram associated with the high-side differential voltage sensor of FIG. 10 during a turn-on event;
FIG. 12 is a timing diagram associated with the high-side differential voltage sensor of FIG. 10 during a shutdown event;
FIG. 13 is a timing diagram associated with the high-side differential voltage sensor of FIG. 10 during an on event and an off event;
FIG. 14 is a schematic diagram of an input stage suitable for use in the low side differential voltage sensor of FIG. 6; and
fig. 15 is a schematic diagram of an input stage suitable for use in the high-side differential voltage sensor of fig. 10.
Detailed Description
According to an embodiment, a gate current of an output stage of a gate driver for a power switch is configured to depend on an output voltage V of the switchSSupply voltage (V) to the switchSSAnd DC +). In general, VSSIs a negative voltage supply or ground and DC + is a positive voltage supply. The absolute values of these voltages may be in the range of tens to hundreds of volts as required by the particular application and allowed by the particular switching technology.
Fig. 4A is a timing diagram associated with an on phase of a low side of a power switch, according to an embodiment, and fig. 4B is a timing diagram associated with an off phase of the low side of the power switch, according to an embodiment.
The following waveforms are shown in fig. 4A and 4B: gate voltage (V)G) (ii) a Output voltage (V)S) (ii) a Gate current (I)G) (ii) a Collector current (I)C) (ii) a Energy loss (E). Shows a structure having E as previously describedSWAnd ECONDPart of the energy is lost. VSOf wave form (at time t)2And time t3In between)
Compare FIG. 4A with FIG. 4B and 3A and 3B, E obtained by the enhanced gate current provided by the circuit embodiments described in further detail below can be clearly seenSWReduction of energy loss.
Referring to fig. 5A, the output voltage V is obtained using a diode D1 and a diode D2SThe difference from the supply voltage (this difference is hereinafter identified as av); at low side VS-VSS=ΔVLSAnd at the high side DC + -VS=ΔVHS. From these differential voltages and the on/off state of the power transistors (known to the user), the correct level of gate boost current is provided at the gates of the high-side and low-side power devices during both the on and off phases. The description for generating the differential voltage av, in particular using the input stage shown in fig. 14 and 15, is explained in further detail belowLSAnd Δ VHSThe correct mechanism of (2).
Analysis of previous power switch data tables and tests at VSThe average value (threshold value) Δ V is found where the previously described tail phenomenon starts to be exhibited (see arrow portions in fig. 3A and 3B). This threshold Δ V is hereinafter referred to as Δ Vth. The initial part of the tail phenomenon corresponds to the peak value of the miller capacitance. Once Δ V reaches or falls to Δ VthHereinafter, the gate current is enhanced. These voltage thresholds and the implementation of these voltage thresholds in a gate driver circuit for driving a power switching device are described in further detail below.
Fig. 5A is a block diagram of an integrated
An integrated
The gate driver integrated
The gate driver integrated
The following blocks are also shown in the integrated circuit gate driver 501: an
Finally, the lower voltage blocks 502, 504, 506, 508, 516, 522, 524 and D2 may all be integrated on the P substrate portion of the gate driver integrated
While a half-bridge implementation has been shown and described with respect to fig. 5A, a single transistor power switch implementation may also be used. A single transistor power switch system is described below with reference to fig. 5B and 5C. Depending on the implementation, a full-bridge implementation including four power transistors or devices (not shown) may also be used.
Fig. 5B is a block diagram of a
Fig. 5C is a block diagram of a
Fig. 6 is a block diagram of the low side
The low side sensor and
In operation, Δ V is sensed onceLSBeyond the pre-created threshold as described above, diode D2 provides compliance with avLSThe shape of (2). This signal is then combined with an adaptive voltage reference (V)REF) Together, are provided to the input of a
At the Output (OUT) of the differentiator 608DER) At each time of Δ VLSWhen reduced, the appearance of more than VREFPulses of level and in the opposite case below VREFA pulse of a level. The signal is input to a
A signal is required to provide an auxiliary current at the output of the power stage to provide a higher gate current when required. Thus, V of
The internal waveforms of the low side of the switching system are shown in the timing diagrams in fig. 7, 8 and 9, which are described in further detail below.
FIG. 7 is a timing diagram associated with the low side
FIG. 8 is a timing diagram associated with the low side
Fig. 9 is a timing diagram associated with the low side
Fig. 10 is a block diagram of the high-side
In more detail in block diagram form in fig. 10A high side sensor and
In operation, Δ V is sensed onceHSBeyond the pre-created threshold as described above, diode D1 provides compliance with avHSThe shape of (2). This signal is then combined with an adaptive voltage reference (V)REF) Together, are provided to the input of a
At the Output (OUT) of the differentiator 1008DER) At each time of Δ VHSWhen reduced, the appearance of more than VREFPulses of level and in the opposite case below VREFA pulse of a level. The signal is input to a
A signal is required to provide an auxiliary current at the output of the power stage to provide a higher when requiredThe gate current. Thus, V of
The internal waveforms of the high side of the switching system are shown in the timing diagrams in fig. 11, 12 and 13, which are described in further detail below.
FIG. 11 is a timing diagram associated with the high-side
FIG. 12 is a timing diagram associated with the high-side
FIG. 13 is a timing diagram associated with the high-side
Fig. 14 is an exemplary schematic diagram of a low-
In operation, the REF reference voltage is higher than VSSA substantially constant reference voltage for the power supply level. VREFThe reference voltage is a substantially constant reference voltage having a voltage higher than V in the first mode of operationSSA first nominal value of the power supply level and has a value higher than V in the second operating modeSSA second nominal value of the power supply level. The
Fig. 15 is an exemplary schematic diagram of a high-
In operation, the operation of the high-
While the invention has been described with reference to illustrative embodiments, this description is not intended to be construed in a limiting sense. Various modifications and combinations of the illustrative embodiments, as well as other embodiments of the invention, will be apparent to persons skilled in the art upon reference to the description. It is therefore intended that the appended claims cover any such modifications or embodiments.
- 上一篇:一种医用注射器针头装配设备
- 下一篇:一种主板虚拟开关电路及其工作方法