阅读说明：本技术 一种电子***芯片内部时钟校准方法 (Method for calibrating internal clock of electronic detonator chip ) 是由 *** 李明政 章鑫 徐平 赵鹏飞 熊江辉 王明 代弦德 于 2019-11-08 设计创作，主要内容包括：本发明公开了一种电子雷管芯片内部时钟校准方法,所述电子雷管为从机,所述从机由主机控制,所述主机包括周期唤醒模块,所述从机包括定时器,所述方法包括：获取所述定时器与所述主机之间的第一时差值；获取所述周期唤醒模块与所述主机之间的第二时差值；根据所述第一差值与所述第二差值得到第三时差值；根据定时器的累计运行时间与所述第三时差值得到所述定时器的真实运行时间。本发明对整个网络的校准采用分组模式,防止了所有模块同时工作导致供电电流过大。因此,本发明具有功耗低、抗干扰能力强、精度高的特点。(The invention discloses a method for calibrating an internal clock of an electronic detonator chip, wherein the electronic detonator is a slave computer, the slave computer is controlled by a host computer, the host computer comprises a periodic wake-up module, the slave computer comprises a timer, and the method comprises the following steps: acquiring a first time difference value between the timer and the host; acquiring a second time difference value between the periodic awakening module and the host; obtaining a third time difference value according to the first difference value and the second difference value; and obtaining the real running time of the timer according to the accumulated running time of the timer and the third time difference value. The invention adopts a grouping mode for the calibration of the whole network, thereby preventing the overlarge power supply current caused by the simultaneous work of all modules. Therefore, the invention has the characteristics of low power consumption, strong anti-interference capability and high precision.)

1. A method for calibrating an internal clock of an electronic detonator chip, wherein the electronic detonator is a slave, and the slave is controlled by a master, is characterized in that the master comprises a periodic wake-up module, the slave comprises a timer, and the method comprises the following steps:

acquiring a first time difference value between the timer and the host;

acquiring a second time difference value between the periodic awakening module and the host;

obtaining a third time difference value according to the first difference value and the second difference value;

and obtaining the real running time of the timer according to the accumulated running time of the timer and the third time difference value.

2. The method of electronic detonator chip internal clock calibration of claim 1 wherein the third time difference value is equal to the first time difference value plus the second time difference value.

3. The electronic detonator chip internal clock calibration method of claim 1 wherein the true running time of the timer is equal to the accumulated running time of the timer plus the third time difference value.

4. The electronic detonator chip internal clock calibration method according to claim 1, wherein all slaves are grouped, and the timer clocks of the slaves of each group are calibrated respectively.

5. The electronic detonator chip internal clock calibration method of claim 1, further comprising:

the host sends a calibration broadcast command with an address range;

if the communication address of the slave computer is in the address range, the slave computer enters a clock calibration pulse acquisition process; and if the communication address of the slave is not in the address range, the slave enters a bus idle monitoring mode.

6. The electronic detonator chip internal clock calibration method according to claim 1, wherein the first time difference value is obtained by capturing a pulse period of a signal transmitted by the host by the timer.

7. The method for calibrating the internal clock of the electronic detonator chip according to claim 1, wherein a fourth time difference value between a periodic wake-up module and the timer is obtained, and the second time difference value is obtained according to the fourth time difference value.

8. The electronic detonator chip internal clock calibration method of claim 6 wherein the characteristic matrix convolution is performed on the pulse period of the signal captured by the timer.

Technical Field

The invention relates to the field of electronic detonators, in particular to a method for calibrating an internal clock of an electronic detonator chip.

Background

Due to the fact that the RC oscillator inside the MCU is warm and drifts at present, and different voltages have influences on RC accuracy. The maximum error of the internal master clock of the low-cost general-purpose MCU is controlled within + -5%. And the maximum error of the low-speed clock precision inside the MCU is higher than the precision of the internal master clock. Some MCUs have RC errors at low speed greater than + -10%. In practical applications, directly using RC as the MCU internal timer clock would result in very large differences. If a plurality of MCU shall complete a certain delay unified output control, the time difference of MCU output control will be very large. The standard of the electronic detonator is that the delay error is less than +/-1.5 ms within the range of 0-150ms, and the precision is less than +/-1% when the delay error is greater than 150 ms. The working temperature of the electronic detonator is required to be-40-85 ℃. The current general MCU with low cost and ultra-low power consumption can not be achieved.

Controlled by the production cost and the influence of the product application environment, the MCU for the product does not consider an external high-precision oscillator. The MCU works by using an internal clock oscillator, and a clock source of the timer in the MCU comes from the internal oscillator. The current MCU has no function of calibrating the internal main clock of the chip during operation.

Disclosure of Invention

In view of the above-mentioned drawbacks of the prior art, it is an object of the present invention to provide a method for calibrating an internal clock of an electronic detonator chip, which solves at least one of the drawbacks of the prior art.

In order to achieve the above and other related objects, the present invention provides a method for calibrating an internal clock of an electronic detonator chip, wherein the electronic detonator is a slave, the slave is controlled by a master, the master includes a periodic wake-up module, the slave includes a timer, and the method includes:

acquiring a first time difference value between the timer and the host;

acquiring a second time difference value between the periodic awakening module and the host;

obtaining a third time difference value according to the first difference value and the second difference value;

and obtaining the real running time of the timer according to the accumulated running time of the timer and the third time difference value.

Optionally, the third time difference value is equal to the first time difference value plus the second time difference value.

Optionally, the real running time of the timer is equal to the accumulated running time of the timer plus the third time difference value.

Optionally, all slaves are grouped, and the timer clock of each group of slaves is calibrated respectively.

Optionally, the method further comprises:

the host sends a calibration broadcast command with an address range;

if the communication address of the slave computer is in the address range, the slave computer enters a clock calibration pulse acquisition process; and if the communication address of the slave is not in the address range, the slave enters a bus idle monitoring mode.

Optionally, the timer captures a pulse period of a signal sent by the host, so as to obtain the first time difference value.

Optionally, a fourth time difference value between the periodic wakeup module and the timer is obtained, and the second time difference value is obtained according to the fourth time difference value.

Optionally, the feature matrix convolution is performed on the pulse period of the signal captured by the timer.

As described above, the method for calibrating the internal clock of the electronic detonator chip of the present invention has the following beneficial effects:

according to the clock frequency in the MCU, microsecond level or even nanosecond level can be achieved. Because the hardware function of the MCU internal timer is used, the error of software processing is avoided. The delay precision between 250ms and 20000ms can realize the error of +/-0.2 percent, and the precision can be improved by 10 times compared with that before the calibration is not carried out.

The anti-interference capability is strong, and a group of pulse waveforms are used, and a stable calibration period is obtained after data are screened through a filtering algorithm.

The power consumption is low, the whole power requirement of the network is low after networking is carried out, a grouping mode is adopted for calibrating the whole network, and the condition that the power supply current is overlarge due to the fact that all modules work simultaneously is prevented. 400 MCU points can be calibrated on a 1000 m detonation bus simultaneously.

Drawings

Fig. 1 is a flowchart of a method for calibrating an internal clock of an electronic detonator chip according to an embodiment of the present invention.

Detailed Description

The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention. It is to be noted that the features in the following embodiments and examples may be combined with each other without conflict.

It should be noted that the drawings provided in the following embodiments are only for illustrating the basic idea of the present invention, and the components related to the present invention are only shown in the drawings rather than drawn according to the number, shape and size of the components in actual implementation, and the type, quantity and proportion of the components in actual implementation may be changed freely, and the layout of the components may be more complicated.

The frequency of the main MCU can be measured, the HCR of the main MCU is set to be 2M, Fhrc is the main clock frequency of the main MCU, and Fhlc is the low-speed clock of the main MCU and is used for periodic awakening; tcap1 is a measurement of the frequency of the timer capture master 2KhZ, with Fhrc being Tcap1 × 2 KHz. Tcap2 is a pulse value captured by the timer from the low speed clock inside the main MCU, Fhrc/Tcap2 ═ Fhlc, Fhlc ═ Tcap1 × 2KHz/Tcap1, and Fhrc and Fhlc are the measured real frequencies of the MCU internal clock.

The invention converts the frequency error into the delay error, and the HRC in the MCU is set to be 2M, but the error (2M + diff) exists actually. The clock of diff-Fhrc-2M, (2M + diff) inputs a given clock as a clock source, the count value of the timer is set to be Tcap1, the delay is Tcap 1/2M-a, and the actual delay relative to the host is Tcap1/Tcap 1-2 KHz-500 us-b. There is a time difference between a and b, which is caused by diff.

The actual delay is Tcap1/(2M + diff), and therefore, calibration is required.

As shown in fig. 1, in the method for calibrating the internal clock of the electronic detonator chip, the electronic detonator is a slave, the slave is controlled by a host, the host comprises a periodic wake-up module, the periodic wake-up module is arranged in an MCU chip of the host, and the periodic wake-up module has a periodic wake-up function, that is, periodically wakes up the MCU chip to change the working state thereof. The slave machine comprises a timer, and the timer is arranged in an MCU chip of the slave machine.

The master machine utilizes a high-precision clock (the clock precision error is less than 20ppm) of the master machine, outputs a PWM waveform with a fixed period through hardware, and the slave machine acquires the period of the PWM waveform through an input capturing channel of a timer of the slave machine, so that the deviation from the standard period is obtained. The calibration method comprises the following steps:

s11 obtaining a first time difference value between the timer and the host;

s12, acquiring a second time difference value between the periodic wake-up module and the host;

s13, obtaining a third time difference value according to the first difference value and the second difference value;

s14 obtaining a real operation time of the timer according to the accumulated operation time of the timer and the third time difference value.

In one embodiment, the third time difference value is equal to the first time difference value plus the second time difference value.

In one embodiment, the real running time of the timer is equal to the accumulated running time of the timer plus the third time difference value.

In one embodiment, all slaves are grouped, and the timer clocks of the slaves in each group are calibrated respectively. By grouping the slaves, the condition that the supply current is overlarge due to the fact that all modules work simultaneously is avoided, and 400 MCU points can be calibrated on a 1000-meter detonation bus simultaneously.

In an embodiment, the method further comprises:

the host sends a calibration broadcast command with an address range;

if the communication address of the slave computer is in the address range, the slave computer enters a clock calibration pulse acquisition process; and if the communication address of the slave is not in the address range, the slave enters a bus idle monitoring mode. Wherein the idle state is an ultra low power mode.

In an embodiment, the first time difference value is obtained by capturing a pulse period of a signal sent by the host through the timer.

In an embodiment, a fourth time difference value between the periodic wakeup module and the timer is obtained, and the second time difference value is obtained according to the fourth time difference value.

Specifically, the system clock may be reconfigured, pulling up the clock cycles of the MCU master and the timer. And configuring a periodic awakening function inside the MCU. And measuring the periodical awakening time of the MCU by using the timer to obtain the delay time of the periodical awakening time of the MCU relative to the timer.

In the present invention, the deviation of the timer from the master is obtained. The timer is used for measuring the deviation of the periodic awakening module, and the deviation can be converted into the deviation of the periodic awakening module relative to the host through the timer.

In one embodiment, the characteristic matrix convolution is performed on the pulse period of the signal captured by the timer.

In an embodiment, the slave that enters the calibration pulse acquisition process may configure an input clock frequency of an internal timer of the MCU, where the higher the input frequency, the higher the calibration accuracy, but the larger the power consumption. The interrupt function of input capture is configured, and the slave computer enters an idle mode which is a low power consumption mode which can be awakened by the capture interrupt.

The invention has the following advantages:

①, the calibration precision is high, microsecond or even nanosecond can be achieved according to the clock frequency in the MCU, because of using the hardware function of the timer in the MCU, the error in software processing is left aside, the delay precision between 250ms and 20000ms can realize the error of +/-0.2%, and the precision can be improved by 10 times compared with the precision before no calibration.

②, the anti-interference ability is strong, a group of pulse waveforms is used, and a stable calibration period is obtained after the data are screened by a filtering algorithm.

③, the power consumption is low, the whole power requirement of the network is low after networking, the existing communication protocol is utilized, the whole network is calibrated by adopting a grouping mode, the condition that the power supply current is overlarge due to the fact that all modules work simultaneously is prevented, and 400 MCU points can be calibrated on a 1000-meter detonating bus simultaneously.

It will be apparent to those skilled in the art that, for convenience and brevity of description, only the above-mentioned division of the functional units and modules is illustrated, and in practical applications, the above-mentioned function distribution may be performed by different functional units and modules according to needs, that is, the internal structure of the apparatus is divided into different functional units or modules to perform all or part of the above-mentioned functions. Each functional unit and module in the embodiments may be integrated in one processing unit, or each unit may exist alone physically, or two or more units are integrated in one unit, and the integrated unit may be implemented in a form of hardware, or in a form of software functional unit. In addition, specific names of the functional units and modules are only for convenience of distinguishing from each other, and are not used for limiting the protection scope of the present application. The specific working processes of the units and modules in the system may refer to the corresponding processes in the foregoing method embodiments, and are not described herein again.

In the above embodiments, the descriptions of the respective embodiments have respective emphasis, and reference may be made to the related descriptions of other embodiments for parts that are not described or illustrated in a certain embodiment.

Those of ordinary skill in the art will appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware or combinations of computer software and electronic hardware. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the implementation. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present invention.

In the embodiments provided in the present invention, it should be understood that the disclosed apparatus/terminal device and method may be implemented in other ways. For example, the above-described embodiments of the apparatus/terminal device are merely illustrative, and for example, the division of the modules or units is only one logical division, and there may be other divisions when actually implemented, for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, devices or units, and may be in an electrical, mechanical or other form.

The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.

In addition, functional units in the embodiments of the present invention may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit. The integrated unit can be realized in a form of hardware, and can also be realized in a form of a software functional unit.

The integrated modules/units, if implemented in the form of software functional units and sold or used as separate products, may be stored in a computer readable storage medium. Based on such understanding, all or part of the flow of the method according to the embodiments of the present invention may also be implemented by a computer program, which may be stored in a computer-readable storage medium, and when the computer program is executed by a processor, the steps of the method embodiments may be implemented. Wherein the computer program comprises computer program code, which may be in the form of source code, object code, an executable file or some intermediate form, etc. The computer readable medium may comprise any entity or device capable of carrying the computer program code, a recording medium, a U disk, a removable hard disk, a magnetic disk, an optical disk, a computer Memory, a Read-Only Memory (ROM), a Random Access Memory (RAM), an electrical carrier signal, a telecommunications signal, a software distribution medium, etc.

The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.