阅读说明：本技术 用于功率放大器的限流电路 (Current limiting circuit for power amplifier ) 是由 陈京华 柳智善 Y·K·G·候 孙彦杰 王新伟 张向东 于 2018-07-11 设计创作，主要内容包括：本公开的某些方面提供了对放大器(401)(诸如在射频(RF)前端的功率放大器)进行限流保护的方法和装置。一个示例限流电路通常包括耦合到电流源(404)的节点,耦合到该节点的多个电流吸收设备(406),耦合在该节点和多个电流吸收设备(406)中的至少一个电流吸收设备之间的一个或多个开关(408),以及偏置电路,该偏置电路具有耦合到该节点的输入和用于耦合到该放大器(401)的输入的输出。(Certain aspects of the present disclosure provide methods and apparatus for current limiting protection of an amplifier (401), such as a power amplifier in a Radio Frequency (RF) front end. One example current limiting circuit generally includes a node coupled to a current source (404), a plurality of current sinking devices (406) coupled to the node, one or more switches (408) coupled between the node and at least one of the plurality of current sinking devices (406), and a biasing circuit having an input coupled to the node and an output for coupling to an input of the amplifier (401).)

1. A current limiting circuit for an amplifier, comprising:

a node coupled to a current source;

a plurality of current sinking devices coupled to the node;

one or more switches coupled between the node and at least one of the plurality of current sinking devices; and

a bias circuit having an input coupled to the node and an output for coupling to an input of the amplifier.

2. The circuit of claim 1, wherein the bias circuit comprises a buffer implemented as an emitter follower.

3. The circuit of claim 2, wherein the emitter follower comprises a transistor having a base coupled to the node, an emitter for coupling to the input of the amplifier, and a collector for coupling to a power rail for the circuit.

4. The circuit of claim 3, wherein the transistor comprises a Heterojunction Bipolar Transistor (HBT).

5. The circuit of claim 1, wherein at least one of the plurality of current sinking devices comprises one or more diode devices.

6. The circuit of claim 5, wherein the one or more diode devices comprise diode-connected transistors.

7. The circuit of claim 6, wherein the diode-connected transistor comprises a Heterojunction Bipolar Transistor (HBT) having a collector and a base coupled to the collector.

8. The circuit of claim 1, wherein at least one of the plurality of current sinking devices comprises two diode devices connected in series.

9. The circuit of claim 1, wherein at least one of the plurality of current sinking devices is directly connected to the node.

10. The circuit of claim 1, wherein the number of the one or more switches configured to be closed depends on an output current from the current source.

11. The circuit of claim 1, further comprising a resistive element having a first terminal coupled to the output of the bias circuit and a second terminal for coupling to the input of the amplifier.

12. The circuit of claim 1, wherein the current source is configured based on temperature.

13. The circuit of claim 1, wherein the current source is configured to provide a substantially constant current.

14. The circuit of claim 1, wherein the amplifier comprises a power amplifier configured to output a radio frequency signal.

15. A method of current limiting an amplifier, comprising:

supplying a supply current to a node, the node being coupled to a plurality of current sinking devices;

providing a bias current to an input of the amplifier via a bias circuit having an input coupled to the node and an output coupled to the input of the amplifier; and

selectively closing one or more switches coupled between the node and at least one of the plurality of current sinking devices to regulate a reference current derived from the supply current, the reference current limiting an input current for the bias circuit to no greater than the reference current, the input current for the bias circuit based on the bias current.

16. The method of claim 15, wherein the amplifier comprises a transistor, and wherein the bias current is a base current for the transistor and the bias current is proportional to a collector current for the transistor.

17. The method of claim 15, wherein:

the bias circuit includes a buffer implemented as an emitter follower;

the emitter follower comprises a transistor having a base coupled to the node, an emitter coupled to the input of the amplifier, and a collector for coupling to a power supply rail;

the input current for the bias circuit is a base current for the transistor; and

the bias current is an emitter current for the transistor, and the bias current is proportional to the base current according to β of the transistor.

18. The method of claim 17, wherein the transistor comprises a Heterojunction Bipolar Transistor (HBT).

19. The method of claim 15, wherein at least one current sinking device of the plurality of current sinking devices comprises one or more diode devices.

20. The method of claim 19, wherein the one or more diode devices comprise diode-connected transistors.

21. The method of claim 20, wherein the diode-connected transistor comprises a Heterojunction Bipolar Transistor (HBT) having a collector and a base coupled to the collector.

22. The method of claim 15, wherein at least one of the plurality of current sinking devices is directly connected to the node.

23. The method of claim 15, wherein the selectively closing comprises selectively closing a number of switches of the one or more switches based on the supply current supplied to the node.

24. The method of claim 15, wherein the selectively closing comprises selectively closing a number of switches of the one or more switches to adjust linearity of the amplifier.

25. The method of claim 15, wherein the supplying comprises configuring the supply current to establish a protection condition for the amplifier.

26. An apparatus, comprising:

means for amplifying the radio frequency signal;

means for supplying a substantially constant current;

means for adjustably sinking current supplied by the means for supplying the substantially constant current; and

means for biasing the means for amplifying, the means for biasing coupled between the means for adjustably sinking current and the means for amplifying.

27. The apparatus of claim 26, wherein the means for adjustably sinking a current comprises a plurality of means for selectively sinking the current.

28. The apparatus of claim 27, wherein at least one of the plurality of means for selectively sinking the current comprises a switch coupling a means for supplying the substantially constant current to a current sinking device.

29. The apparatus of claim 26, wherein the means for biasing comprises an β helper circuit.

30. The apparatus of claim 26, wherein the means for amplifying comprises a gallium arsenide (GaAs) power amplifier.

Technical Field

Certain aspects of the present disclosure generally relate to electronic circuits, and more particularly, to current limiting circuits.

Background

Wireless communication networks are widely deployed to provide various communication services such as telephony, video, data, messaging, broadcasting, and so on. Such networks are typically multiple-access networks that support communication for multiple users by sharing the available network resources. For example, one network may be a 3G (third generation mobile telephony standards and technologies) system, which may provide network services via any of a variety of 3G Radio Access Technologies (RATs), including EVDO (evolution data optimized), 1xRTT (1 x radio transmission technology, or 1x for short), W-CDMA (wideband code division multiple access), UMTS-TDD (universal mobile telecommunications system-time division multiplexing), HSPA (high speed packet access), GPRS (general packet) radio service), or EDGE (enhanced data rates for global evolution). The 3G network is a wide area cellular telephone network that has evolved to merge high speed internet access and video telephony in addition to voice calls. Furthermore, 3G networks may be more sophisticated and provide greater coverage than other network systems. Such multiple-access networks may also include Code Division Multiple Access (CDMA) systems, Time Division Multiple Access (TDMA) systems, Frequency Division Multiple Access (FDMA) systems, Orthogonal Frequency Division Multiple Access (OFDMA) systems, single carrier FDMA (SC-FDMA) networks, 3 rd generation partnership project (3GPP) Long Term Evolution (LTE) networks, and long term evolution advanced (LTE-a) networks.

A wireless communication network may include a plurality of base stations capable of supporting communication for a plurality of mobile stations. A Mobile Station (MS) may communicate with a Base Station (BS) via a downlink and an uplink. The downlink (or forward link) refers to the communication link from the base stations to the mobile stations, and the uplink (or reverse link) refers to the base stations from the mobile stations to the communication link. The base station may transmit data and control information to the mobile station on the downlink and/or may receive data and control information from the mobile station on the uplink. The base station and/or mobile station may include a radio frequency front end having a power amplifier coupled to one or more antennas for transmission.

Disclosure of Invention

Certain aspects of the present disclosure generally relate to current limiting circuits, such as circuits for current limiting protection of amplifiers (e.g., power amplifiers in radio frequency front ends of wireless devices).

Certain aspects of the present disclosure provide a current limiting circuit for an amplifier. The circuit generally includes a node coupled to a current source, a plurality of current sinking devices coupled to the node, one or more switches coupled between the node and at least one of the plurality of current sinking devices, and a bias circuit having an input coupled to the node and an output for coupling to an input of the amplifier.

Certain aspects of the present disclosure provide a method of current limiting an amplifier. The method generally includes providing a supply current to a node, the node coupled to a plurality of current sinking devices; providing a bias current to an input of the amplifier via a bias circuit, an input of the bias circuit coupled to the node and an output coupled to an input of the amplifier; and selectively closing one or more switches coupled between the node and at least one of the plurality of current sinking devices to regulate a reference current derived from the supply current, the reference current limiting an input current of the bias circuit to no greater than a reference current, the input current for the bias circuit based on the bias current.

Certain aspects of the present disclosure provide an apparatus. The apparatus generally comprises: means for amplifying the radio frequency signal, means for providing a substantially constant current, means for adjustably sinking current being provided through the means for supplying said substantially constant current; and means for biasing the means for amplifying, the means for biasing coupled between the means for adjustably sinking current and the means for amplifying.

Drawings

So that the manner in which the above recited features of the present disclosure can be understood in detail, a more particular description of the above briefly summarized above may be had by reference to various aspects, some of which are illustrated in the appended drawings. It is to be noted, however, that the appended drawings illustrate only some general aspects of this disclosure and are therefore not to be considered limiting of its scope, for the description may admit to other equally effective aspects.

Fig. 1 is a diagram of an example of a wireless communication network in accordance with certain aspects of the present disclosure.

Fig. 2 is a block diagram of an example Access Point (AP) and an example user terminal in accordance with certain aspects of the present disclosure.

Fig. 3 is a block diagram of an example transceiver front end in accordance with certain aspects of the present disclosure.

Fig. 4 is a circuit diagram of an example current limiting protection circuit for a power amplifier, according to certain aspects of the present disclosure.

Fig. 5 is an example graph of output power versus input power for a power amplifier comparing protection circuit enablement and disablement, according to certain aspects of the present disclosure.

Fig. 6 is an example graph of gain versus output power with different numbers of dual-stacked diodes enabled, according to certain aspects of the present disclosure.

Fig. 7 is a flow diagram of example operations for current limiting an amplifier, according to certain aspects of the present disclosure.

Detailed Description

Various aspects of the disclosure will be described more fully hereinafter with reference to the accompanying drawings. This disclosure may, however, be embodied in many different forms and should not be construed as limited to any specific structure or function presented throughout this disclosure. Rather, these aspects are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art. Based on the teachings herein one skilled in the art should appreciate that the scope of the present disclosure is intended to cover any aspect of the present disclosure disclosed herein, whether implemented independently or in combination with any other aspect of the present disclosure. For example, an apparatus may be implemented or a method may be practiced using any number of the aspects set forth herein. Additionally, the scope of the present disclosure is intended to cover such an apparatus or method which is practiced using other structure, functionality, or structure and functionality in addition to or other than the various aspects of the present disclosure set forth herein. It should be understood that any aspect of the disclosure disclosed herein may be embodied by one or more elements of a claim.

The word "exemplary" is used herein to mean "serving as an example, instance, or illustration. Any aspect described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other aspects.

As used herein, the term "connected," in various tenses of the verb "connect," may mean that element a is directly connected to element B or that other elements may be connected between elements a and B (i.e., element a is indirectly connected with element B). In the case of electrical components, the term "and.. connect" may also be used herein to mean electrically connecting elements a and B (and any components electrically connected therebetween) using wires, traces, or other electrically conductive materials.

The techniques described herein may be used in conjunction with various wireless technologies such as Code Division Multiple Access (CDMA), Orthogonal Frequency Division Multiplexing (OFDM), Time Division Multiple Access (TDMA), Space Division Multiple Access (SDMA), single carrier frequency division multiple access (SC-FDMA), time division synchronous code division multiple access (TD-SCDMA), and so on. Multiple user terminals can simultaneously transmit/receive data via different (1) orthogonal code channels for CDMA, (2) time slots for TDMA, or (3) subbands for OFDM. A CDMA system may implement IS-2000, IS-95, IS-856, wideband CDMA (W-CDMA), or some other standard. The OFDM system may implement Institute of Electrical and Electronics Engineers (IEEE)802.11, IEEE802.16, Long Term Evolution (LTE) (e.g., in TDD and/or FDD modes), or some other standard (e.g., 5G). A TDMA system may implement the global system for mobile communications (GSM) or some other standard. In some embodiments, the techniques described herein may be used in conjunction with a Wireless Local Area Network (WLAN), for example, using a WiFi standard such as one of the IEEE802.11 standards. These various standards are known in the art.

Example of Wireless System

Fig. 1 illustrates a wireless communication system 100 having an access point 110 and a user terminal 120 in which aspects of the disclosure may be practiced. For simplicity, only one access point 110 is shown in fig. 1. An Access Point (AP) is generally a fixed station that communicates with user terminals and may also be referred to as a Base Station (BS), an evolved node b (enb), or some other terminology. A User Terminal (UT) may be fixed or mobile and may also be referred to as a Mobile Station (MS), an access terminal, a User Equipment (UE), a Station (STA), a client, a wireless device, or some other terminology. The user terminal may be a wireless device such as a cellular telephone, a Personal Digital Assistant (PDA), a handheld device, a wireless modem, a laptop computer, a tablet computer, a personal computer, etc.

The access point 110 may communicate with one or more user terminals 120 at any given moment on the downlink and uplink. The downlink (i.e., forward link) is the communication link from the access points to the user terminals, and the uplink (i.e., reverse link) is the communication link from the user terminals to the access points. A user terminal may also communicate peer-to-peer with another user terminal. A system controller 130 couples to and provides coordination and control for the access points.

System 100 may employ multiple transmit antennas and multiple receive antennas for data transmission on the downlink and uplink. For example, the access point 110 may be equipped with a number N_apTo achieve transmit diversity for downlink transmissions and/or receive diversity for uplink transmissions. Set N of selected user terminals 120_uA downlink transmission may be received and an uplink transmission may be transmitted. Each selected user terminal transmits user-specific data to and/or receives user-specific data from the access point. In general, each selected user terminal may be equipped with one or more antennas (i.e., N)_utNot less than 1). The selected user terminal N_uMay have the same or different numbers of antennas.

Wireless system 100 may be a Time Division Duplex (TDD) system or a Frequency Division Duplex (FDD) system. For a TDD system, the downlink and uplink share the same frequency band. For FDD systems, the downlink and uplink use different frequency bands. System 100 may also utilize a single carrier or multiple carriers for transmission. Each user terminal 120 may be equipped with a single antenna (e.g., to reduce cost) or multiple antennas (e.g., additional cost may be provided).

According to certain aspects of the present disclosure, the access point 110 and/or the user terminal 120 may include a current limiting circuit coupled to a power amplifier.

Fig. 2 shows a block diagram of an access point 110 and two user terminals 120m and 120x in a wireless system 100. The access point 110 is equipped with N_apAnd antennas 224a through 224 ap. User terminal 120m is equipped with N_ut,mAntennas 252ma through 252mu, and user terminal 120x is equipped with N_ut,xAnd antennas 252xa through 252 xu. The access point 110 is a transmitting entity for the downlink and for the uplinkThe receiving entity of (1). Each user terminal 120 is a transmitting entity for the uplink and a receiving entity for the downlink. As used herein, a "transmitting entity" is an independently operated device or apparatus capable of transmitting data via a frequency channel, and a "receiving entity" is an independently operated device or apparatus capable of receiving data via a frequency channel. In the following description, the subscript "dn" denotes the downlink, the subscript "up" denotes the uplink, N is chosen_upThe user terminals transmit simultaneously on the uplink, N is selected_dnWith simultaneous transmission of individual user terminals on the downlink, N_upMay or may not be equal to N_dnAnd N is_upAnd N_dnMay be a static value or may be changed for each scheduling interval. Beam steering or other spatial processing techniques may be used at the access point and the user terminal.

On the uplink, at each user terminal 120 selected for uplink transmission, a TX data processor 288 receives traffic data from a data source 286 and control data from a controller 280. TX data processor 288 processes (e.g., encodes, interleaves, and modulates) traffic data { d based on a coding and modulation scheme associated with a rate selected for the user terminal_upAnd is N_ut,mOne of the antennas provides a stream of data symbols s_up}. A transceiver front end (TX/RX)254 (also referred to as a Radio Frequency Front End (RFFE)) receives and processes (e.g., converts to analog, amplifies, filters, and frequency upconverts) the respective symbol streams to generate an uplink signal. The transceiver front-end 254 may also route uplink signals to antennas for transmit diversity via, for example, an RF switch. The controller 280 may control routing in the transceiver front end 254. A memory 282 may store data and program codes for the user terminal 120 and may be connected with the controller 280.

The number of dispatches is N_upFor simultaneous transmission on the uplink. Each of these user terminals transmits their set of processed symbol streams on the uplink to the access point.

At the access point 110, N_apA plurality of antennas 224a to 224ap for receiving signals fromWith N_upAn uplink signal transmitted on the uplink by each user terminal. Signals received from multiple antennas 224 may be combined to enhance receive diversity. The access point's transceiver front end 222 also performs processing complementary to that performed by the user terminal's transceiver front end 254 and provides a recovered uplink data symbol stream. The recovered uplink data symbol stream is an estimated data symbol stream transmitted by the user terminal. The RX data processor 242 processes (e.g., demodulates, deinterleaves, and decodes) the recovered uplink data symbol stream in accordance with the rate used for the stream to obtain decoded data. The decoded data for each user terminal may be provided to a data sink 244 for storage and/or to controller 230 for further processing.

According to certain aspects of the present disclosure, the transceiver front end (TX/RX)222 of the access point 110 and/or the transceiver front end 254 of the user terminal 120 may include current limiting circuitry coupled to a power amplifier.

On the downlink, at access point 110, a TX data processor 210 receives N from a data source 208_dnService data for a subscriber terminal, N_dnThe user terminals are scheduled for downlink transmission, receive control data from controller 230, and possibly other data from scheduler 234. Various types of data may be transmitted on different transmit channels. TX data processor 210 processes (e.g., encodes, interleaves, and modulates) the traffic data for each user terminal based on a rate selected for that user terminal. TX data processor 210 may be N_dnOne or more of the user terminals provide a downlink data symbol stream to be transmitted by N_apOne of the antennas transmits. Transceiver front end 222 receives and processes (e.g., converts to analog, amplifies, filters, and frequency upconverts) the symbol stream to generate a downlink signal. Transceiver front-end 222 may also route downlink signals to N via, for example, an RF switch_apOne or more of the antennas for transmit diversity. The controller 230 may control routing in the transceiver front end 222. A memory 232 may store data and program codes for access point 110 and may be coupled to controller 230.

At each user terminal 120, N_ut,mAn antenna 252 receives downlink signals from access point 110. For receive diversity at the user terminal 120, the transceiver front end 254 may select a signal received from one of the antennas 252 for processing. Signals received from multiple antennas 252 may be combined to enhance receive diversity. The user terminal's transceiver front end 254 also performs processing complementary to that performed by the access point's transceiver front end 222 and provides a recovered downlink data symbol stream. An RX data processor 270 processes (e.g., demodulates, deinterleaves, and decodes) the recovered downlink data symbol stream to obtain decoded data for the user terminal. The decoded data for the user terminal may be provided to a data sink 272 for storage and/or to a controller 280 for further processing.

Those skilled in the art will recognize that the techniques described herein may generally be applied in systems utilizing any type of multiple access scheme, such as TDMA, SDMA, Orthogonal Frequency Division Multiple Access (OFDMA), CDMA, SC-FDMA, TD-SCDMA, and combinations thereof.

Fig. 3 is a block diagram of an example transceiver front end 300 (such as transceiver front ends 222, 254 in fig. 2) in which aspects of the present disclosure may be practiced. The transceiver front end 300 includes a Transmit (TX) path 302 (also referred to as a transmit chain) for transmitting signals via one or more antennas, and a Receive (RX) path 304 (also referred to as a receive chain) for receiving signals via the antennas. When TX path 302 and RX path 304 share antenna 303, the paths may be connected with the antenna via interface 306, which may include any of a variety of suitable RF devices (such as duplexers, switches, diplexers, etc.).

Receiving in-phase (I) or quadrature (Q) baseband analog signals from digital-to-analog converter (DAC)308, TX path 302 may include a baseband filter (BBF)310, a mixer 312, a Driver Amplifier (DA)314, and a Power Amplifier (PA) 316. BBF310, mixer 312, and DA 314 may be contained in a Radio Frequency Integrated Circuit (RFIC), while PA 316 may be located external to the Radio Frequency Integrated Circuit (RFIC). The BBF310 filters the baseband signal received from the DAC 308, and the mixer 312 mixes the filtered baseband signal with a signal of a transmit Local Oscillator (LO) to convert the baseband signal of interest to a different frequency (e.g., up-convert from baseband to RF). The frequency conversion process generates sum and difference frequencies of the LO frequency and the frequency of the signal of interest. The sum and difference frequencies are referred to as beat frequencies. The beat frequency is typically in the RF range so that the signal output by the mixer 312 is typically an RF signal, which may be amplified by a DA 314 and/or a PA 316 before being transmitted through the antenna 303.

In certain aspects, a current limiting circuit may be connected to the PA 316. Examples of such current limiting circuits are described below.

The RX path 304 includes a Low Noise Amplifier (LNA)322, a mixer 324, and a baseband filter (BBF) 326. LNA322, mixer 324, and BBF 326 may be included in a Radio Frequency Integrated Circuit (RFIC), which may be the same or different from the RFIC that includes the TX path components. The RF signal received via antenna 303 may be amplified by LNA322 and mixed with a receive Local Oscillator (LO) signal by mixer 324 to convert the RF signal of interest to a different baseband frequency (i.e., down-convert). The baseband signal output by the mixer 324 may be filtered by a BBF 326 before being converted to a digital signal I or Q for digital signal processing by an analog-to-digital converter (ADC) 328.

Contemporary systems may employ a frequency synthesizer with a Voltage Controlled Oscillator (VCO) to generate a stable, tunable LO with a particular tuning range. Thus, the transmit LO frequency may be generated by a TX frequency synthesizer 318, which TX frequency synthesizer 318 may be buffered or amplified by an amplifier 320 before mixing with the baseband signal in mixer 312. Similarly, the receive LO frequency may be generated by an RX frequency synthesizer 330, which may be buffered or amplified by an amplifier 332 before mixing with the RF signal in mixer 324. For certain aspects, the frequency synthesizer may be shared by TX and RX and/or by multiple TX chains and/or RX chains.

Examples of current limiters for power amplifiers

Design specifications such as ruggedness for earpiece Power Amplifiers (PAs) are very stringent, as it can be expected that a PA (e.g., PA 316) can survive and operate at high load mismatch (e.g., 10: 1 Voltage Standing Wave Ratio (VSWR), extreme temperatures, and high supply voltages (e.g., 4.5V), while delivering high output power (e.g., up to 36dBm or about 4 watts). Such extreme conditions may result in high voltage and/or current swings at the collector of the PA power transistor and may damage the circuitry. To improve the durability of the PA, certain aspects of the present invention provide techniques and apparatus for protecting the PA with a current limiting protection circuit that limits the maximum current drawn by the PA power transistor (also referred to as the "power cell transistor"). The protection circuit can improve the durability and stability of the PA.

Fig. 4 is a circuit diagram 400 of an example power amplifier 401 and supporting circuitry including an example current limiting protection circuit 402 for the power amplifier, in accordance with certain aspects of the present disclosure. The power amplifier 401 may include a transistor M1 (power cell transistor). As shown in fig. 4, the collector of transistor M1 may be coupled to the power rail (Vcc) via an inductive element (e.g., inductor L1). The base of transistor M1 may be coupled to the input voltage node (Vin) via an AC coupling capacitor C1, and the emitter of transistor M1 may be coupled to a reference potential node (e.g., electrical ground). For certain aspects, the transistor M1 may be implemented by a Heterojunction Bipolar Transistor (HBT) and/or be composed of gallium arsenide (GaAs). The output of the power amplifier 401 (e.g., the collector of the transistor M1) may be coupled to an output voltage node (Vout) via an output impedance matching network (OMN) 403.

The protection circuit 402 may be coupled to or include a current source 404 configured to provide at least one reference current (I) to a bias circuit 410 for the power amplifier 401_ref). The current source 404 may supply a current I_ref', slave current I_ref' providing a reference current (I)_ref). For certain aspects, current I_ref' is provided by a Complementary Metal Oxide Semiconductor (CMOS) controller. In this case, the current source 404 may be considered part of the CMOS controller. In other aspects, the current source 404 is a separate circuit that may be coupled to a node of the CMOS controller. A CMOS controller (or other logic controller) may be used to control the rf front end (e.g., of fig. 3)Transceiver front-end 300), such as the state of various switches to select different operating modes (e.g., switches in interface 306, frequency synthesizers 318, 330, amplifiers 316, 322, and/or BBFs 310, 326). In some cases, the CMOS controller may be located in the vicinity of the power amplifier 401. In some embodiments, the protection circuit 402, the bias circuit 410, and the power amplifier 401 are implemented together in one module. In some such embodiments, the controller (e.g., CMOS controller) is implemented separately from the module. In other embodiments, one or more of the bias circuit 410 and the protection circuit 402 are implemented separately from the power amplifier 401, e.g., as separate components or in separate modules. In one such embodiment, the protection circuit 402 is implemented with a controller.

In certain aspects and/or modes, the current I for the protection circuit 402_ref' may be configured to be substantially constant (e.g., with a suitable temperature and/or time drift, such as less than 5% over an operating temperature range). In some configurations, for example, with I_refSuch constant operation simplifies the design and/or operation of the CMOS controller compared to implementations where' programmably changes to achieve linearity of the power amplifier 401.

Further, as shown in the example of fig. 4, the protection circuit 402 includes: (1) an array of current sinking devices 406, such as diode devices, and (2) an optional switch array 408 coupled between the current source 404 and the array of current sinking devices 406 (to enable different numbers of stacked diode devices). There may be n switches, labeled "S1" through "Sn," in the optional switch array 408, where n is any positive integer (including 1). Nominal reference current I of current source 404_ref' may be configured to provide a fixed reference current, although I_ref' may depend on temperature. In such an aspect, the current source 404 may be configured to provide a substantially constant current I for each of a plurality of different temperature and/or mode settings_ref'. The diode device may be implemented by any of a variety of suitable components having a p-n junction, such as a diode or a diode-connected transistor (e.g., a diode-connected transistor)A dual stacked diode connected transistor M3-M8, as shown in fig. 4). The diode device may be implemented using the same or different semiconductor technology (e.g., GaAs HBT) as power cell transistor M1 of power amplifier 401. For certain aspects, more or less than two diode devices may be connected in series in each of a plurality of stacks of an array of current sinking devices 406 (described below). Although each current sinking device is shown in fig. 4 as a pair of series-connected diode-connected transistors (e.g., with the same current sinking device in each stack), one of ordinary skill in the art will appreciate that one or more current sinking devices may alternatively comprise different elements. For certain aspects, the switch array 408 may be located on the CMOS controller die. Other examples of current sinking devices include resistors, current source circuits acting as current sinks, transistors, and the like.

The operation of the current limiting protection circuit 402 is described below. Collector current (I) when power amplifier 401 is driven by input Radio Frequency (RF) power received at Vin_cc) And the base current of the power cell (transistor M1) increases due to its self-rectification. The base current of transistor M1 may be represented as I_cc/β_M1In which I_ccIs the collector current and β_M1Is a factor of β of transistor M1 the base current of transistor M1 is provided by a bias circuit 410, the bias circuit 410 being implemented in fig. 4 as a buffer with an emitter follower topology, which includes transistor M2 (e.g., HBT), the base current of transistor M2 may be approximated as I_cc/β_M1/β_M2The collector of transistor M2 may be coupled to a power rail (e.g., Vbatt), the emitter of transistor M2 may be coupled to the base of transistor M1 via an impedance (e.g., including a resistive element, such as resistor R1), and the base of transistor M2 may be coupled to node 412, node 412 representing the output of protection circuit 402 and the input of bias circuit 410. For certain aspects, a low pass filter or shunt capacitive element (e.g., capacitor C2) may be disposed between the node 412 and the base of the transistor M2 to filter high frequency signals (e.g., transients) from the output of the protection circuit 402.

The protection circuit 402 (e.g., via a CMOS controller) may be based on a fixed reference current I_ref' operate, and I_refCan be selected from_ref' providing. I may be connected by a stack of diode devices (e.g., diode-connected transistors M3 and M4)_refSplitting into a base current and a forward current I for a transistor M2_diode，0。I_refMaximum value of (1) is_refThe value of' is limited. Because of the limited I_refThe maximum base current provided to node 412, transistor M2, is I_refThe base current of transistor M1 is limited, therefore, by I_refIn some embodiments, certain such aspects may be referred to as β helper and the current may be appropriately adjusted for operation of β helper/power cell as described herein_cc/β_M1/β_M2>I_ref。

I_ref' may be set to satisfy certain conditions. For example, I can be_ref' is arranged to provide sufficient base current to meet the maximum power specification at nominal operating conditions. I is_ref' may also be set to ensure that power cell transistor M1 does not exceed the maximum current and/or voltage under extreme conditions (e.g., high temperature).

Fig. 5 is an example plot 500 of output power versus input power for a power amplifier (e.g., power amplifier 401), comparing the same circuit with and without implementing a protection technique as described above for testing purposes, curve 502 represents no protection implemented and curve 504 represents protection implemented, curve 504 illustrates the case where the maximum power is limited (e.g., current limited) and power begins to decrease when the power amplifier is overdriven, the behavior of such overdriven illustrated by curve 504 may be that β of the power cell transistor varies with temperature as the transistor warms up with increasing power.

Returning to FIG. 4, because of the reference current (I)_ref) Can be designed to be in a nominal stripThe member delivers sufficient power and, for certain aspects, may provide additional degrees of freedom to attempt to adjust the quiescent current (I)_q) To improve the linearity, gain and/or efficiency of the power amplifier 401. For certain aspects, the adjustment I may be provided by a switch array 408 between the current source 404 and at least some of the diode device stacks (e.g., those diode device stacks other than transistors M3 and M4 having diode connections)_q(＝I_cc/β_M1) The ability of the cell to perform. By connecting more diode device stacks (e.g., dual-stacked diodes) via switches (S1-Sn), forward current (I) through the various enabled stacks_diode,1To I_diode,n) From I_refThe more current is absorbed in. Thus, less I_refIs provided to current branch 411, less base current is provided to transistor M2, and therefore, less current is provided to the base of the power cell (transistor M1), which determines the DC bias condition. For a given I_ref', the switch array 408 can determine the DC offset because of I_refThe value of' can be set based on design specifications. In other words, for a given I_ref', a specific number of switches in the array can be closed; if I_ref' changed, a different number of switches may be closed. Thus, regulating I_ref' and the ability to control the number of diode device stacks enabled may provide multiple degrees of freedom for protection and linearity considerations. For example, I can be_ref' set up e.g. for protection in a certain mode or under certain conditions, however, the number of diode device stacks enabled may be used to set up I_qAnd controls the linearity of the power amplifier 401.

Fig. 6 is an example graph 600 of gain versus output power with different numbers of diode device stacks (e.g., dual stack diodes) enabled, in accordance with certain aspects of the present disclosure. For at least 10 different diode device stacks, as shown by trend line 602 in graph 600, as the number of enabled diode device stacks increases (e.g., as the number of closed switches in switch array 408 increases), the gain decreases.

Advantageously, the current limiting circuit may improve durability and stability under various power (e.g., different Vcc) and Voltage Standing Wave Ratio (VSWR) conditions.

Fig. 7 is a flow diagram of example operations 700 for current limiting an amplifier (e.g., power amplifier 401) in accordance with certain aspects of the present disclosure. Operation 700 may be performed by a current limiting circuit, such as current limiting protection circuit 402 of fig. 4, for example, in combination with a biasing circuit, such as biasing circuit 410 of fig. 4.

May be controlled by supplying a current (e.g., I) to a node (e.g., node 412)_ref') begins operation 700 at block 702. The node may be coupled to a plurality of current sinking devices (e.g., an array of current sinking devices 406). At block 704, a bias current (I) may be applied via a bias circuit (e.g., bias circuit 410)_q) To an input of an amplifier, the bias circuit having an input coupled to the node and an output coupled to the input of the amplifier. At block 706, the circuit may selectively close one or more switches (e.g., switches S1-Sn) coupled between the node and at least one of the plurality of current sinking devices to adjust a reference current (e.g., I) derived from the supply current_ref) For example, because β at M2 draws an amount of current from the protection circuit 402 as an input current based on the bias current.

According to certain aspects, the amplifier includes a transistor. In this case, the bias current may be the base current for the transistor and proportional to the collector current for the transistor. For certain aspects, the transistor comprises an HBT.

The bias circuit includes a buffer implemented as an emitter follower in this case, the emitter follower includes a transistor having a base coupled to a node, an emitter coupled to an input of the amplifier, and a collector for coupling to a power supply rail.

According to certain aspects, at least one of the plurality of current sinking devices comprises one or more diode devices. The one or more diode devices include diode-connected transistors. For certain aspects, the diode-connected transistor is an HBT having a collector and a base coupled to the collector.

According to certain aspects, at least one current sinking device of the plurality of current sinking devices comprises two diode devices connected in series.

According to certain aspects, at least one current sinking device of the plurality of current sinking devices is directly connected to a node (e.g., a diode device stack including M3 and M4).

According to certain aspects, the selectively closing at block 706 includes: based on the supply current supplied to the node (e.g., the output current I from the current source 404)_ref') selectively close a number of switches of the one or more switches.

According to certain aspects, the selective closing at block 706 entails selectively closing a number of switches of the one or more switches to adjust the linearity of the amplifier.

According to certain aspects, the source at block 702 includes programming a current source (e.g., current source 404) to set a supply current. For certain aspects, the current source is configured to provide a substantially constant current.

According to certain aspects, the amplifier includes a power amplifier configured to output a radio frequency signal.

The various operations or methods described above may be performed by any suitable means capable of performing the corresponding functions. The components may include various hardware and/or software components and/or modules, including but not limited to circuits, Application Specific Integrated Circuits (ASICs), or processors. Generally, where operations are illustrated in the figures, those operations may have corresponding relative component-plus-function elements with similar numbering.

For example, the means for amplifying the radio frequency signal may include a power amplifier, such as power amplifier 316 depicted in FIG. 3 or power amplifier 401 shown in FIG. 4, the means for providing the substantially constant current may include a current source, such as current source 404 depicted in FIG. 4, the means for adjustably sinking the current may include a plurality of means for selectively sinking the current, such as an array of current sinking devices 406 coupled to switch array 408, as shown in FIG. 4, the means for biasing may include a biasing circuit, such as biasing circuit 410 or β helper circuits shown in FIG. 4.

As used herein, the term "determining" encompasses a wide variety of actions. For example, "determining" can include calculating, computing, processing, deriving, investigating, looking up (e.g., looking up in a table, a database or another data structure), ascertaining and the like. Also, "determining" may include receiving (e.g., receiving information), accessing (e.g., accessing data in a memory), and the like. Also, "determining" may include resolving, choosing, selecting, establishing, and the like.

As used herein, a phrase referring to "at least one of" a series of items refers to any combination of those items, including a single member. By way of example, "at least one of a, b, or c" is meant to encompass: a. b, c, a-b, a-c, b-c, and a-b-c, as well as any combination of multiple identical elements (e.g., a-a-a, a-a-b, a-a-c, a-b-b, a-c-c, b-b-b, b-b-c, c-c, and c-c-c, or any other order of a, b, and c).

The methods disclosed herein comprise one or more steps or actions for achieving the described method. The method steps and/or actions may be interchanged with one another without departing from the scope of the claims. In other words, unless a specific order of steps or actions is specified, the order and/or use of specific steps and/or actions may be modified without departing from the scope of the claims.

It is to be understood that the claims are not limited to the precise configuration and components shown above. Various modifications, changes and variations may be made in the arrangement, operation and details of the methods and apparatus described above without departing from the scope of the claims.