阅读说明：本技术 一种多通道任意波形发生器校正方法及系统 (Multichannel arbitrary waveform generator correction method and system ) 是由 张孝飞 赵素梅 刘强 于 2019-11-05 设计创作，主要内容包括：本发明涉及信号发生器领域,具体提供了一种多通道任意波形发生器校正方法及系统。与现有技术相比,本发明的一种多通道任意波形发生器校正方法,由上位机通过PCIE接口发送多通道波形数据和指令,多通道波形数据根据指令的需要进行各个通道延时、幅度和偏置的调节,待调节的各个通道达到理想的状态下,调节各个通道配置参数作为校正数据储存到外挂的Flash中,Flash储存的校正数据用于在下次使用时掉电不丢失。在信号发生器测试中具有良好的推广价值。(The invention relates to the field of signal generators, and particularly provides a method and a system for correcting a multichannel arbitrary waveform generator. Compared with the prior art, the multichannel random waveform generator correction method has the advantages that the upper computer sends multichannel waveform data and instructions through the PCIE interface, the multichannel waveform data carry out adjustment on time delay, amplitude and bias of each channel according to the requirements of the instructions, under the condition that each channel to be adjusted reaches an ideal state, configuration parameters of each channel are adjusted to serve as correction data to be stored in the plug-in Flash, and the correction data stored in the Flash is used for preventing power failure loss when the Flash is used next time. The method has good popularization value in signal generator testing.)

1. A correction method for a multichannel arbitrary waveform generator is characterized in that an upper computer sends multichannel waveform data and instructions through a PCIE interface, the multichannel waveform data carry out adjustment on delay, amplitude and bias of each channel according to the requirements of the instructions, each channel to be adjusted is adjusted to serve as correction data to be stored in a plug-in Flash when each channel to be adjusted reaches an ideal state, and the correction data stored in the Flash is used for being not lost when power is lost in next use.

2. The method of calibrating a multichannel arbitrary waveform generator according to claim 1, wherein the upper computer sends the waveform data to the XDMA IP core of the FPGA for data and command processing via the PCIE interface.

3. The multi-pass through arbitrary waveform generator correction method as claimed in claim 2, wherein the waveform data is stored in DDR by invoking DMA of FPGA by python to generate a desired number of waveform points through a waveform generation function.

4. The method for correcting the multi-channel arbitrary waveform generator according to claim 3, wherein the instruction processing is directly called by an upper computer to the XDMA driver, the XDMA driver is sent to the FPGA through an AXI Lite channel of an XDMA IP core, the FPGA analyzes the instruction and then controls the FPGA to be allocated to perform corresponding work through the instruction.

5. The calibration method of the multi-channel arbitrary waveform generator according to claim 4, wherein the command control is to analyze command data generated by a command of an upper computer, and to configure corresponding data and chips according to the command of the upper computer;

firstly, distributing waveform data to corresponding DA channels according to the waveform data sent by an upper computer, and processing the waveform data of each DA channel to obtain the desired waveform data configuration of each channel;

then, generating and sending a command for writing in the plug-in Flash through a command of the upper computer, and writing the configured parameters into Flash for storing waveform correction data;

and finally, performing waveform conditioning and checking the waveform output of each corresponding path through an oscilloscope.

6. The method according to claim 5, wherein the command control sent data comprises all configuration data of the chip to be configured and the amplitude, phase, bias rate and bias of each DA channel waveform.

7. The method for calibrating a multichannel arbitrary waveform generator according to claim 6, wherein the digital signal output by the FPGA is converted into an analog signal by a DAC chip to perform waveform conditioning, the analog signal output by the DAC chip is amplified by an operational amplifier and a program-controlled amplifier, the amplified signal is processed and output by a filter and output to an oscilloscope, and the oscilloscope checks the waveform output of each path correspondingly.

8. A multi-channel arbitrary waveform generator correction system is characterized by comprising an upper computer, an FPGA, a waveform conditioning module and an oscilloscope, wherein the upper computer is sequentially connected with the FPGA, the waveform conditioning module and the oscilloscope;

the upper computer generates a waveform generation module and an instruction generation module by calling python, wherein the waveform generation module is used for generating waveform data, and the instruction generation module is used for sending a control instruction;

the FPGA is composed of a waveform control module, an instruction control module and a correction data storage module, wherein the waveform control module and the instruction control module are instantiated XDMA IP cores in the FPGA and are connected with an upper computer, data are sent to a waveform conditioning module and an oscilloscope, and the correction data storage module is correction data which is controlled by the FPGA and is stored by an external Flash without losing when power failure;

and the waveform conditioning module is used for responding to a waveform conditioning instruction sent by the FPGA, conditioning waveform data and storing the conditioned instruction in Flash of the correction data after an ideal effect is achieved.

9. The correction system of claim 8, wherein the waveform conditioning module comprises a DAC chip, an operational amplifier, a programmable amplifier and a filter, and the DAC chip is connected to the operational amplifier, the programmable amplifier and the filter in sequence.

10. The system of claim 9, wherein the waveform control module receives the host computer waveform data via DMA, and the command control module receives the host computer commands via AXI Lite.

Technical Field

The invention relates to the field of signal generators, and particularly provides a method and a system for correcting a multichannel arbitrary waveform generator.

Background

In the design process of an electronic system, an arbitrary waveform generator is indispensable in the processes of circuit hardware, detection and the like.

Disclosure of Invention

Aiming at the defects of the prior art, the invention provides a correction method of a multichannel arbitrary waveform generator with strong practicability.

The invention further aims to provide a multichannel arbitrary waveform generator correction system which is reasonable in design, safe and applicable.

The technical scheme adopted by the invention for solving the technical problems is as follows:

a multichannel random waveform generator correction method is characterized in that an upper computer sends multichannel waveform data and instructions through a PCIE interface, the multichannel waveform data carry out adjustment on delay, amplitude and bias of each channel according to the requirements of the instructions, configuration parameters of each channel are adjusted to serve as correction data to be stored in a plug-in Flash when each channel to be adjusted reaches an ideal state, and the correction data stored in the Flash are used for preventing power failure loss when the correction data are used for the next time.

Further, the upper computer sends the waveform data to an XDMA IP core of the FPGA through the PCIE interface to process data and instructions.

Further, the waveform data is stored in the DDR after the waveform data is generated by calling a waveform generating function through python to generate the expected number of waveform points, and then DMA of calling the FPGA is driven through xdma to store the waveform data.

Further, the instruction processing is to directly call the XDMA driver through an upper computer, send the XDMA driver to the FPGA through an AXILite channel of the XDMA IP core, analyze the instruction by the FPGA, and then control and allocate the FPGA to perform corresponding work through the instruction.

Further, the instruction control is to analyze instruction data generated by the instruction of the upper computer and configure corresponding data and chips according to the instruction of the upper computer;

firstly, according to the waveform data sent by the upper computer, the waveform data is distributed to the corresponding DA channels, the waveform data of each DA channel is processed to obtain the desired waveform data configuration of each channel,

then, generating and sending a command for writing in the plug-in Flash through a command of the upper computer, and writing the configured parameters into Flash for storing waveform correction data;

and finally, performing waveform conditioning and checking the waveform output of each corresponding path through an oscilloscope.

Preferably, the data sent by the command control includes all configuration data passing through the chip to be configured and the amplitude, phase, bias rate and bias of each DA channel waveform.

Further, the digital signals output by the FPGA are converted into analog signals through the DAC chip to achieve waveform conditioning, the analog signals output by the DAC chip are amplified through the operational amplifier and the program control amplifier, the amplified signals are processed and output through the filter and output to the oscilloscope, and the oscilloscope checks the waveform output of each corresponding path.

A multi-channel arbitrary waveform generator correction system comprises an upper computer, an FPGA, a waveform conditioning module and an oscilloscope, wherein the upper computer is sequentially connected with the FPGA, the waveform conditioning module and the oscilloscope;

the upper computer generates a waveform generation module and an instruction generation module by calling python, wherein the waveform generation module is used for generating waveform data, and the instruction generation module is used for sending a control instruction;

the FPGA is composed of a waveform control module, an instruction control module and a correction data storage module, wherein the waveform control module and the instruction control module are instantiated XDMA IP cores in the FPGA and are connected with an upper computer, data are sent to a waveform conditioning module and an oscilloscope, and the correction data storage module is correction data which is controlled by the FPGA and is stored by an external Flash without losing when power failure;

and the waveform conditioning module is used for responding to a waveform conditioning instruction sent by the FPGA, conditioning waveform data and storing the conditioned instruction in Flash of the correction data after an ideal effect is achieved.

Furthermore, the waveform conditioning module is composed of a DAC chip, an operational amplifier, a program control amplifier and a filter, wherein the DAC chip is sequentially connected with the operational amplifier, the program control amplifier and the filter.

Further, the waveform control module receives the waveform data of the upper computer through the DMA, and the instruction control module receives the instruction of the upper computer through the AXILite.

Compared with the prior art, the multichannel arbitrary waveform generator correction method and the multichannel arbitrary waveform generator correction system have the following outstanding beneficial effects:

the invention utilizes the reconfigurability and the programmability of the FPGA to receive waveform data and instructions sent by an upper computer, and then the FPGA analyzes and processes the waveform data and the instructions to configure a waveform conditioning module chip at the rear end and store correction data. The waveform of the multi-channel arbitrary waveform generator is corrected through an instruction of an upper computer, after a desired waveform data relation is obtained among channels, the instructed data is stored in a plug-in Flash through a correction module, correction parameters can be directly loaded from the Flash in the next outage, and the parameters of the channels do not need to be reconfigured.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to these drawings without creative efforts.

FIG. 1 is a schematic diagram of a calibration system for a multi-channel arbitrary waveform generator;

fig. 2 is a schematic structural diagram of the waveform conditioning module in fig. 1.

Detailed Description

The present invention will be described in further detail with reference to specific embodiments in order to better understand the technical solutions of the present invention. It is to be understood that the described embodiments are merely exemplary of the invention, and not restrictive of the full scope of the invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

A preferred embodiment is given below:

as shown in fig. 1 and 2, in the multichannel arbitrary waveform generator correction method in this embodiment, an upper computer sends multichannel waveform data and an instruction through a PCIE interface, the multichannel waveform data adjusts delay, amplitude, and offset of each channel according to the requirement of the instruction, when each channel to be adjusted reaches an ideal state, the configuration parameters of each channel are adjusted to be stored in a plug-in Flash as correction data, and the correction data stored in the Flash is used for preventing power failure from being lost when used next time.

And the upper computer sends the waveform data to an XDMA IP core of the FPGA through the PCIE interface to carry out data and instruction processing. The waveform data is stored in the DDR by calling a waveform generating function through python to generate expected waveform points, and then calling DMA (direct memory access) of the FPGA through xdma drive. The command processing is to directly call the XDMA driver through an upper computer, send the XDMA driver to the FPGA through an AXI Lite channel of an IP core of the XDMA, analyze the command by the FPGA and then control and allocate the FPGA to carry out corresponding work through the command.

The instruction control is used for analyzing instruction data generated by an instruction of the upper computer and configuring corresponding data and chips according to the instruction of the upper computer;

firstly, distributing waveform data to corresponding DA channels according to the waveform data sent by an upper computer, and processing the waveform data of each DA channel to obtain the desired waveform data configuration of each channel;

then, generating and sending a command for writing in the plug-in Flash through a command of the upper computer, and writing the configured parameters into Flash for storing waveform correction data;

and finally, performing waveform conditioning and checking the waveform output of each corresponding path through an oscilloscope.

The data sent by the command control includes all configuration data passing through the chip that needs to be configured, as well as the amplitude, phase, offset rate and offset of each DA channel waveform.

The digital signals output by the FPGA are converted into analog signals through the DAC chip to realize waveform conditioning, the analog signals output by the DAC chip are amplified through the operational amplifier and the program control amplifier, the amplified signals are processed and output through the filter and output to the oscilloscope, and the oscilloscope checks the waveform output of each corresponding path.

The system for realizing the method comprises the following steps: the multichannel arbitrary waveform generator correction system is composed of an upper computer, an FPGA, a waveform conditioning module and an oscilloscope, wherein the upper computer is sequentially connected with the FPGA, the waveform conditioning module and the oscilloscope.

The upper computer generates a waveform generation module and an instruction generation module by calling python, wherein the waveform generation module is used for generating waveform data, and the instruction generation module is used for sending a control instruction.

The FPGA is composed of a waveform control module, an instruction control module and a correction data storage module, wherein the waveform control module and the instruction control module are instantiated in the FPGA and connected with an upper computer, data are sent to a waveform conditioning module and an oscilloscope, and the correction data storage module is correction data which is controlled by the FPGA and is stored by an external Flash without losing power failure.

And the waveform conditioning module is used for responding to a waveform conditioning instruction sent by the FPGA, conditioning waveform data and storing the conditioned instruction in Flash of the correction data after an ideal effect is achieved.

The waveform conditioning module consists of a DAC chip, an operational amplifier, a program control amplifier and a filter, wherein the DAC chip is sequentially connected with the operational amplifier, the program control amplifier and the filter. The waveform control module receives waveform data of an upper computer through DMA, and the instruction control module receives instructions of the upper computer through AXI Lite.

The method can be simply understood that the multichannel arbitrary waveform generator of the PCIE interface is inserted into an upper computer with a PCIE slot; the method comprises the steps that power is turned on, an upper computer checks whether a PCIE device is mounted, an xdma driver is loaded after the PCIE device is mounted, and then a python library is called; generating a required waveform through python, for example, generating a square wave through a first channel, generating a Gaussian wave through a second channel, and generating a sine wave through a third channel; calling xdma drive through python to control parameters such as frequency, amplitude, bias, delay and the like of each path of waveform; sending waveform data and instructions generated by python to the FPGA board card through a program; checking the corresponding waveform output of each corresponding path through an oscilloscope; configuring parameters such as amplitude, bias, frequency and the like of a corresponding channel according to requirements; the upper computer sends an instruction to write the configured parameters into the plug-in Flash;

and finally, powering off and restarting the multichannel arbitrary waveform generator of the PCIE interface, and observing that the output waveform of each channel is the waveform data of the configured parameters after the waveform data of the corresponding channel is loaded. This proves that correction data loaded from Flash can be implemented.

The above embodiments are only specific ones of the present invention, and the scope of the present invention includes but is not limited to the above embodiments, and any suitable changes or substitutions that may be made by one of ordinary skill in the art and in accordance with the method and system claims for calibrating a multichannel arbitrary waveform generator according to the present invention shall fall within the scope of the present invention.

Although embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that changes, modifications, substitutions and alterations can be made in these embodiments without departing from the principles and spirit of the invention, the scope of which is defined in the appended claims and their equivalents.