阅读说明：本技术 一种用于蜂鸣器低电压启动电路 (Low-voltage starting circuit for buzzer ) 是由 张怀东 于 2019-11-22 设计创作，主要内容包括：本发明电路包括二极管D1、PMOS管P1、PMOS管控制电路、上电复位电路、振荡器，分频器。其中，D1正极连接电源VDD，负极连接信号线VCC，P1栅极连接PMOS管控制电路输出G，源极连接电源VDD，漏极连接信号线VCC，信号线VCC给PMOS管控制电路、上电复位电路、振荡器、分频器供电，上电复位电路输出P分别连接PMOS管控制电路、振荡器、分频器的输入，振荡器输出F连接到分频器的输入，分频器输出G2连接PMOS管控制电路输入，分频器输出G3连接到蜂鸣器驱动管栅极。本发明通过在蜂鸣器驱动管截止时打开PMOS管P1，起到电路低电压启动并正常工作的作用。该电路具有成本低和工作电压低的优点。(The circuit comprises a diode D1, a PMOS tube P1, a PMOS tube control circuit, a power-on reset circuit, an oscillator and a frequency divider. The positive electrode of the D1 is connected with a power supply VDD, the negative electrode of the D1 is connected with a signal line VCC, the grid of the P1 is connected with the output G of the PMOS tube control circuit, the source of the P1 is connected with the power supply VDD, the drain of the D1 is connected with the signal line VCC, the signal line VCC supplies power to the PMOS tube control circuit, the power-on reset circuit, the oscillator and the frequency divider, the output P of the power-on reset circuit is respectively connected with the inputs of the PMOS tube control circuit, the oscillator and the frequency divider, the output F of the oscillator is connected with the input of the frequency divider, the output G2 of the frequency divider is connected with. According to the invention, the PMOS tube P1 is opened when the buzzer driving tube is cut off, so that the circuit is started at low voltage and works normally. The circuit has the advantages of low cost and low working voltage.)

1. A low-voltage starting circuit for a buzzer is characterized by comprising a diode D1, a PMOS tube P1, a PMOS tube control circuit, a power-on reset circuit, an oscillator and a frequency divider. The positive electrode of the diode D1 is connected with a power supply VDD, the negative electrode of the diode D1 is connected with a signal line VCC, the grid electrode of the PMOS tube P1 is connected with a PMOS tube control circuit output G, the source electrode of the PMOS tube P1 is connected with the power supply VDD, the drain electrode of the PMOS tube P1 is connected with the signal line VCC, the signal line VCC supplies power to the PMOS tube control circuit, the power-on reset circuit, the oscillator and the frequency divider, the output P of the power-on reset circuit is respectively connected with the inputs of the PMOS tube control circuit, the oscillator and the frequency divider, the output F of the oscillator is connected with the input of the frequency divider, the output G2 of the frequency divider is connected with the input of the PMOS tube control circuit.

2. The low voltage start-up circuit for buzzer of claim 1, wherein said PMOS transistor control circuit output G1 turns on PMOS transistor P1 when the buzzer driving transistor is turned off, and PMOS transistor control circuit output G1 turns off PMOS transistor P1 when the buzzer driving transistor is turned on.

3. The low voltage start-up circuit for buzzer according to claim 1, wherein the substrate of the PMOS transistor P1 can be connected to the signal line VCC or selectively connected to the higher voltage potential of the signal line VCC and the power supply VDD, or floating.

4. The low voltage start circuit for buzzer of claim 1, wherein said diode D1 is at least one, and said diode D1 may be PMOS P1 or other parasitic diode.

5. The low voltage start circuit for a buzzer of claim 1, wherein said oscillator may not be controlled by a power-on-reset circuit output P.

6. The low voltage start circuit for buzzer of claim 1, wherein said signal line G2 and signal line G3 are the same signal line.

7. The method of claim 1, wherein the frequency divider is removed when the oscillator frequency is appropriate, and signal line G2 and signal line G3 are both output from an oscillator.

Technical Field

The invention relates to the field of buzzer circuits, in particular to a low-voltage starting circuit for a buzzer and a buzzer driving chip.

Background

As shown in fig. 6, in the conventional driving circuit for the buzzer, in order to prevent the electromagnetic coil from excessively reducing the power supply inside the chip when conducting, a diode D1 is added between the power supply and the power supply signal line VCC of the internal circuit, the power supply of the circuit needs to pass through a diode D1, the diode D1 can be regarded as a starting device of the buzzer circuit, the power supply has a relatively large voltage drop through the diode, which is about 0.5-0.7V, the general buzzer requires to operate when the power supply is below 1.5V, when the power supply is at 1.5V, the power supply voltage of the oscillator and other circuits is about 1V after the power supply is reduced through the diode, and under the voltage, the oscillator is difficult to operate or is not normal to operate.

Disclosure of Invention

The invention provides a low-voltage starting circuit for a buzzer, which solves the problem that an oscillator is difficult to work normally when the voltage of a power supply is lower.

In order to solve the above technical problem, the present invention provides a low voltage start circuit for a buzzer, as shown in fig. 1, including a diode D1, a PMOS transistor P1, a PMOS transistor control circuit, a power-on reset circuit, an oscillator, and a frequency divider. The positive electrode of the diode D1 is connected with a power supply VDD, the negative electrode of the diode D1 is connected with a signal line VCC, the grid electrode of a PMOS tube P1 is connected with a PMOS tube control circuit output G, the source electrode of a PMOS tube P1 is connected with the power supply VDD, the drain electrode of the PMOS tube P1 is connected with the signal line VCC, the substrate of the PMOS tube P1 is suspended or is selectively connected with the higher voltage potential in the signal line VCC and the power supply VDD, or the substrate of the PMOS tube P1 is connected with the signal line VCC, the signal line VCC supplies power to the PMOS tube control circuit, a power-on reset circuit, an oscillator and a frequency divider, the output P of the power-on reset circuit is respectively connected with the inputs of the PMOS tube control circuit, the oscillator and the frequency divider, the output F of the oscillator is connected with the input of the PMOS tube control circuit, the output G2 is.

As shown in fig. 1, when the circuit is just powered on, the power-on reset circuit outputs signal P to make the divider output G3 be at low level, the divider output G3 be at low level to make the buzzer driving tube turn off, the power-on reset circuit outputs signal P also makes the PMOS transistor control circuit output signal G1 be at low level, the PMOS transistor control circuit outputs signal G1 be at low level to make the PMOS transistor P1 be turned on, so as to reduce the voltage drop across diode D1, reduce the voltage drop across diode D1, and increase the VCC voltage of the signal line, which is helpful for the normal operation of the oscillator and the divider. Before the buzzer driving tube is conducted from power-on, the PMOS tube P1 can be conducted all the time or conducted for a period of time to complete charging of the signal line VCC, after the buzzer driving tube is conducted once, the PMOS tube P1 can be closed all the time, the PMOS tube P1 can be conducted when the buzzer driving tube is cut off by the PMOS tube control circuit output G1, the PMOS tube P1 is cut off when the buzzer driving tube is conducted by the PMOS tube control circuit output G1, and the buzzer driving tube works for a plurality of periods or works all the time, and is specifically determined by an application environment.

Preferably, there is at least one of said diodes.

Preferably, the oscillator may not be controlled by the power-on reset circuit output P.

Preferably, the signal line G2 and the signal line G3 may be the same signal line.

Preferably, the frequency divider can be eliminated when the oscillator frequency is appropriate, and the signal line G2 and the signal line G3 are both output by the oscillator.

Preferably, the substrate of the PMOS transistor P1 is connected to the signal line VCC or selectively connected to the higher voltage potential of the signal line VCC and the power supply VDD, or floating.

The invention has the following beneficial effects: according to the low-voltage starting circuit for the buzzer, the PMOS tube between the power line and the internal power supply signal line is opened when the buzzer driving tube is cut off, so that the power supply voltage of the internal circuit module is increased, and the low-voltage starting and normal working functions of the circuit are achieved. The circuit has the advantages of low cost and low working voltage. .

Drawings

Fig. 1 is a schematic structural diagram of a low-voltage starting circuit for a buzzer of the present invention.

Fig. 2 is a schematic diagram of a low voltage start-up circuit for a buzzer according to a first embodiment of the present invention.

FIG. 3 is a timing diagram of a low voltage start-up circuit for a buzzer according to a first embodiment of the present invention.

Fig. 4 is a schematic diagram of a low voltage start-up circuit for a buzzer according to a second embodiment of the present invention.

FIG. 5 is a timing diagram of a low voltage start-up circuit for a buzzer according to a second embodiment of the present invention.

Fig. 6 is a schematic diagram of the background art.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention will be described in further detail below with reference to the accompanying drawings and specific embodiments.

As shown in fig. 1, the low voltage start circuit for a buzzer provided by the present invention includes a diode D1, a PMOS transistor P1, a PMOS transistor control circuit, a power-on reset circuit, an oscillator, and a frequency divider. The diode D1 has an anode connected to a power supply VDD, a cathode connected to a signal line VCC, a gate of a PMOS transistor P1 connected to the output G of the PMOS transistor control circuit, a source connected to the power supply VDD, a drain connected to the signal line VCC, the signal line VCC supplies power to the PMOS transistor control circuit, a power-on reset circuit, an oscillator and a frequency divider, the output P of the power-on reset circuit is connected to the inputs of the PMOS transistor control circuit, the oscillator and the frequency divider respectively, the output F of the oscillator is connected to the input of the frequency divider, the output G2 of the frequency divider is connected to the input of the PMOS transistor control circuit, and the output G3 of the frequency divider is connected to. In practical application, the oscillator may not be controlled by the output P of the power-on reset circuit, the signal line G2 and the signal line G3 may be the same signal line, and the substrate of the PMOS transistor P1 is connected to the signal line VCC or selectively connected to the higher voltage potential of the signal line VCC and the power supply VDD, or floating.

The first embodiment of the present invention, as shown in fig. 2: the power-on reset circuit comprises a diode D1, a PMOS tube P1, a PMOS tube control circuit, a power-on reset circuit, an oscillator and a frequency divider. The positive electrode of the diode D1 is connected with a power supply VDD, the negative electrode of the diode D1 is connected with a signal line VCC, the grid electrode of a PMOS tube P1 is connected with a PMOS tube control circuit output G, the source electrode of a PMOS tube P1 is connected with the power supply VDD, the drain electrode of the PMOS tube P1 is connected with the signal line VCC, the substrate of the PMOS tube P1 is connected with the signal line VCC, the signal line VCC supplies power to the PMOS tube control circuit, the power-on reset circuit, the oscillator and the frequency divider, the output P of the power-on reset circuit is respectively connected with the inputs of the PMOS tube control circuit, the oscillator and the frequency divider, the output F of the oscillator is connected with the input of the frequency divider, the output G2 of the frequency divider is connected with the input of. The signal wire VCC is externally connected with a capacitor C1, and the other end of the external capacitor C1 is connected with the ground wire.

In a first embodiment of the present invention, as shown in fig. 3, with reference to fig. 2, when the power supply VDD is powered on, the power-on reset circuit starts to operate by charging the signal line VCC through a diode D1, the power-on reset circuit outputs P to a high level, the power-on reset circuit outputs P resets the oscillator and the frequency divider, the frequency divider outputs G2 to a low level, the PMOS transistor control circuit outputs G1 to a low level when the power-on reset circuit outputs P to a high level, so that the PMOS transistor P1 is turned on, the PMOS transistor P1 charges the external capacitor C1, the signal line VCC potential further rises to provide a high enough voltage for the internal circuits such as the oscillator and the frequency divider to ensure the normal operation of the circuit, after a period of time, the power-on reset circuit outputs P changes from a high level to a low level, the PMOS transistor control circuit outputs G1 keeps the low level unchanged, and the oscillator and the frequency divider start to operate, and after a period of time, the output G2 of the frequency divider is at a high level, the high level of the output G2 of the frequency divider enables the output G1 of the MOS tube control circuit to be inverted to be at a high level, the P1 of the PMOS tube is cut off, and after a period of time, the output G3 of the frequency divider is at a high level, and the buzzer driving tube starts to work.

In other operation sequences of the first embodiment of the present invention, the power-on reset output P reset period may be low level, and not necessarily high level as shown in fig. 3, and the frequency divider output G2 may be high level during the reset period, and not necessarily low level as shown in fig. 3, but the same functions are performed when the frequency divider output G2 is low level during the reset period, that is, the PMOS transistor P1 is turned on during the power-on reset period, and the PMOS transistor P1 is turned on and off when the buzzer driving transistor is turned on.

A second embodiment of the invention is shown in fig. 4: the power-on reset circuit comprises a diode D1, a PMOS tube P1, a PMOS tube P2, a PMOS tube P3, a PMOS tube control circuit, a power-on reset circuit, an oscillator and a frequency divider. Wherein, the anode of the diode D1 is connected to the power VDD, the cathode of the diode D1 is connected to the signal line VCC, the gate of the PMOS tube P1 is connected to the PMOS tube control circuit output G, the source of the PMOS tube P1 is connected to the power VDD, the drain of the PMOS tube P1 is connected to the signal line VCC, the substrate of the PMOS tube P1 is connected to the signal line b1, the gate of the PMOS tube P2 is connected to the signal line VCC, the source of the PMOS tube P2 is connected to the power VDD, the drain of the PMOS tube P2 is connected to the signal line b1, the substrate of the PMOS tube P2 is connected to the signal line b1, the gate of the PMOS tube P3 is connected to the power VDD, the source of the PMOS tube P3 is connected to the signal line VCC, the drain of the PMOS tube P3 is connected to the signal line b1, the substrate of the PMOS tube P3 is connected to the signal line b1, the signal line VCC is used for powering the PMOS tube control circuit, the power supply to the power supply, the divider output G2 is connected to the buzzer driver gate. The signal wire VCC is externally connected with a capacitor C1, and the other end of the external capacitor C1 is connected with the ground wire.

A working timing sequence of the second embodiment of the present invention is shown in fig. 5, and with reference to fig. 4, a reset cycle in the drawing refers to a power-on reset cycle, where in the power-on reset cycle, the output G1 of the PMOS transistor control circuit is at a low level, the PMOS transistor P1 is turned on, the PMOS transistor P1 charges the external capacitor C1, the VCC potential of the signal line further rises to provide a sufficiently high voltage for internal circuits such as an oscillator and a frequency divider to ensure normal operation of the circuit, during the operation of the frequency divider, when the output G2 of the frequency divider is at a low level, the PMOS transistor P1 is turned on, the PMOS transistor P1 charges the external capacitor C1, and when the output G2 of the frequency divider is at a high level, the PMOS transistor P1 is turned off, and so on.

In other operation sequences of the second embodiment of the present invention, during the operation of the frequency divider, the PMOS transistor P1 may be turned on only when the first period of the frequency divider output G2 is at low level, or may be turned on only when the first period of the frequency divider output G2 is at low level before the frequency divider operation, depending on the size of the capacitor and the application conditions.

In summary, the low-voltage start circuit for the buzzer provided by the invention reduces the voltage difference between the power line and the internal power supply signal line by controlling the conduction time of the PMOS transistor between the power line and the internal power supply signal line, so that the buzzer can normally work under a relatively low voltage.

The above description is only an example of the present invention, and is not intended to limit the present invention, and it is obvious to those skilled in the art that various modifications and variations can be made in the present invention. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the scope of the claims of the present invention.