阅读说明：本技术 一种电压波形产生装置 (Voltage waveform generating device ) 是由 赖练章 于 2019-11-11 设计创作，主要内容包括：本发明提供一种电压波形产生装置，应用于脉冲宽度调制系统中。本发明的电压波形产生装置包括数字序列产生器模块、组合逻辑电路模块以及数模转换器模块，外部时钟输入信号经数字序列产生器模块和组合逻辑电路模块处理后产生预设时间长度的数字域电压波形并发送给数模转换器模块，数模转换器模块对预设时间长度的数字域电压波形进行转换处理后向外部输出预设时间长度的模拟电压波形。本发明的电压波形产生装置克服了目前现有技术方案的缺点，实现了一个任意可编程时间长度的电压波形。(The invention provides a voltage waveform generating device which is applied to a pulse width modulation system. The voltage waveform generating device comprises a digital sequence generator module, a combinational logic circuit module and a digital-to-analog converter module, wherein an external clock input signal is processed by the digital sequence generator module and the combinational logic circuit module to generate a digital domain voltage waveform with a preset time length and send the digital domain voltage waveform to the digital-to-analog converter module, and the digital-to-analog converter module converts the digital domain voltage waveform with the preset time length and outputs an analog voltage waveform with the preset time length to the outside. The voltage waveform generating device overcomes the defects of the prior art and realizes a voltage waveform with any programmable time length.)

1. A voltage waveform generator for use in a pulse width modulation system, comprising

Comprises the following steps: digital sequence generator module, combinatorial logic circuit module and digital analog converter module, external clock input signal is connected to the input of digital sequence generator module, digital sequence generator module's the end that resets is connected the output of combinatorial logic circuit module, digital sequence generator module's output is connected respectively combinatorial logic circuit module's input with digital analog converter module's input, external clock input signal warp digital sequence generator module with produce the digital domain voltage waveform of presetting time length after the combinatorial logic circuit module is handled and give digital analog converter module, digital analog converter module is right the analog voltage waveform of presetting time length is exported to the outside after the digital domain voltage waveform of presetting time length carries out the conversion.

2. The voltage waveform generating device according to claim 1, wherein the digital sequence is

The column generator module comprises a counter, the combinational logic circuit module comprises an OR gate, a first AND gate, a first D trigger and a pulse generator, the input end of the counter is connected with the external clock input signal, the output end of the counter is respectively connected with the input end of the OR gate, the input end of the first AND gate and the input end of the digital-to-analog converter module, the output end of the OR gate is connected with the reset end of the first D trigger, the output end of the first AND gate is connected with the clock input end of the first D trigger, and the output end of the first D trigger is connected with the reset end of the counter through the pulse generator.

3. The voltage waveform generating device according to claim 2, wherein the counter is arranged to be driven by a motor

Either synchronous or asynchronous.

4. The voltage waveform generation apparatus according to claim 3, wherein the count is

The counter is an asynchronous counter consisting of four second D flip-flops.

5. The voltage waveform generating device according to claim 2, wherein the or gate is

The first AND gate is an AND gate with an inverting input;

or, the or gate is an or gate without an inverting input, and the first and gate is an and gate without an inverting input.

6. The voltage waveform generating device according to any one of claims 2 to 5, wherein the digital sequencer module further comprises a delay unit, an input terminal of the delay unit is connected to the external clock input signal, an output terminal of the delay unit is connected to an input terminal of the counter, and a reset terminal of the delay unit is connected to an output terminal of the first D flip-flop through the pulse generator.

7. The voltage waveform generating device according to claim 6, wherein the delay unit comprises one or more third D flip-flops.

8. The voltage waveform generating device according to claim 7, wherein the delay unit comprises a third D flip-flop and a second AND gate, a reset terminal of the third D flip-flop is connected to a reset terminal of the counter, a clock terminal of the third D flip-flop is connected to an output terminal of the counter, and a Q output terminal of the third D flip-flop and the external clock input signal are respectively connected to two input terminals of the second AND gate.

9. The voltage waveform generating device according to claim 7, wherein the delay unit comprises four third D flip-flops connected in series, wherein the reset terminals of the four third D flip-flops are all connected to the reset terminal of the counter, the clock input terminal of the first third D flip-flop is connected to the external clock input signal, and the Q output terminal of the last third D flip-flop is connected to the input terminal of the counter.

10. The voltage waveform generating device according to claim 1, wherein the digital-to-analog conversion

The number of bits of the translator module may be 4 bits, 6 bits, 8 bits, 10 bits, 12 bits, 14 bits, or 16 bits.

Technical Field

The invention belongs to the technical field of pulse width modulation, and particularly relates to a voltage waveform generating device.

Background

In the PWM control and PWM modulation circuits, it is often necessary to generate a periodically rising voltage waveform, as shown in fig. 1, which is a PWM control schematic diagram of a DC-DC controller: 001 is a voltage dividing circuit composed of a resistor R1 and a resistor R2, and is used for detecting the output voltage of the system, and the detected output value is VS; 002 is an operational amplifier for generating a differential signal of VS and a reference voltage VREF and storing the differential signal (Vcomp) in the form of electric charges in the capacitor C1 (003). The Vcomp voltage is compared with the periodic signal Vsw generated by the sawtooth generator 004, and the generated square wave signal controls a metal oxide semiconductor field effect transistor (hereinafter referred to as MOSFET) M1. When the reference VREF < VS, the 002 output voltage Vcomp rises, the duty cycle of the square wave signal output by the comparator 005 decreases, and the duty cycle controls the buck converter composed of the switching tube M1(006), the rectifying tube M2(007), the inductor L1(008), the loads CL1 and RL1(009), and the power supply V1 (010); a decrease in the duty cycle of the signal Vcontrol (see fig. 2(a)) will cause the output voltage VOUT of the buck converter to decrease. When the reference VREF > VS and the 002 output voltage Vcomp decreases, the duty cycle of the square wave output by the comparator 005 increases (see fig. 2(b)), and this duty cycle signal will regulate the buck converter, causing the output voltage VOUT to increase. Through such feedback control, VS is finally made to trend toward VREF, i.e., VS becomes equal to VREF. VOUT ═ VREF (R1+ R2)/R1.

As described above, the periodic waveform generated by the sawtooth wave generator 004 is an essential part in the control of the DC-DC converter. Generally, the period of the periodic waveform is about several tens of KHZ to several tens of MHZ. However, in a special mode, such as a standby mode or a burst-mode (burst-mode), in order to meet the energy efficiency requirement and reduce power consumption, the operating frequency is reduced to within 1KHZ, even to several tens of HZ. In particular, in an AC-DC adapter control chip, in order to meet the level 6 energy efficiency requirement, the frequency is generally reduced to a range of 1KHZ to 10HZ in the standby mode.

As in fig. 3, generating voltage waveforms at frequencies of tens of KHZ and above can generally be achieved by charging the capacitor with current. The principle is that the current source 101 charges the capacitor 103, and when the charged voltage is greater than VREF, the comparator 104 is inverted, the transistor 105 is turned on, and the voltage on the capacitor 103 is discharged to 0 potential. A delay network is formed by a resistor 106 and a capacitor 107, after the voltage of the capacitor 103 is pulled down to 0 level, the comparator 104 is reset (the output is at low level), and finally conducted to the transistor 105 through the delay of the delay network formed by the resistor 106 and the capacitor 107, the transistor is turned off, and the current source 101 continues to charge the capacitor 103 and enters the next cycle. Finally, the waveform of the voltage across the capacitor 103 is the Vsw waveform of fig. 2 (a). An estimate can be made of the maximum period that fig. 3 is likely to do. For a 3.3V integrated circuit process, the minimum current source that can be realized is 0.2Ua (i.e. 200nA, the level of leakage in the chip is within 10nA, so 200nA can ensure that the leakage does not exceed 5%), assuming that the capacitance is 20pF, and when the charge is 3V, the charge time is:

this period corresponds to a frequency of 3 KHZ. Of course, the capacitance can be increased continuously, for example, to 100pF, and the period can be made to be 1.5ms, but the capacitance is integrated inside the chip, the area is very large, and the chip cost is greatly increased.

From the above analysis, it can be seen that the minimum frequency achievable by the method shown in fig. 3 is approximately 1 KHZ.

Fig. 4 is another conventional implementation. The working principle is as follows: the power supply 201 is a square wave with a frequency of about 20KHZ and the power supply 202 is a fixed voltage, e.g. 3V. The square wave 201 and the director 205 control the transistors 203 and 206 to be alternately turned on. When the transistor 203 is turned on, the transistor 206 is turned off, and the voltage source 202 charges the capacitor 204 through the transistor 203; when the transistor 206 is turned on, the transistor 203 is turned off, and the capacitor 204 discharges the charge charged in the first half cycle to the capacitor 207. Eventually, when the voltage at the output terminal OUT approaches the voltage source 202, the OUT voltage does not continue to rise. The comparator 208 detects that the voltage at the OUT terminal is close to the voltage source 202, outputs a high level, which reaches the transistor 211 through the delay network formed by the resistor 209 and the capacitor 210, and opens the transistor 211 to discharge the voltage at the capacitor 207 to 0 level. At this point, a complete cycle is complete. The voltage source 202 then continues to charge … … the capacitor 204 and the process repeats over and over.

The time constant that fig. 4 can achieve can be estimated by: assume that the capacitance of capacitor 204 is 0.5pF and the capacitance of capacitor 207 is 50 pF. The voltage of the voltage source 202 is 3V. During the first half of the period that transistor 203 was on, the charge stored by capacitor 204 is: 0.5Pf × 3V, the second half cycle, the transistor 206 is turned on, and assuming that there is an initial voltage Vo on the capacitor 207 and the voltage on the capacitor 207 becomes V1 after the transistor 206 is turned on, the following formula is shown:

0.5pF*3V+V₀*50pF＝50.5pF*V₁

within 50us of a period, the voltage of the OUT port rises by 30 mV. Then 100 cycles are required to rise to 3V and the rise time of the waveform is:

50us*100＝5ms

then can the clock period be greatly increased to achieve a longer length of time? The answer is negative because in a real process the capacitor has a certain leakage, around 5nA at high temperature, and the voltage on 100us capacitor will drop by 5nA by 100us/0.5pF to 1V. This results in too much leakage and therefore it is difficult to implement this solution for a long period of time.

As mentioned above, two existing schemes for implementing millisecond-scale time constant waveforms are listed in fig. 3 and 4, and have several significant disadvantages as follows:

first, the noise impact is large. The scheme of fig. 3 in order to save capacitor area, the current source 101 is typically set at a level of several hundred nA, which is easily susceptible to noise impression at this level of current; the arrangement of fig. 4, with the capacitor 204 set at a few hundred fF, also leads to the same problem, being very much affected by noise. The switching of the transistor 203 or 206 causes charge injection into the capacitor 204, which is also affected by the peripheral wiring.

Secondly, the time constant can only be in the order of milliseconds at most, and is difficult to increase continuously, and if a frequency of about 20HZ, namely a time constant of 50ms, is to be realized, the schemes of fig. 3 and 4 cannot be used.

Thirdly, it is difficult to control precisely, such as the methods of fig. 3 and 4, because they are easily affected by noise, it is difficult to achieve very precise control.

Fourth, the power consumption is relatively large. The methods shown in fig. 3 and 4 both use an operational amplifier or a comparator, and the power consumption of the whole circuit is relatively large.

Therefore, a solution for realizing a voltage waveform with an arbitrary programmable time length is urgently needed.

Disclosure of Invention

The invention provides a voltage waveform generating device, which solves the problem that the existing scheme can not realize the voltage waveform with any programmable time length.

To solve the foregoing technical problem, in one aspect, an embodiment of the present invention provides a voltage waveform generating apparatus applied in a pulse width modulation system, including: digital sequence generator module, combinatorial logic circuit module and digital analog converter module, external clock input signal is connected to the input of digital sequence generator module, digital sequence generator module's the end that resets is connected the output of combinatorial logic circuit module, digital sequence generator module's output is connected respectively combinatorial logic circuit module's input with digital analog converter module's input, external clock input signal warp digital sequence generator module with produce the digital domain voltage waveform of presetting time length after the combinatorial logic circuit module is handled and give digital analog converter module, digital analog converter module is right the analog voltage waveform of presetting time length is exported to the outside after the digital domain voltage waveform of presetting time length carries out the conversion.

According to an embodiment of the present invention, the digital sequence generator module includes a counter, the combinational logic circuit module includes an or gate, a first and gate, a first D flip-flop, and a pulse generator, an input end of the counter is connected to the external clock input signal, an output end of the counter is respectively connected to an input end of the or gate, an input end of the first and gate, and an input end of the digital-to-analog converter module, an output end of the or gate is connected to a reset end of the first D flip-flop, an output end of the first and gate is connected to a clock input end of the first D flip-flop, and an output end of the first D flip-flop is connected to the reset end of the counter through the pulse generator.

According to another embodiment of the invention, the counter is a synchronous counter or an asynchronous counter.

According to another embodiment of the present invention, the counter is an asynchronous counter composed of four second D flip-flops.

According to another embodiment of the present invention, the or gate is an or gate with an inverting input, the first and gate is an and gate with an inverting input;

or, the or gate is an or gate without an inverting input, and the first and gate is an and gate without an inverting input.

According to another embodiment of the present invention, the digital sequence generator module further includes a delay unit, an input end of the delay unit is connected to the external clock input signal, an output end of the delay unit is connected to an input end of the counter, and a reset end of the delay unit is connected to an output end of the first D flip-flop through the pulse generator.

According to another embodiment of the present invention, the delay unit includes one or more third D flip-flops.

According to another embodiment of the present invention, the delay unit includes a third D flip-flop and a second and gate, a reset terminal of the third D flip-flop is connected to a reset terminal of the counter, a clock terminal of the third D flip-flop is connected to an output terminal of the counter, and a Q output terminal of the third D flip-flop and the external clock input signal are respectively connected to two input terminals of the second and gate.

According to another embodiment of the present invention, the delay unit includes four third D flip-flops connected in series, reset terminals of the four third D flip-flops are all connected to the reset terminal of the counter, a clock input terminal of a first third D flip-flop is connected to the external clock input signal, and a Q output terminal of a last third D flip-flop is connected to the input terminal of the counter.

According to another embodiment of the present invention, the number of bits of the digital-to-analog converter module may be 4 bits, 6 bits, 8 bits, 10 bits, 12 bits, 14 bits, or 16 bits.

The invention has the beneficial effects that:

the voltage waveform generating device of the embodiment of the invention is a scheme based on a digital sequence generating circuit and digital-to-analog conversion, and mainly comprises a digital sequence generator module, a combinational logic circuit module and a digital-to-analog converter module, wherein an external clock input signal generates voltage waveform of a digital domain through the digital sequence generator module and the combinational logic circuit module, and then the voltage waveform is converted into analog voltage by the digital-to-analog converter for output. Because the digital circuit does not have the charge leakage problem, and the time length of the digital code stored in the digital circuit can be controlled by any clock period, the analog voltage waveform with the preset time length can be obtained, therefore, the voltage waveform generating device of the embodiment of the invention overcomes the defects of the prior art, realizes a voltage waveform with any programmable time length, and has the following advantages:

compared with other voltage waveform generating circuits, the voltage waveform generating device provided by the embodiment of the invention has extremely strong anti-interference capability, and the generated circuit waveform can be accurately controlled, so that the yield is high in large-scale production;

secondly, the voltage waveform generated by the voltage waveform generating device of the invention can be any time, and the time can be continuously increased by increasing the clock period or the number of D triggers of a counter as long as required;

thirdly, the voltage waveform generating device of the embodiment of the invention is based on a digital circuit and a digital-to-analog converter, and has low power consumption;

fourth, the voltage waveform generating device of the embodiment of the present invention is based on a digital circuit and a digital-to-analog converter, is very easy to integrate, is suitable for an integrated circuit process with a small line width, and can achieve a small area.

Fifth, the voltage waveform generator according to the embodiment of the present invention is based on a digital circuit and a digital-to-analog converter, and can generate a more complex voltage waveform by expanding a digital sequence generator circuit conveniently, that is, has a good expansion capability.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed to be used in the description of the embodiments of the present invention will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other drawings can be obtained according to these drawings without inventive exercise.

FIG. 1 is a schematic diagram of a PWM control principle of a DC-DC controller in the prior art;

FIG. 2 is a schematic diagram of a duty cycle shifted waveform for PWM control of the DC-DC controller shown in FIG. 1;

FIG. 3 is a circuit schematic of a prior art scheme for current-to-capacitor charging to achieve a periodic ramp waveform;

FIG. 4 is a circuit schematic of a prior art scheme for alternating capacitor charging to achieve a voltage ramp waveform;

FIG. 5 is a schematic structural diagram of one embodiment of a voltage waveform generating apparatus of the present invention;

fig. 6 is a schematic circuit diagram of a first embodiment of the voltage waveform generating device of the present invention;

FIG. 7 is a graph of an output waveform corresponding to FIG. 6;

fig. 8 is a schematic circuit diagram of a second embodiment of the voltage waveform generating device of the present invention;

FIG. 9 is a graph of an output waveform corresponding to FIG. 8;

FIG. 10 is a circuit schematic of one embodiment of a counter 301 of the present invention;

fig. 11 is a schematic circuit diagram of a third embodiment of the voltage waveform generating device of the present invention;

FIG. 12 is a waveform diagram of an output corresponding to FIG. 11;

FIG. 13 is a schematic circuit diagram of one embodiment of the delay cell 307 of the present invention;

FIG. 14 is a schematic circuit diagram of another embodiment of delay unit 307 of the present invention;

fig. 15 is a circuit schematic of one embodiment of the digital to analog converter module 332 of the present invention.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

Referring to fig. 5, an embodiment of the present invention provides a voltage waveform generating apparatus 1, applied in a pulse width modulation system, including: the digital sequence generator module 330, the combinational logic circuit module 331 and the digital-to-analog converter module 332, an input end of the digital sequence generator module 330 is connected to an external clock input signal 333, a reset end of the digital sequence generator module 330 is connected to an output end of the combinational logic circuit module 331, an output end of the digital sequence generator module 330 is respectively connected to an input end of the combinational logic circuit module 331 and an input end of the digital-to-analog converter module 332, the external clock input signal 333 is processed by the digital sequence generator module 330 and the combinational logic circuit module 331 to generate a digital domain voltage waveform with a preset time length and send the digital domain voltage waveform to the digital-to-analog converter module 332, and the digital-to-analog converter module 332 converts the digital domain voltage waveform with the preset time length and outputs an analog voltage waveform with the preset time.

The voltage waveform generator of the embodiment of the invention is a scheme based on a digital sequence generator circuit and digital-to-analog conversion, mainly comprises a digital sequence generator module 330, a combinational logic circuit module 331 and a digital-to-analog converter module 332, and has the following basic principle: the external clock input signal 333 is converted into an analog voltage by the digital-to-analog converter after generating a voltage waveform of a digital domain through the digital sequence generator module and the combinational logic circuit module. Because the digital circuit does not have the charge leakage problem, and the time length of the digital code stored in the digital circuit can be controlled by any clock period, the analog voltage waveform with the preset time length can be obtained, and therefore, the voltage waveform generating device of the embodiment of the invention overcomes the defects of the prior art, realizes a voltage waveform with any programmable time length, and has excellent performance.

Alternatively, as shown in fig. 6 and 8, the digital sequence generator module 330 in the voltage waveform generating device 1 according to the embodiment of the present invention includes a counter 301, and the combinational logic circuit module 331 includes an or gate 302, a first and gate 303, a first D flip-flop 305, and a pulse generator 304, wherein an input terminal of the counter 301 is connected to the external clock input signal CLK, an output terminal of the counter 301 is respectively connected to an input terminal of the or gate 301, an input terminal of the first and gate 303, and an input terminal of the digital-to-analog converter module 306 (i.e., 332), an output terminal of the or gate 302 is connected to a reset terminal of the first D flip-flop 305, an output terminal of the first and gate 303 is connected to a clock input terminal of the first D flip-flop 305, and an output terminal of the first D flip-flop 305 is connected to the reset.

In the embodiment shown in fig. 6 301 is a counter for generating a rising sequence of numbers, such as the signals b3, b2, b1, b0 in fig. 7. Counter 301 generates a sequence of 4-bit numbers from 000000010010 … up to 1111. In an actual circuit, the circuit may also be a digital sequence of any bit, such as 3 bits, 6 bits, 8 bits, etc., according to design requirements. 302 is a 4-input or gate with one input inverted to detect "0001"; when the output of the counter 301 is "0001", the or gate 302 outputs a low-level signal, resetting the first D flip-flop 305. The 4-input first and gate 303 is used to detect the end of the counter count, and when the counter 301 output is "1111", the output of 303 jumps from "0" to "1". Continuing to count, the output of 301 will change from "1111" to the initial state "0000", i.e., 303 will output a falling edge that will set the first D flip-flop 305 to "1", i.e., the Counter _ END signal is "1" (as shown in FIG. 7). The rising edge of Counter _ END signal will cause pulse generator 304 to output a narrow pulse signal that resets Counter 301. After the counter is reset, a new round of counting will start from "0000". The input of the first and gate 303 may also be an inverted signal of the (b3, b2, b1, b0) signal and a combination thereof. As shown in fig. 8, the first and gate 303 has two inputs that are inverted, when the counter 301 counts to "1100", the output of 303 goes high, and when it counts to 1101, the output of 303 will have a falling edge that will cause the first D flip-flop 305 to go high. The first D flip-flop 305 is set to "1" from "0", that is, a rising edge occurs, and the rising edge is inputted to the pulse generator 304, and the pulse generator 304 will output a narrow pulse signal, so that the counter 301 is reset to the initial state "0000", and the counting will be restarted, and the waveform is as shown in fig. 9. It can be seen that the voltage waveform generation apparatus according to the embodiment of the present invention can realize various count termination states by modifying the and gate.

The output of the counter in the voltage waveform generating device according to the embodiment of the present invention is input to the digital-to-analog converter, and is converted into an analog voltage output (such as the OUT voltage waveform of fig. 7 and 9). Thus, the analog voltage is the voltage waveform that we want, because the counter can produce the accurate digital sequence output, and the digital-to-analog converter can be designed more accurately, and this scheme naturally has very high precision.

Optionally, the counter 301 in the embodiment of the present invention is a synchronous counter or an asynchronous counter.

Alternatively, referring to fig. 10, the counter 301 according to the embodiment of the present invention is an asynchronous counter composed of four second D flip-flops 3011.

Optionally, the or gate 302 according to the embodiment of the present invention is an or gate with an inverting input, and the first and gate 303 is an and gate with an inverting input;

alternatively, or gate 302 is an or gate without an inverting input and first and gate 303 is an and gate without an inverting input.

Optionally, referring to fig. 11, the digital sequence generator module 331 of the embodiment of the present invention further includes a delay unit 307, an input terminal of the delay unit 307 is connected to the external clock input signal 333, an output terminal of the delay unit 307 is connected to the input terminal of the counter 301, and a reset terminal of the delay unit 307 is connected to the output terminal of the first D flip-flop 305 through the pulse generator 304.

In the embodiment of the present invention, before the counter 301, a delay unit 307 is added, and the delay unit 307 is used to increase the time length of the "0" level signal before the voltage rising signal, as shown in the 603 straight line in fig. 12, the longer the delay is, the longer the time duration of the straight line is. In actual circuit control, the delay may be the time when the power tube is turned on in a peak control system, or may be intentionally inserted into the time for some control purpose.

Alternatively, as shown in fig. 13 and 14, the delay unit 307 of the embodiment of the present invention includes one or more third D flip-flops 3071.

Preferably, the delay unit 301 according to the embodiment of the present invention includes a third D flip-flop 3071 and a second and gate 308, a reset terminal of the third D flip-flop 3071 is connected to the reset terminal of the counter 301, a clock terminal of the third D flip-flop 3071 is connected to an output terminal of the counter 301, and a Q output terminal of the third D flip-flop 3071 and the external clock input signal 333 are respectively connected to two input terminals of the second and gate 308.

Fig. 13 shows one implementation of the delay unit 307. An external clock input signal CLK is input into an asynchronous counter composed of a second D flip-flop 3011 for counting, when the count reaches 2^NAfter (where N ═ 4) clock cycles, the counter 301 outputs a bit high; in the next cycle, the second D flip-flop 3011 in the counter 301 will output a falling edge, and the third D flip-flop 3071 will read the signal (high level) from the "D" terminal under the action of the falling edge and output the signal to the "Q" terminal of 3071. 3071 the high level output will enable the AND gate 308 and the external clock input signal CLK will be output normally. The delay Td of this delay unit can be calculated as:

Td＝2^Nt, where T is the period (1) of the clock CLK

When there is a reset signal (high) input, all D flip-flops will be reset and the counting will start from the new.

As shown in fig. 12, the digital sequence (b3, b2, b1, b0) generated by the digital module is input to the digital-to-analog converter 306, 306 generates corresponding analog output according to the difference of the input digital signal, such as the OUT curve of fig. 12, which is the voltage waveform curve we need. From the clock period of CLK this rise time can be estimated. Assuming that the period of the clock CLK is T, the sequence of numbers is 4 bits and the counter is a counter as in fig. 10. The time that the number sequence rises from "0000" to "1111" is:

T_R＝2^N·T，N＝4 (2)

the expression (2) is the same as the expression (1), but corresponds to different meanings.

Optionally, referring to fig. 14, the delay unit 307 includes four serially connected third D flip-flops 3071, reset terminals of the four third D flip-flops 3071 are all connected to the reset terminal of the counter 301, a clock input terminal of a first third D flip-flop 3071 is connected to the external clock input signal 333, and a Q output terminal of a last third D flip-flop 3071 is connected to the input terminal of the counter 301.

In the embodiment of the invention, T is increased by adding more third D flip-flops 3071 in front of the counter_R. As shown in fig. 14, on the basis of fig. 10, by adding 4 third D flip-flops 3071, the time when the number sequence rises from "0000" to "1111" becomes:

T_R＝2^N·T·2⁴，N＝4 (3)

(3) the rise time is increased by 16 times! If the selection period T is 200us, T_RThe calculation is as follows:

T_R＝2⁴·200us·2⁴＝51.2ms

therefore, the embodiment of the invention can achieve the rise time of tens of milliseconds. If more third D flip-flops are added, the rise time will be further increased, which can be arbitrarily increased.

Alternatively, the number of bits of the digital-to-analog converter module 332 according to the embodiment of the present invention may be 4 bits, 6 bits, 8 bits, 10 bits, 12 bits, 14 bits, or 16 bits.

As shown in fig. 15, a specific implementation of the digital-to-analog converter module 332 is shown, but the digital-to-analog converter module in the embodiment of the present invention is not limited to a specific type, and any method capable of implementing digital-to-analog conversion may be used in the present invention. Meanwhile, the number of bits of the dac module 332 may be any desired number of bits, such as 6 bits, 8 bits, or even 10 bits, and the higher the number of bits is, the smaller the voltage difference of each step of the output voltage waveform (the OUT signal in fig. 7 and 9) is, and the higher the accuracy of the analog signal is.

In summary, the voltage waveform generating device of the embodiment of the invention has the following advantages:

compared with other voltage waveform generating circuits, the voltage waveform generating device provided by the embodiment of the invention has extremely strong anti-interference capability, and the generated circuit waveform can be accurately controlled, so that the yield is high in large-scale production;

secondly, the voltage waveform generated by the voltage waveform generating device of the invention can be any time, and the time can be continuously increased by increasing the clock period or the number of D triggers of a counter as long as required;

thirdly, the voltage waveform generating device of the embodiment of the invention is based on a digital circuit and a digital-to-analog converter, and has low power consumption;

fourth, the voltage waveform generating device of the embodiment of the present invention is based on a digital circuit and a digital-to-analog converter, is very easy to integrate, is suitable for an integrated circuit process with a small line width, and can achieve a small area.

Fifth, the voltage waveform generator according to the embodiment of the present invention is based on a digital circuit and a digital-to-analog converter, and can generate a more complex voltage waveform by expanding a digital sequence generator circuit conveniently, that is, has a good expansion capability.

While the present invention has been described with reference to the embodiments shown in the drawings, the present invention is not limited to the embodiments, which are illustrative and not restrictive, and it will be apparent to those skilled in the art that various changes and modifications can be made therein without departing from the spirit and scope of the invention as defined in the appended claims.