阅读说明：本技术 一种驱动多路晶闸管的触发控制器 (Trigger controller for driving multi-channel thyristor ) 是由 程新兵 陈绒 周相 杨建华 钱宝良 耿玖源 于 2019-11-26 设计创作，主要内容包括：本发明公开了一种驱动多路晶闸管的触发控制器，目的是解决现有晶闸管触发方式不能触发多路晶闸管的问题。本发明由光接收模块、N个MOSFET驱动器、N个功率MOSFET、(N?1)个集成单稳态触发器组成；光接收模块、第一MOSFET驱动器与第一功率MOSFET构成第一路信号传输通道；光接收模块、第一集成单稳态触发器、第二MOSFET驱动器以及第二功率MOSFET构成第二路信号传输通道；……；光接收模块、第(N?1)集成单稳态触发器、第N MOSFET驱动器、第N功率MOSFET构成第N路信号传输通道；N路信号传输通道分别触发N个晶闸管；本发明通过调节(N?1)个集成单稳态触发器的时延，可弥补现有触发方式中多路脉冲变压器的输出一致性难以解决的不足，实现N路晶闸管的精确控制。(The invention discloses a trigger controller for driving a multi-channel thyristor, and aims to solve the problem that the existing thyristor trigger mode cannot trigger the multi-channel thyristor. The invention is composed of a light receiving module, N MOSFET drivers, N power MOSFETs and (N-1) integrated monostable triggers; the light receiving module, the first MOSFET driver and the first power MOSFET form a first signal transmission channel; the light receiving module, the first integrated monostable trigger, the second MOSFET driver and the second power MOSFET form a second path of signal transmission channel; … …, respectively; the light receiving module, the (N-1) th integrated monostable trigger, the Nth MOSFET driver and the Nth power MOSFET form an Nth signal transmission channel; n signal transmission channels respectively trigger N thyristors; according to the invention, by adjusting the time delay of (N-1) integrated monostable triggers, the defect that the output consistency of a multi-path pulse transformer in the existing trigger mode is difficult to solve can be made up, and the accurate control of the N-path thyristor can be realized.)

1. A trigger controller for driving a multi-channel thyristor is characterized in that the trigger controller for driving the multi-channel thyristor consists of a light receiving module, N metal-oxide semiconductor field effect transistors (MOSFET drivers), N power MOSFETs and (N-1) integrated monostable triggers; the N MOSFET drivers are marked as a first MOSFET driver, a second MOSFET driver, … …, a second nMOSFET driver, … … and a second NMOSFET driver; the N power MOSFETs are marked as a first power MOSFET, a second power MOSFET, … …, an nth power MOSFET, … … and an nth power MOSFET; (N-1) the integrated monostable triggers are recorded as a first integrated monostable trigger, a second integrated monostable trigger, … …, an (N-1) th integrated monostable trigger, … … and an (N-1) th integrated monostable trigger; n is more than or equal to 2 and less than or equal to N; n is a positive integer;

the light receiving module, the first MOSFET driver and the first power MOSFET form a first signal transmission channel; the light receiving module, the first integrated monostable trigger, the second MOSFET driver and the second power MOSFET form a second path of signal transmission channel; the light receiving module, the second integrated monostable trigger, the third MOSFET driver and the third power MOSFET form a third signal transmission channel; … …, respectively; the light receiving module, the (n-1) th integrated monostable trigger, the nth MOSFET driver and the nth power MOSFET form an nth signal transmission channel … …; the light receiving module, the (N-1) th integrated monostable trigger, the NMOSFET driver and the Nth power MOSFET form an Nth signal transmission channel; the first signal transmission channel is used for triggering a first thyristor S in an external pulse power system₁The second signal transmission channel is used for triggering a second thyristor S in the external pulse power system₂The third signal transmission channel is used for triggering a third thyristor S in the external pulse power system₃… …, the nth signal transmission channel is used to trigger the nth thyristor S in the external pulse power system_n… …, the Nth signal transmission channel is used to trigger the Nth thyristor S in the external pulse power system_NThe N signal transmission channels share the optical receiving module;

in the first signal transmission channelThe optical receiving module is an optical-electrical conversion module, is connected with the first MOSFET driver, is externally connected with a synchronous signal source, receives an optical pulse signal generated by the synchronous signal source, converts the received optical pulse signal into a pulse weak current signal and transmits the pulse weak current signal to the first MOSFET driver; the first MOSFET driver is connected with the light receiving module and the first power MOSFET, amplifies the pulse weak current signal received from the light receiving module into a pulse large current signal and sends the pulse large current signal to the first power MOSFET; first power MOSFET and first thyristor S in first MOSFET driver and external pulsed power system₁The output end of the first power MOSFET is used as the output end of the first signal transmission channel, and the pulse high-current signal with higher intensity is sent to a first thyristor S in an external pulse power system₁For triggering the first thyristor S₁；

The first integrated monostable trigger in the second signal transmission channel is connected with the light receiving module and the second MOSFET driver, is an element with time delay function, delays the pulse weak current signal received from the light receiving module, and outputs the pulse weak current signal with time delay t relative to the first signal transmission channel to the second MOSFET driver₁The pulsed weak current signal of (2); the second MOSFET driver is connected with the first integrated monostable trigger and the second power MOSFET and receives the signal with time delay t from the first integrated monostable trigger₁Amplifying the pulsed weak current signal to have a time delay of t₁Pulsing a high current signal and will have a time delay of t₁Sending the pulse large-current signal to a second power MOSFET; second power MOSFET and second MOSFET driver and second thyristor S in external pulsed power system₂Connected to receive the signal from the second MOSFET driver with a time delay t₁Converting the pulsed high current signal to a higher strength signal with a time delay of t₁The output end of the second power MOSFET is used as the output end of the second signal transmission channel, and the higher-intensity signal with the time delay of t₁Sending out a pulse heavy current signalSecond thyristor S in partial pulse power system₂For triggering the second thyristor S₂；

The second integrated monostable trigger in the third signal transmission channel is connected with the light receiving module and the third MOSFET driver, is completely the same as the first integrated monostable trigger, delays the pulse weak current signal received from the light receiving module, and outputs a delay t to the third MOSFET driver relative to the first signal transmission channel₂The pulsed weak current signal of (2); the third MOSFET driver is connected with the second integrated monostable trigger and the third power MOSFET and receives the signal with time delay t from the second integrated monostable trigger₂Amplifying the pulsed weak current signal to have a time delay of t₂Pulsing a high current signal and will have a time delay of t₂Sending the pulse large-current signal to a third power MOSFET; third power MOSFET and third MOSFET driver and third thyristor S in external pulsed power system₃Connected to receive the signal from the third MOSFET driver with a time delay t₂Converting the pulsed high current signal to a higher strength signal with a time delay of t₂The output end of the third power MOSFET is used as the output end of the third signal transmission channel, and the higher-intensity signal with the time delay of t₂Sending the pulse large current signal to a third thyristor S in an external pulse power system₃For triggering the third thyristor S₃；

According to the same connection mode with the third signal transmission channel, the output end of the nth power MOSFET is used as the output end of the nth signal transmission channel, and the time delay t relative to the first signal transmission channel is set_n-1Sending the pulse large current signal to the nth thyristor S in the external pulse power system_nFor triggering the n-th thyristor S_n(ii) a … …, respectively; the output end of the Nth power MOSFET is used as the output end of the Nth signal transmission channel, and the time delay of the Nth power MOSFET relative to the Nth signal transmission channel is t_N-1Sending the pulse large current signal to the Nth thyristor S in the external pulse power system_NFor triggering the Nth thyristor S_N。

2. The firing controller for driving a multiplexer according to claim 1, wherein said light receiving module is connected to an external synchronizing signal source through an optical fiber.

3. The firing controller for driving a multiplexer according to claim 1, wherein said light receiving module is formed by connecting a light receiver and a field effect transistor having level conversion and power amplification functions.

4. A trigger controller for driving a multiplexer as claimed in claim 3, wherein said light receiver is implemented by using HFBR2412 chip, and said field effect transistor is implemented by using 2SK2742 chip.

5. The trigger controller for driving a multiplexer according to claim 1, wherein said N MOSFET drivers each employ a TC4424 chip, said (N-1) integrated monostable flip-flops each employ a CD4098 chip, and said N power MOSFETs each employ an IRF740 chip.

6. The firing controller for driving a multi-way thyristor according to claim 1, wherein the first MOSFET driver and the first thyristor S₁A second MOSFET driver and a second thyristor S₂A third MOSFET driver and a third thyristor S₃… …, second nMOSFET driver and nth thyristor S_n… …, Nth MOSFET driver and Nth thyristor S_NAnd isolation transformers are adopted for electrical insulation and isolation.

7. The trigger controller for driving a multiplexer according to claim 1, wherein the first MOSFET driver is electrically isolated from the first power MOSFET, the second MOSFET driver is electrically isolated from the second power MOSFET, the third MOSFET driver is electrically isolated from the third power MOSFET, … …, the nth MOSFET driver is electrically isolated from the nth power MOSFET, … …, the nth power MOSFET driver is electrically isolated from the nth power MOSFET by isolation transformers.

8. The firing controller for driving a multiplexer thyristor according to claim 6 or 7, wherein the isolating transformer has a transformation ratio of 1: 1 magnetic core transformer.

9. The firing controller for driving a multi-way thyristor according to claim 1, wherein the pulsed weak current signal is of the order of 5V/10mA, the pulsed large current signal is of the order of 12V/2A, and the pulsed large current signal of higher intensity is of the order of 12V/10A; the time delay t₁、t₂、……、t_n-1、……、t_N-1Each of which is 50 μ s or more and 35ms or less.

10. A trigger controller for driving a multiplexer according to claim 1, wherein said trigger controller is encapsulated by a metal case, and the metal case is grounded.

Technical Field

The invention relates to a trigger controller, in particular to a trigger controller capable of driving a multi-channel thyristor, and belongs to the technical field of pulse power.

Background

The Thyristor (Thyristor) is called Silicon Controlled Rectifier (SCR) for short, and has the advantages of compact structure, fast medium recovery speed, no noise, accurate and controllable triggering, reduced on-state voltage, strong current capacity, high reliability, strong environmental adaptability and the like. On the premise of reasonably selecting the topological structure of the main circuit of the pulse power supply module and the parameters of the thyristor, the quality of the trigger system directly influences the discharge performance of the main circuit. Therefore, how to trigger the multi-way thyristor quickly and reliably is very important, and is one of the key technologies of the pulse power supply.

The thyristor is used as a main control switch of the primary energy storage charging system, and the purpose of the trigger control system is to provide an electric pulse signal which meets the trigger requirement for a gate pole. Therefore, the working performance of the trigger control system directly determines whether the primary energy storage charging system main control switch can be normally triggered to be conducted or not. In the field of pulse power, a thyristor generally works in a complex electromagnetic environment, and a trigger control system of the thyristor is easily interfered by the outside world and cannot normally operate.

The thyristor triggering modes mainly include three triggering circuit designs and researches [ J ] of a large-power thyristor in wulihong and lie vibration [ 2009 ]: (1) and in the transformer isolation triggering mode, the low-potential triggering pulse signal is isolated by the pulse transformer and then is transmitted to the gate level of the high-potential thyristor. The trigger pulse in the mode is transmitted by adopting a full cable, is seriously interfered by electromagnetic, is difficult to solve the output consistency of a multi-path pulse transformer and is not suitable for occasions where high-power thyristors are used in series-parallel connection; (2) and in the optical coupling isolation triggering mode, the triggering pulse is transmitted to the high-potential pulse amplifying circuit through the optical coupler, and the thyristor is triggered after the pulse is amplified. The mode can isolate the upper kilovolt high voltage, but is difficult to be qualified when the voltage is continuously increased, and the mode still adopts a full circuit to transmit pulses, so that the problem that the pulse transmission is interfered cannot be solved; (3) and (3) optical fiber isolation triggering, wherein an optical fiber transmission technology is adopted. The trigger pulse is coupled to the optical fiber through the electro-optical converter, then transmitted to the high potential pulse amplification unit through the optical fiber, and then output to the thyristor gate after being converted and amplified to form an electric signal. The mode solves the problem of high-voltage isolation, and simultaneously, because the optical fiber is adopted to transmit the pulse, the pulse is not subjected to electromagnetic interference in the transmission process, so that the external electromagnetic interference is reduced to a great extent. However, the scheme given in the text can only trigger one thyristor, and does not consider a trigger control scheme when multiple thyristors exist.

Disclosure of Invention

The technical problem to be solved by the invention is to solve the problems that the transformer isolation triggering mode and the optical coupling isolation triggering mode in the existing thyristor triggering mode adopt full circuit transmission pulse, are seriously interfered by electromagnetic, and are difficult to solve the problem of time consistency (or multi-path time sequence accuracy) of the driving output of a multi-path serial/parallel thyristor, and solve the problem that the optical fiber isolation triggering mode cannot trigger the multi-path thyristor, and provide a triggering controller for driving the multi-path thyristor. The application of the integrated monostable trigger is combined, the problem that the transformer isolation triggering mode is not suitable for the occasion where high-power thyristors are connected in series and in parallel for use is solved, thyristor gate-level triggering pulses with small dispersity and steep front edge can be generated, the thyristor gate-level triggering mode is a practical and effective triggering mode for driving the thyristor, and the integrated monostable trigger has the comprehensive advantages of low cost and good performance.

The invention adopts the following technical scheme:

a trigger controller for driving a multi-way thyristor can drive N (N is a positive integer and is more than or equal to 2) way thyristors and comprises a light receiving module, N Metal-Oxide-Semiconductor Field Effect transistors (MOSFET) drivers (namely a first MOSFET driver, a second MOSFET driver, … …, an nMOSFET driver, … … and an Nth MOSFET driver), N power MOSFETs (namely a first power MOSFET, a second power MOSFET, … …, an nth power MOSFET, … … and an Nth power MOSFET) and N-1 integrated monostable triggers (namely a first integrated monostable trigger, a second integrated monostable trigger, … …, an (N-1) integrated monostable trigger, … … and an (N-1) integrated monostable trigger). N is more than or equal to 2 and less than or equal to N, and N is a positive integer; the light receiving module is connected with an external synchronous signal source through optical fibers to avoid electromagnetic interference, and the connection of other elements is only common cable connection.

The light receiving module, the first MOSFET driver and the first power MOSFET form a first signal transmission channel; the light receiving module, the first integrated monostable trigger, the second MOSFET driver and the second power MOSFET form a second path of signal transmission channel; the light receiving module, the second integrated monostable trigger, the third MOSFET driver and the third power MOSFET form a third signal transmission channel; … …, respectively; the light receiving module, the (n-1) th integrated monostable trigger, the nth MOSFET driver and the nth power MOSFET form an nth signal transmission channel … …; the light receiving module, the (N-1) th integrated monostable trigger, the NMOSFET driver and the Nth power MOSFET form an Nth signal transmission channel. The first signal transmission channel is used for triggering a first thyristor S in an external pulse power system₁The second signal transmission channel is used for triggering a second thyristor S in the external pulse power system₂The third signal transmission channel is used for triggering a third thyristor S in the external pulse power system₃… …, the nth signal transmission channel is used to trigger the nth thyristor S in the external pulse power system_n… …, the Nth signal transmission channel is used to trigger the Nth thyristor S in the external pulse power system_NThe N signal transmission channels share the optical receiving module; n is more than or equal to 2 and less than or equal to N.

In the first signal transmission channel, the light receiving module is a light-electricity conversion module, is connected with the first MOSFET driver, is externally connected with a synchronous signal source (the light receiving module is connected with an external synchronous signal source through an optical fiber), receives optical pulse signals (the pulse width is tau, the wavelength is lambda and the optical power is W) generated by the synchronous signal source, converts the received optical pulse signals into a pulse weak current signal and transmits the pulse weak current signal to the first MOSFET driver; light receivingThe module generally adopts a low-power-consumption optical receiver combined with a field effect transistor with level conversion and power amplification functions (the signal current from the optical receiver is small, the driving capability is weak, and a MOSFET driver cannot be directly driven, so that level conversion and power amplification are required); the first MOSFET driver is connected with the light receiving module and the first power MOSFET, amplifies the pulse weak current signal received from the light receiving module into a pulse large current signal and sends the pulse large current signal to the first power MOSFET; first power MOSFET and first thyristor S in first MOSFET driver and external pulsed power system₁The output end of the first power MOSFET is used as the output end of the first signal transmission channel, and the pulse high-current signal with higher intensity is sent to a first thyristor S in an external pulse power system₁For triggering the first thyristor S₁。

The first integrated monostable trigger in the second signal transmission channel is connected with the light receiving module and the second MOSFET driver, is an element with time delay function, delays the pulse weak current signal received from the light receiving module, and outputs the pulse weak current signal with time delay t relative to the first signal transmission channel to the second MOSFET driver₁(t₁Continuously adjustable, and t is more than or equal to 50 mu s₁Less than or equal to 35ms) pulse weak current signals; the second MOSFET driver is connected with the first integrated monostable trigger and the second power MOSFET and receives the signal with time delay t from the first integrated monostable trigger₁Amplifying the pulsed weak current signal to have a time delay of t₁Pulsing a high current signal and will have a time delay of t₁Sending the pulse large-current signal to a second power MOSFET; second power MOSFET and second MOSFET driver and second thyristor S in external pulsed power system₂Connected to receive the signal from the second MOSFET driver with a time delay t₁Converting the pulsed high current signal to a higher strength signal with a time delay of t₁The output end of the second power MOSFET is used as the output end of the second signal transmission channel, so that the signal with higher intensity is transmittedWith a time delay of t₁The pulse heavy current signal is sent to a second thyristor S in an external pulse power system₂For triggering the second thyristor S₂。

The second integrated monostable trigger in the third signal transmission channel is connected with the light receiving module and the third MOSFET driver, is completely the same as the first integrated monostable trigger, delays the pulse weak current signal received from the light receiving module, and outputs a delay t to the third MOSFET driver relative to the first signal transmission channel₂(t₂Continuously adjustable, and t is more than or equal to 50 mu s₂Less than or equal to 35ms) pulse weak current signals; the third MOSFET driver is connected with the second integrated monostable trigger and the third power MOSFET and receives the signal with time delay t from the second integrated monostable trigger₂Amplifying the pulsed weak current signal to have a time delay of t₂Pulsing a high current signal and will have a time delay of t₂Sending the pulse large-current signal to a third power MOSFET; third power MOSFET and third MOSFET driver and third thyristor S in external pulsed power system₃Connected to receive the signal from the third MOSFET driver with a time delay t₂Converting the pulsed high current signal to a higher strength signal with a time delay of t₂The output end of the third power MOSFET is used as the output end of the third signal transmission channel, and the higher-intensity signal with the time delay of t₂Sending the pulse large current signal to a third thyristor S in an external pulse power system₃For triggering the third thyristor S₃。

According to the same connection mode with the third signal transmission channel, the output end of the nth power MOSFET is used as the output end of the nth signal transmission channel, and the time delay t relative to the first signal transmission channel is set_n-1(t_n-1Continuously adjustable, and t is more than or equal to 50 mu s_n-1Less than or equal to 35ms) pulse large current signal is sent to the nth thyristor S in the external pulse power system_nFor triggering the n-th thyristor S_n(ii) a … …, respectively; the output end of the Nth power MOSFET is used as the output end of the Nth signal transmission channel to transmit the relative first signalThe track having a time delay of t_N-1(t_N-1Continuously adjustable, and t is more than or equal to 50 mu s_N-1Less than or equal to 35ms) pulse large current signal is sent to the Nth thyristor S in the external pulse power system_NFor triggering the Nth thyristor S_N。

Generally, the output end of the trigger controller must be connected with the gate level of the thyristor, and the potential of the gate level of the thyristor is far higher than the output pulse potential of the trigger controller, so that an isolation element is generally added between weak current (trigger controller) and strong current (thyristor) to prevent high voltage (kV magnitude) signals on the gate level of the thyristor from entering the trigger controller through the signal output end of the trigger controller. Usually in the first MOSFET driver and the first thyristor S of the trigger controller₁A second MOSFET driver and a second thyristor S₂A third MOSFET driver and a third thyristor S₃… …, nth MOSFET driver and nth thyristor S_n… …, Nth MOSFET driver and Nth thyristor S_NCarry out electrical insulation through isolation transformer between and keep apart, isolation transformer is magnetic core transformer, and the transformation ratio is 1: 1.

further, in order to prevent the pulse large current signal with higher intensity output by the power MOSFET from entering the MOSFET driver through the output end of the MOSFET driver and affecting the preceding stage circuit, isolation transformers may be used for electrical insulation isolation between the first MOSFET driver and the first power MOSFET, between the second MOSFET driver and the second power MOSFET, between the third MOSFET driver and the third power MOSFET, … …, between the nth MOSFET driver and the nth power MOSFET, … …, between the nth MOSFET driver and the nth power MOSFET, the isolation transformers are magnetic core transformers, and the transformation ratio is 1: 1.

in order to reduce the interference of the electromagnetic radiation in the space to the trigger controller, the trigger controller may be packaged by a metal shell, and the metal shell may be grounded.

The working process of the invention is as follows:

in the first step, the optical receiving module receives an optical pulse signal generated by an external synchronous signal source, converts the optical pulse signal into a pulse weak current signal and sends the pulse weak current signal to the first MOSFET driver in the first signal transmission channel and the first, second, … …, nth, … …, and first, second, … …, (N-1), … …, and (N-1) integrated monostable flip-flops in the second, third, … …, nth, … …, and nth signal transmission channels:

1.1 an optical receiver in the optical receiving module receives an optical pulse signal generated by an external synchronous signal source and converts the optical pulse signal into an electric pulse signal;

1.2 the optical receiver sends the converted electric pulse signal to a field effect transistor in the optical receiving module for level conversion and power amplification and outputs a pulse weak current signal;

1.3 the light receiving module sends the pulse weak current signal to a first MOSFET driver in a first signal transmission channel;

meanwhile, the light receiving module sends the pulse weak current signal to a first integrated monostable trigger in a second path of signal transmission channel;

meanwhile, the light receiving module sends the pulse weak current signal to a second integrated monostable trigger in a third signal transmission channel; … …, respectively; meanwhile, the light receiving module sends the pulse weak current signal to an (n-1) th integrated monostable trigger in the nth signal transmission channel; … …, respectively;

meanwhile, the light receiving module sends the pulse weak current signal to an (N-1) th integrated monostable trigger in an Nth signal transmission channel.

Secondly, a first MOSFET driver in the first signal transmission channel converts the pulse weak current signal into a pulse large current signal and sends the pulse large current signal to a first power MOSFET; in the second, third, … …, nth, … … and nth signal transmission channels, the first, second, … …, (N-1), … … and (N-1) integrated monostable flip-flops delay the pulse weak current signal and send the signal to the second, third, … …, nth, … … and nth MOSFET drivers;

2.1 in the first path of signal transmission channel, a first MOSFET driver receives a pulse weak current signal sent by a light receiving module, amplifies the signal, converts the signal into a pulse large current signal, and sends the pulse large current signal to a first power MOSFET;

2.2 the first, second, … …, (N-1), (… …), (N-1) integrated monostable flip-flops delay the pulse weak current signal:

2.2.1 in the second path of signal transmission channel, the first integrated monostable trigger receives the pulse weak current signal sent by the optical receiving module, delays the signal, and has a time delay t relative to the first path of signal transmission channel₁The pulse weak current signal is sent to a second MOSFET driver;

meanwhile, in the third signal transmission channel, the second integrated monostable trigger receives a pulse weak current signal sent by the light receiving module, delays the signal and has a time delay t relative to the first signal transmission channel₂The pulsed weak current signal of (a) is sent to a third MOSFET driver;

meanwhile, the (n-1) th integrated monostable trigger in the nth signal transmission channel receives a pulse weak current signal sent by the optical receiving module, delays the signal and has a time delay t relative to the first signal transmission channel_n-1The pulse weak current signal is sent to the nth MOSFET driver; … …, respectively;

meanwhile, in the Nth signal transmission channel, the (N-1) th integrated monostable trigger receives a pulse weak current signal sent by the optical receiving module, delays the signal and has a time delay t relative to the first signal transmission channel_N-1Sending the pulse weak current signal to an Nth MOSFET driver;

thirdly, the first power MOSFET in the first signal transmission channel converts the pulse heavy current signal into a pulse heavy current signal with higher intensity, and triggers the first thyristor S₁(ii) a In the second, third, … …, nth, … … and nth signal transmission channels, the second, third, … …, nth, … … and nth MOSFET drivers will have time delay t relative to the first signal transmission channel₁、t₂、……、t_n-1、……、t_N-1The pulse weak current signal is converted into a signal transmission channel with time delay t relative to the first path of signal transmission channel₁、t₂、……、t_n-1、……、t_N-1A pulsed high current signal of, andwill have a time delay t with respect to the first signal transmission channel₁、t₂、……、t_n-1、……、t_N-1The pulse large current signal is transmitted to the second, third, … …, nth, … … and nth power MOSFET:

3.1 in the first signal transmission channel, the first power MOSFET receives the pulse heavy current signal generated by the first MOSFET driver, amplifies the pulse heavy current signal, converts the signal into a pulse heavy current signal with higher intensity, and sends the pulse heavy current signal with higher intensity to the first thyristor S in the external pulse power system₁A first thyristor S₁Is triggered;

3.2 in the second path of signal transmission channel, the second MOSFET driver receives the signal transmission channel generated by the first integrated monostable trigger and has time delay t relative to the first path of signal transmission channel₁The pulse weak current signal is amplified and converted into a signal transmission channel with time delay t relative to the first path of signal transmission channel₁The pulse large current signal has time delay t relative to the first signal transmission channel₁The pulse large current signal is sent to a second power MOSFET;

meanwhile, in the third signal transmission channel, the third MOSFET driver receives the signal transmission channel generated by the second integrated monostable trigger and has time delay t relative to the first signal transmission channel₂The pulse weak current signal is amplified and converted into a signal transmission channel with time delay t relative to the first path of signal transmission channel₂The pulse large current signal has time delay t relative to the first signal transmission channel₂The pulse large current signal is sent to a third power MOSFET;

meanwhile, in the nth signal transmission channel, the nth MOSFET driver receives the signal transmission channel generated by the (n-1) th integrated monostable trigger and has time delay t relative to the first signal transmission channel_n-1The pulse weak current signal is amplified and converted into a signal transmission channel with time delay t relative to the first path of signal transmission channel_n-1The pulse large current signal has time delay t relative to the first signal transmission channel_n-1The pulse large current signal is sent to the nth power MOSFET; … …, respectively;

meanwhile, in the Nth signal transmission channel, the Nth MOSFET driver receives the signal transmission channel generated by the (N-1) th integrated monostable trigger and has time delay t relative to the first signal transmission channel_N-1The pulse weak current signal is amplified and converted into a signal transmission channel with time delay t relative to the first path of signal transmission channel_N-1The pulse heavy current signal has time delay t relative to the first signal transmission channel through an isolation transformer_N-1Sending the pulse large current signal to the Nth power MOSFET;

fourthly, in the second, third and … … th signal transmission channels, the second, third, … … th, N, … … th and N power MOSFETs have time delay t relative to the first signal transmission channel₁、t₂、……、t_n-1、……、t_N-1The pulse heavy current signal is converted into a signal transmission channel with time delay t relative to the first path of signal transmission channel₁、t₂、……、t_n-1、……、t_N-1The second, third, … …, nth, … … and nth thyristors S are triggered by the higher intensity of the pulse high current₂、S₃、……、S_n、……、S_N；

4.1 in the second path of signal transmission channel, the second power MOSFET receives the signal transmission channel generated by the second MOSFET driver and has time delay t relative to the first path of signal transmission channel₁The pulse large current signal has time delay t relative to the first signal transmission channel₁The pulse heavy current signal is amplified and converted into a signal transmission channel with higher strength and time delay of t relative to the first path of signal transmission channel₁The pulse large current signal is transmitted by the first path of signal transmission channel with higher strength and time delay of t₁Is sent to a second thyristor S in an external pulse power system₂Second thyristor S₂Is triggered relative to the first thyristor S₁Is t₁；

Meanwhile, in the third signal transmission channel, the third power MOSFET receives the signal transmission channel generated by the third MOSFET driver and has time delay t relative to the first signal transmission channel₂Pulsed high current ofA signal with time delay t relative to the first signal transmission channel₂The pulse heavy current signal is amplified and converted into a signal transmission channel with higher strength and time delay of t relative to the first path of signal transmission channel₂The pulse large current signal is transmitted by the first path of signal transmission channel with higher strength and time delay of t₂The pulse large current signal is sent to a third thyristor S in an external pulse power system₃The third thyristor S₃Is triggered relative to the first thyristor S₁Is t₂；

Meanwhile, in the nth signal transmission channel, the nth power MOSFET receives the signal transmission channel generated by the nth MOSFET driver and has time delay t relative to the first signal transmission channel_n-1The pulse large current signal has time delay t relative to the first signal transmission channel_n-1The pulse heavy current signal is amplified and converted into a signal transmission channel with higher strength and time delay of t relative to the first path of signal transmission channel_n-1The pulse large current signal is transmitted by the first path of signal transmission channel with higher strength and time delay of t_n-1Is sent to the nth thyristor S in an external pulse power system_nN th thyristor S_nIs triggered relative to the first thyristor S₁Is t_n-1；……；

Meanwhile, in the Nth signal transmission channel, the Nth power MOSFET receives the signal transmission channel generated by the Nth MOSFET driver and has time delay t relative to the first signal transmission channel_N-1The pulse large current signal has time delay t relative to the first signal transmission channel_N-1The pulse heavy current signal is amplified and converted into a signal transmission channel with higher strength and time delay of t relative to the first path of signal transmission channel_N-1The pulse large current signal is transmitted by the first path of signal transmission channel with higher strength and time delay of t_N-1The pulse large current signal is sent to the Nth thyristor S in the external pulse power system_NNth thyristor S_NIs triggered relative to the first thyristor S₁Is t_N-1。

Compared with the prior art, the invention can achieve the following technical effects:

1. according to the invention, (N-1) integrated monostable triggers are introduced, N thyristors in series and parallel connection can be triggered simultaneously, meanwhile, the time delay of the (N-1) integrated monostable triggers is adjusted, the defect that the output consistency of a multi-path pulse transformer in the existing transformer isolation triggering mode is difficult to solve can be made up, and the accurate control of the N thyristors is realized;

2. the N signal transmission channels are independent and only share the optical receiving module, so that the N signal transmission channels independently transmit pulses, the N signal transmission channels are not interfered with each other, and the stability of the trigger controller is improved;

3. the invention adopts the protection measure of optical fiber isolation, adopts optical fiber to replace electric wire to transmit signals between the light receiving module and the external synchronous signal source, solves the problem that electromagnetic radiation is fed into interference signals in an electronic element in an electric coupling mode, can effectively prevent misoperation caused by parameter drift of circuit elements and improves the anti-interference capability of the system;

4. the invention adopts the protective measure of transformer isolation, and utilizes the isolation transformer to carry out electric insulation isolation between the gate level of the thyristor and the trigger controller, thereby preventing high voltage (kV level) signals on the gate level of the thyristor from entering the trigger controller through the signal output end of the trigger controller to cause element damage;

5. the invention is packaged by the metal shell outside the trigger controller, and the metal shell is grounded, thereby effectively reducing the interference of space electromagnetic radiation to the trigger controller.

Drawings

Fig. 1 is a general logic structure diagram of a trigger controller for driving a multi-way thyristor according to the present invention;

FIG. 2 is an experimental output waveform of an embodiment of the present invention;

FIG. 3 is an expanded view of the first signal of FIG. 2 on a time axis;

FIG. 4 is an expanded view of the second path signal of FIG. 2 on a time axis;

fig. 5 is an expanded view of the third signal in fig. 2 on a time axis.

Detailed Description

The invention will be further described with reference to the accompanying drawings.

Fig. 1 is a logical structure diagram of a trigger controller for driving a multi-way thyristor according to the present invention. The invention can drive an N (N is more than or equal to 2) way thyristor, which consists of a light receiving module, N MOSFET drivers (namely a first MOSFET driver, a second MOSFET driver, … … and an NMOSFET driver), N power MOSFETs (namely a first power MOSFET, a second power MOSFET, … … and an Nth power MOSFET) and (N-1) integrated monostable triggers (namely a first integrated monostable trigger, a second integrated monostable trigger, … … and an (N-1) integrated monostable trigger). The light receiving module is connected with an external synchronous signal source through an optical fiber. The light receiving module, the first MOSFET driver and the first power MOSFET form a first signal transmission channel; the light receiving module, the first integrated monostable trigger, the second MOSFET driver and the second power MOSFET form a second path of signal transmission channel; the light receiving module, the second integrated monostable trigger, the third MOSFET driver and the third power MOSFET form a third signal transmission channel; … …, respectively; the light receiving module, the (n-1) th integrated monostable trigger, the nth MOSFET driver and the nth power MOSFET form an nth signal transmission channel; … …, respectively; the light receiving module, the (N-1) th integrated monostable trigger, the Nth MOSFET driver and the Nth power MOSFET form an Nth signal transmission channel. The first signal transmission channel is used for triggering a first thyristor S in an external pulse power system₁The second signal transmission channel is used for triggering a second thyristor S in the external pulse power system₂… …, the nth signal transmission channel is used to trigger the third thyristor S in the external pulse power system_n… …, the Nth signal transmission channel is used to trigger the Nth thyristor S in the external pulse power system_NThe N signal transmission channels share the optical receiving module; in the first signal transmission channel, the light receiving module is a light-electricity conversion module, is connected with the first MOSFET driver, is externally connected with a synchronous signal source (the light receiving module is connected with an external synchronous signal source through an optical fiber), and receives an optical pulse signal generated by the synchronous signal sourceThe signal (pulse width is tau, wavelength is lambda, optical power is W) and converts the received optical pulse signal into a pulse weak current signal (5V/10mA magnitude) and transmits the pulse weak current signal to the first MOSFET driver; the light receiving module is formed by connecting a light receiver with low power consumption and a field effect transistor with level conversion and power amplification functions (the signal current from the light receiver is small, the driving capability is weak, and a MOSFET driver cannot be directly driven, so that level conversion and power amplification are required); the first MOSFET driver is connected with the light receiving module and the first power MOSFET, amplifies a pulse weak current signal (5V/10mA magnitude) received from the light receiving module into a pulse large current signal (12V/2A magnitude) and sends the pulse large current signal to the first power MOSFET; first power MOSFET and first thyristor S in first MOSFET driver and external pulsed power system₁The output end of the first power MOSFET is used as the output end of the first signal transmission channel, and the higher-strength pulse large-current signal (12V/10A magnitude) is sent to a first thyristor S in an external pulse power system₁For triggering the first thyristor S₁。

The first integrated monostable trigger in the second signal transmission channel is connected with the light receiving module and the second MOSFET driver, is an element with a time delay function, delays the pulse weak current signal (5V/10mA magnitude) received from the light receiving module, and outputs a time delay t relative to the first signal transmission channel to the second MOSFET driver₁(t₁Continuously adjustable, and t is more than or equal to 50 mu s₁Less than or equal to 35ms) pulse weak current signals (5V/10mA magnitude); the second MOSFET driver is connected with the first integrated monostable trigger and the second power MOSFET and receives the signal with time delay t from the first integrated monostable trigger₁Is amplified to have a time delay of t₁Pulsed high current signals (of the order of 12V/2A) and will have a time delay of t₁A pulse high-current signal (in the order of 12V/2A) is sent to a second power MOSFET; second power MOSFET and second MOSFET driver and externalSecond thyristor S in partial pulse power system₂Connected to receive the signal from the second MOSFET driver with a time delay t₁Is converted into a higher-intensity signal with time delay t (of the order of 12V/2A)₁The output end of the second power MOSFET is used as the output end of the second signal transmission channel, and the higher intensity signal with time delay of t is used as the output end of the second signal transmission channel₁A pulse high current signal (12V/10A magnitude) is sent to a second thyristor S in an external pulse power system₂For triggering the second thyristor S₂. The second integrated monostable trigger in the nth signal transmission channel is connected with the light receiving module and the nth MOSFET driver, the (n-1) th integrated monostable trigger is completely the same as the first integrated monostable trigger, and delays the pulse weak current signal (5V/10mA magnitude) received from the light receiving module, and outputs a delay t to the second nMOSFET driver relative to the first signal transmission channel_n-1(t_n-1Continuously adjustable, and t is more than or equal to 50 mu s_n-1Less than or equal to 35ms) pulse weak current signals (5V/10mA magnitude); the nth MOSFET driver is connected with the (n-1) th integrated monostable trigger and the third power MOSFET and receives the signal from the second integrated monostable trigger with time delay t_n-1Is amplified to have a time delay of t_n-1Pulsed high current signals (of the order of 12V/2A) and will have a time delay of t_n-1Sending a pulse large current signal to an nth power MOSFET; nth power MOSFET and nth thyristor S in nth MOSFET driver and external pulse power system_nConnected to receive the signal from the nth MOSFET driver with a time delay t_n-1Is converted into a higher-intensity signal with time delay t (of the order of 12V/2A)_n-1A pulse large current signal (12V/10A magnitude), the output end of the nth power MOSFET is used as the output end of the nth signal transmission channel, and the higher intensity signal with the time delay of t is transmitted_n-1Sending the pulse large current signal to the nth thyristor S in the external pulse power system_nFor triggering the n-th thyristor S_n. The output end of the Nth power MOSFET is used as the output of the Nth signal transmission channel according to the same connection mode as the Nth signal transmission channelEnd, having time delay t relative to the first signal transmission channel_N-1(t_N-1Continuously adjustable, and t is more than or equal to 50 mu s_N-1Less than or equal to 35ms) pulse large current signal (12V/10A magnitude) is sent to the Nth thyristor S in the external pulse power system_NFor triggering the Nth thyristor S_N。

The national defense science and technology university designs a trigger controller (namely N is 3) capable of driving a 3-way thyristor (named as embodiment 1), a light receiving module is formed by connecting a light receiver HFBR2412 chip with low power consumption and a field effect transistor 2SK2742 chip with level conversion and power amplification functions, the light receiver HFBR2412 chip is connected with an external synchronous signal source through an optical fiber, and parameters of light pulses generated by the external synchronous signal source are received as follows: pulse width tau is 40 mus, wavelength lambda is 820nm (namely infrared light pulse signal), and optical power W is-15 dBm; 3 MOSFET drivers use 3 TC4424 chips, 3 power MOSFETs use 3 IRF740 chips, 2 integrated monostable flip-flops use 2 CD4098 chips.

In order to prevent high voltage (kV magnitude) signals on the thyristor gate level from entering the trigger controller through the signal output end of the trigger controller, a first MOSFET driver and a first thyristor S in the trigger controller₁A second MOSFET driver and a second thyristor S₂A third MOSFET driver and a third thyristor S₃Carry out electrical insulation through isolation transformer between and keep apart, isolation transformer is magnetic core transformer, and the transformation ratio is 1: 1; simultaneously, in order to prevent that the output of power MOSFET's the pulse heavy current signal of higher intensity from getting into the MOSFET driver through the output of MOSFET driver and causing the influence to preceding stage circuit, adopt isolation transformer to carry out the electrical insulation isolation between first MOSFET driver and first power MOSFET, second MOSFET driver and second power MOSFET, third MOSFET driver and third power MOSFET, isolation transformer is the magnetic core transformer, and the transformation ratio is 1: 1; further, in order to reduce the interference of the electromagnetic radiation in the space to the trigger controller, the trigger controller is packaged by a metal shell, and the metal shell is grounded.

To verify the characteristics of example 1, experimental verification was performed according to the designFig. 2 is a typical output waveform of embodiment 1, a high-voltage probe is respectively placed at output ends of a first power MOSFET, a second power MOSFET, and a third power MOSFET, an external synchronous signal source is controlled to send optical pulse signals (pulse width τ is 40 μ s, wavelength λ is 820nm (i.e. infrared light pulse signal), optical power W is-15 dBm) to a light receiving module, the output signals of the first power MOSFET, the second power MOSFET, and the third power MOSFET are fed into an oscilloscope, a first path of signal, a second path of signal, and a third path of signal are respectively obtained, as shown in fig. 2, the horizontal axis is a time axis, the time base of the oscilloscope is 0.5ms/div, the time 0 is the time when the first power MOSFET outputs a high-intensity pulse current, the vertical axis is a voltage value, and for convenience of reading, the range of the vertical axis of the first signal is set to-60V-24V, the range of the vertical axis of the second signal is set to-36V, and the range of the vertical axis of the third signal is set to-24V-60V; from fig. 2, the time delay between the first signal and the second signal is 462.8 μ s (i.e. t)₁462.8 mus), the time delay between the second and third signals is 584.9 mus (i.e., t)₂584.9 mus), in fact, the two integrated monostable flip-flops of the invention use two CD4098 chips, and the time delay between the two signals and the first signal is continuously adjustable between 50 mus and 35 ms.

FIG. 3 is a developed waveform of the first signal in FIG. 2 on a time axis (-45 μ s-75 μ s), the voltage amplitude of the first signal is 12V, and the pulse width is 31.9 μ s; FIG. 4 is a developed waveform of the second path of signal in FIG. 2 on a time axis (420 μ s-540 μ s), the voltage amplitude of the second path of signal is 12.1V, and the pulse width is 37.7 μ s; fig. 5 is a developed waveform of the third signal in fig. 2 on a time axis (1.00ms-1.12ms), the voltage amplitude of the third signal is 11.9V, and the pulse width is 33.9 μ s. It can be seen that the accurate control of the three thyristors can be realized based on embodiment 1 of the invention, which proves that the invention can be applied to a pulse power system adopting a plurality of high-power thyristors in series-parallel connection.

The above description is only exemplary of the present invention and should not be taken as limiting the invention, as any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.