阅读说明：本技术 纠错电路及其操作方法 (Error correction circuit and method of operating the same ) 是由 金大成 姜淳荣 于 2019-06-14 设计创作，主要内容包括：本文提供的可以是纠错电路及其操作方法。一种操作纠错电路的方法可以包括：将初始符号作为变量节点值分配给变量节点；在每次迭代开始时基于分配给变量节点的初始符号来初始化与变量节点相对应的候选符号的第一可靠性值；基于从耦合到变量节点的校验节点接收的通信来分别更新候选符号的第一可靠性值，所述候选符号具有更新的第一可靠性值；以及当候选符号之一的更新的第一可靠性值等于或大于第一阈值时，将变量节点值调节为候选符号之一。(Provided herein may be an error correction circuit and a method of operating the same. A method of operating an error correction circuit may include: allocating the initial symbol as a variable node value to a variable node; initializing a first reliability value of a candidate symbol corresponding to the variable node at the start of each iteration based on an initial symbol assigned to the variable node; updating first reliability values of candidate symbols, respectively, based on communications received from check nodes coupled to variable nodes, the candidate symbols having updated first reliability values; and adjusting the variable node value to one of the candidate symbols when the updated first reliability value of the one of the candidate symbols is equal to or greater than the first threshold value.)

1. A method of operating an error correction circuit for performing error correction decoding based on an iterative decoding scheme using a non-binary low density parity check (NB-LDPC) code, the method comprising:

allocating the initial symbol as a variable node value to a variable node;

initializing, at the beginning of each iteration, a first reliability value for a candidate symbol corresponding to the variable node based on the initial symbol assigned to the variable node;

updating the first reliability values of the candidate symbols, respectively, based on communications received from check nodes coupled to the variable nodes, the candidate symbols having updated first reliability values; and

adjusting the variable node value to one of the candidate symbols when an updated first reliability value of the one of the candidate symbols is equal to or greater than a first threshold value.

2. The method of claim 1, wherein initializing the first reliability value comprises: initializing the first reliability values of the candidate symbols, respectively, based on hamming distances between the initial symbols allocated to the variable nodes and the candidate symbols.

3. The method of claim 2, wherein a shorter hamming distance between the initial symbol and a certain candidate symbol initializes a first reliability value of the certain candidate symbol to a higher value.

4. The method of claim 1, wherein initializing the first reliability value comprises: initializing the first reliability value for each of the candidate symbols based on the number of iterations.

5. The method of claim 4, wherein a first reliability value of a candidate symbol is initialized to a higher value as the number of iterations increases.

6. The method of claim 1, further comprising: performing syndrome checking using the adjusted variable node values.

7. The method of claim 6, wherein initializing the first reliability value comprises: initializing the first reliability value for an i +1 th iteration based on a number of Unsatisfied Check Nodes (UCNs) from the i-th iteration, where i is a natural number.

8. The method of claim 7, wherein the greater the number of UCNs, the higher value is initialized to a first reliability value of a certain candidate symbol for an i +1 th iteration.

9. The method of claim 6, further comprising:

changing the first threshold based on a number of UCNs.

10. The method of claim 9, wherein changing the first threshold comprises:

changing the first threshold to a higher value the greater the number of UCNs.

11. The method of claim 1, further comprising: changing the first threshold based on the number of iterations.

12. The method of claim 11, wherein changing the first threshold comprises:

changing the first threshold to a higher value as the number of iterations increases.

13. The method of claim 1, further comprising:

setting the first threshold based on a degree of the variable node.

14. The method of claim 13, wherein setting the first threshold comprises:

setting the first threshold to a higher value the higher the degree of the variable node is.

15. The method of claim 1, further comprising:

determining whether there is a candidate symbol having an updated first reliability value equal to or greater than a second threshold value, which is less than the first threshold value, among the candidate symbols when there is no candidate symbol whose updated first reliability value is equal to or greater than the first threshold value;

setting a second reliability value in the variable node based on the determination; and

adjusting the variable node value when a candidate symbol among the candidate symbols has an updated first reliability value in a next iteration that is equal to or greater than the second threshold value and less than the first threshold value.

16. The method of claim 15, further comprising: adjusting the variable node value to a candidate symbol having the first reliability value in the next iteration equal to or greater than the second threshold and less than the first threshold.

17. The method of claim 1, further comprising:

determining whether there is any candidate symbol whose updated first reliability value is equal to or greater than a second threshold value, which is less than the first threshold value, among the candidate symbols when there is no candidate symbol whose updated first reliability value is equal to or greater than the first threshold value;

increasing a second reliability value corresponding to the variable node by a first set value based on the determination;

determining whether there is any candidate symbol whose updated first reliability value is equal to or greater than a third threshold value, which is less than the second threshold value, among the candidate symbols when there is no candidate symbol whose updated first reliability value is equal to or greater than the second threshold value;

increasing the second reliability value corresponding to the variable node by a second set value based on the determination; and

adjusting the variable node value when the increased second reliability value is equal to or greater than a fourth threshold value.

18. The method of claim 17, further comprising: adjusting the variable node value to a candidate symbol having a first reliability value less than the first threshold and equal to or greater than the second threshold.

19. The method of claim 17, further comprising: adjusting the variable node value to a candidate symbol having a first reliability value less than the second threshold and equal to or greater than the third threshold.

20. The method of claim 17, wherein the second setting is less than the first setting.

21. An error correction circuit for performing error correction decoding based on an iterative decoding scheme using a non-binary low density parity check (NB-LDPC) code, comprising:

a symbol configuration circuit configured to configure an initial symbol to be allocated to a variable node as a variable node value;

a reliability value initialization circuit configured to initialize a first reliability value of a candidate symbol corresponding to the variable node based on the initial symbol allocated to the variable node; and

symbol correction circuitry configured to update the first reliability values of the candidate symbols, respectively, based on communications received from check nodes coupled to the variable nodes, the candidate symbols having updated first reliability values, and to adjust one of the candidate symbols to the one of the candidate symbols based on a comparison of the updated first reliability value of the one of the candidate symbols to a first threshold value.

22. The error correction circuit of claim 21, wherein the reliability value initialization circuit initializes the first reliability value for each of the candidate symbols based on a hamming distance between the initial symbol assigned to the variable node and the corresponding candidate symbol.

23. The error correction circuit of claim 21, wherein the shorter the hamming distance between the initial symbol and a certain candidate symbol, the reliability value initialization circuit initializes the first reliability value of the certain candidate symbol to a higher value.

24. The error correction circuit of claim 21 wherein the reliability value initialization circuit initializes the first reliability value for each of the candidate symbols based on a number of iterations.

25. The error correction circuit of claim 24, wherein the reliability value initialization unit initializes the first reliability value of a certain candidate symbol to a higher value as the number of iterations increases.

26. The error correction circuit of claim 21, further comprising:

syndrome check circuitry configured to perform syndrome checks using the adjusted variable node values.

27. The error correction circuit of claim 26, wherein the reliability value initialization circuit is configured to initialize the first reliability value for an i +1 th iteration based on a number of Unsatisfied Check Nodes (UCNs) from the i th iteration.

28. The error correction circuit of claim 27, wherein the reliability value initialization circuit is configured to: the larger the number of UCNs, the higher the value of the first reliability of a certain candidate symbol is initialized.

29. The error correction circuit of claim 26, further comprising:

a threshold setting circuit configured to change the first threshold based on a number of UCNs.

30. The error correction circuit of claim 29, wherein the threshold setting circuit is configured to: changing the first threshold to a higher value the greater the number of UCNs.

31. The error correction circuit of claim 21, further comprising:

a threshold setting circuit configured to change the first threshold based on a number of iterations.

32. The error correction circuit of claim 31, wherein the threshold setting circuit changes the first threshold to a higher value as the number of iterations increases.

33. The error correction circuit of claim 21, wherein the threshold setting circuit sets the first threshold based on a degree of the variable node.

34. The error correction circuit of claim 33, wherein the threshold setting circuit sets the first threshold to a higher value the higher the degree of the variable node.

35. The error correction circuit of claim 21, wherein the symbol correction unit is configured to:

determining whether there is a candidate symbol having an updated first reliability value equal to or greater than a second threshold value, which is less than the first threshold value, among the candidate symbols when there is no candidate symbol whose updated first reliability value is equal to or greater than the first threshold value;

setting a second reliability value in the variable node based on the determination; and

adjusting the variable node value when a candidate symbol among the candidate symbols has an updated first reliability value in a next iteration that is equal to or greater than the second threshold value and less than the first threshold value.

36. The error correction circuit of claim 35, wherein the symbol correction circuit adjusts the variable node value to a candidate symbol having the first reliability value in the next iteration equal to or greater than the second threshold and less than the first threshold.

37. The error correction circuit of claim 21, wherein the symbol correction circuit is configured to:

determining whether there is a candidate symbol whose updated first reliability value is equal to or greater than a second threshold value, which is less than the first threshold value, among the candidate symbols when there is no candidate symbol whose updated first reliability value is equal to or greater than the first threshold value;

increasing a second reliability value corresponding to the variable node by a first set value based on the determination;

determining whether there is a candidate symbol whose updated first reliability value is equal to or greater than a third threshold value, which is less than the second threshold value, among the candidate symbols when there is no candidate symbol whose updated first reliability value is equal to or greater than the second threshold value;

increasing the second reliability value corresponding to the variable node by a second set value based on the determination; and

adjusting the variable node value when the increased second reliability value is equal to or greater than a fourth threshold value.

38. The error correction circuit of claim 37, wherein the symbol correction circuit is configured to adjust the variable node value to a candidate symbol having a first reliability value less than the first threshold and equal to or greater than the second threshold.

39. The error correction circuit of claim 37, wherein the symbol correction circuit is configured to adjust the variable node value to a candidate symbol having a first reliability value less than the second threshold and equal to or greater than the third threshold.

40. The error correction circuit of claim 37, wherein the second setting value is less than the first setting value.

Technical Field

Techniques and implementations disclosed in this patent document relate generally to error correction circuits and methods of operating the same, including error correction circuits using non-binary low density parity check (NB-LDPC) codes and methods of operating the same.

Background

The memory system may include a storage medium that temporarily or permanently stores data therein. During various operations of the memory system including writing, reading, transferring or processing, any data errors or any data corruption may occur due to interference between adjacent memory cells. To control data errors and/or data corruption and ensure the reliability of data, memory systems may use error correction techniques such as error correction coding and decoding. Error correction techniques may be implemented in hardware and/or software. For example, the circuitry for error correction may perform error correction encoding and decoding in the memory system using error correction codes.

Among available error correction code technologies, Low Density Parity Check (LDPC) codes have been widely used in communication and other systems.

Disclosure of Invention

Various embodiments of the disclosed technology relate to an error correction circuit for performing error correction decoding using a non-binary LDPC (NB-LDPC) code and a method of operating the same.

Embodiments of the disclosed technology may provide a method of operating an error correction circuit that performs error correction decoding based on an iterative decoding scheme using a non-binary low density parity check (NB-LDPC) code. The method may include assigning an initial symbol to a variable node as a variable node value; initializing a first reliability value of a candidate symbol corresponding to the variable node at the start of each iteration based on an initial symbol assigned to the variable node; updating first reliability values of candidate symbols, respectively, based on communications received from check nodes coupled to the variable nodes, the candidate symbols having updated first reliability values; and adjusting the variable node value to one of the candidate symbols when the updated first reliability value of the one of the candidate symbols is equal to or greater than the first threshold value.

Embodiments of the disclosed technology may provide an error correction circuit for performing error correction decoding based on an iterative decoding scheme using a non-binary low density parity check (NB-LDPC) code. The error correction circuit may include: a symbol configuration circuit configured to configure an initial symbol to be assigned to a variable node as a variable node value; a reliability value initialization circuit configured to initialize a first reliability value of a candidate symbol corresponding to a variable node based on an initial symbol allocated to the variable node; and a symbol correction circuit configured to update the first reliability values of the candidate symbols, respectively, based on communications received from check nodes coupled to the variable nodes, the candidate symbols having updated first reliability values, and to adjust the variable node value to one of the candidate symbols based on a comparison of the updated first reliability value of the one of the candidate symbols with a first threshold value.

Drawings

Fig. 1 is a diagram illustrating an error correction circuit based on an embodiment of the disclosed technology.

Fig. 2 is a diagram showing an example of a parity check matrix.

Fig. 3 is a diagram showing an example of a Tanner graph for the parity check matrix of fig. 2.

Fig. 4 is a diagram showing an example of syndrome vectors calculated using the parity check matrix of fig. 2.

Fig. 5 is a diagram illustrating an example of a symbol configuration process based on an embodiment of the disclosed technology.

Fig. 6 is a diagram for explaining a threshold value based on an embodiment of the disclosed technology.

Fig. 7 is a diagram illustrating an example of a process for initializing a first reliability value based on an embodiment of the disclosed technology.

Fig. 8 is a diagram illustrating an example of a process for correcting a symbol according to a first reliability value based on an embodiment of the disclosed technology.

Fig. 9 is a diagram for explaining a second reliability value based on an embodiment of the disclosed technology.

Fig. 10 is a diagram illustrating an example of a process for setting a second reliability value based on an embodiment of the disclosed technology.

Fig. 11 is a diagram illustrating an example of a process for correcting a symbol according to a second reliability value based on an embodiment of the disclosed technology.

Fig. 12 is a diagram illustrating an example of a process for setting a second reliability value based on an embodiment of the disclosed technology.

Fig. 13 is a diagram illustrating an example of a process for correcting a symbol according to a second reliability value based on an embodiment of the disclosed technology.

FIG. 14 is a flow chart illustrating a method of operating an error correction circuit based on an embodiment of the disclosed technology.

FIG. 15 is a flow chart illustrating a method of operating an error correction circuit based on an embodiment of the disclosed technology.

Fig. 16 is a diagram illustrating an example of a memory system based on an embodiment of the disclosed technology.

Fig. 17 is a diagram illustrating an example of a memory device based on an embodiment of the disclosed technology.

FIG. 18 is a diagram illustrating an example of a memory block based on an embodiment of the disclosed technology.

Fig. 19 and 20 are diagrams illustrating an embodiment of a memory system including the memory controller shown in fig. 16.

Detailed Description

The techniques disclosed in this patent document may be implemented in embodiments to provide error correction techniques that include error correction decoding using an iterative decoding scheme. Hereinafter, embodiments of the disclosed technology will be described with reference to the accompanying drawings.

Low Density Parity Check (LDPC) codes are widely used for error correction in communications and other systems. The LDPC decoding applies an iterative decoding scheme to improve error correction performance without increasing computational complexity per bit even when a code length increases. Various implementations of LDPC codes have some limitations. For example, hard errors in some LDPC codes may result in inefficiencies in the number of computation cycles or iterations required to produce a successful decode, and may result in a failed decoding operation.

Fig. 1 is a diagram illustrating an error correction circuit in accordance with an embodiment of the disclosed technology.

Referring to fig. 1, an error correction circuit 10 according to an embodiment of the disclosed technology may include an error correction decoder 100 and a post-processor 200.

The error correction decoder 100 may perform error correction decoding using various algorithms employing an iterative decoding scheme. For example, the error correction decoder 100 may perform error correction decoding using a Message Passing Algorithm (MPA), which is also referred to as a "Belief Propagation Algorithm (BPA)".

The error correction decoder 100 may perform error correction decoding within a predefined maximum number of iterations (maximum number of iterations). When a valid codeword satisfying a parity check matrix of the error correction code is generated within the maximum number of iterations, the error correction decoder 100 may output the generated valid codeword as a decoded codeword. When a valid codeword satisfying the parity check matrix of the error correction code is not generated within the maximum number of iterations, the error correction decoder 100 may output a failure signal indicating that error correction decoding has failed.

Error correction decoder 100 may be or include a Low Density Parity Check (LDPC) decoder that uses an LDPC code as an error correction code. The error correction decoder 100 may be or include a non-binary LDPC decoder that configures symbols by grouping bits included in read values received from a channel and performs error correction decoding based on the symbols.

The error correction decoder 100 may include a symbol configuration unit 110, a node processor 120, and a syndrome check unit 130.

The symbol configuration unit 110 may receive a read value from a channel. In some implementations, the channel from which the read value is obtained may represent a wired or wireless medium over which information is transmitted or a storage medium in which information is stored. In some implementations of the disclosed technology, the channel may indicate an interface to transfer data between the error correction circuit 10 and the memory device or indicate the memory device itself. The read value may correspond to a codeword generated by adding parity bits to the original message during error correction coding. For example, the symbol configuration unit 110 may receive a read value corresponding to one codeword from a memory device. In the following, the read values corresponding to a single codeword are referred to as read vectors.

The symbol configuration unit 110 may configure initial symbols by grouping bits included in the read vector, and may provide the configured initial symbols to the node processor 120. For example, when the read vector is composed of 14 bits, the symbol configuration unit 110 may configure seven initial symbols by grouping the bits into cells each having two bits.

The node processor 120 may perform error correction decoding based on the initial symbols received from the symbol configuration unit 110. The node processor 120 may perform error correction decoding using various algorithms employing an iterative decoding scheme. For example, the node processor 120 may perform error correction decoding using a Message Passing Algorithm (MPA). As the message passing algorithm, a sum-product algorithm, a minimum sum algorithm, or other algorithms may be used. In some implementations, various algorithms may also be used and are not limited to messaging algorithms.

The node processor 120 may perform iterations within a maximum number of iterations I, where I is a natural number. As a result of performing the ith iteration, the node processor 120 generates values of variable nodes and provides the values of the variable nodes to the syndrome check unit 130. Here, I is a natural number less than or equal to I. The value of the variable node provided to the syndrome checking unit 130 may be obtained by correction based on at least one of the first reliability value and the second reliability value, which will be described in detail later.

The message passing algorithm may generate an output that converges to the desired estimate of the read vector by exchanging iterations of messages between the variable nodes and the check nodes. The messages may include a variable to check (V2C) message sent from the variable node to the check node and a check to variable (C2V) message sent from the check node to the variable node.

The variable node update module 122 may initialize the variable node using the initial symbol received from the symbol configuration unit 110 before performing the first iteration. Accordingly, the variable node update module 122 may assign the initial symbols as variable node values to the respective variable nodes one by one.

The variable node update module 122 may generate a V2C message and send a V2C message to the check node update module 126 such that, in a first iteration, the variable node values (i.e., initial symbol values in the case of the first iteration) of the respective variable nodes may be transferred to the check nodes coupled with the corresponding variable nodes. The variable node update module 122 may update the values of the variable nodes in response to the C2V message received from the check node update module 126 in the respective iteration. The variable node update module 122 may generate V2C messages based on the C2V messages received from the check node update module 126 in various iterations other than the first iteration, and may send the generated V2C messages to the check node update module 126.

The check node update module 126 may update the values of the check nodes in response to the V2C message received from the variable node update module 122 in the respective iteration. The check node update module 126 may generate a C2V message based on the V2C message received from the variable node update module 122 in the respective iteration, and may send the generated C2V message to the variable node update module 122.

Edge gain processing or inverse edge gain processing may be performed on messages exchanged between the variable node update module 122 and the check node update module 126. For example, the edge gain processing unit 124 may perform edge gain processing on the V2C message generated by the variable node update module 122 and may send the processed V2C message to the check node update module 126. For example, the edge gain processing unit 124 may perform inverse edge gain processing on the C2V message generated by the check node update module 126 and may send the processed C2V message to the variable node update module 122. The edge gains may be obtained from the parity check matrix and may also be referred to as "edge coefficients" or "edge weights".

The variable node update module 122 may include a reliability value initialization unit 122a, a symbol correction unit 122b, and a threshold setting unit 122 c.

The reliability value initialization unit 122a may initialize a first reliability value, which is a reliability value of a candidate symbol that may be selected as a value of each variable node. Initialization may be performed at the beginning of each iteration and based on initial symbols respectively assigned to a plurality of variable nodes. The reliability value initialization unit 122a may initialize the first reliability value of the candidate symbol at the start of the initial iteration or each time a notification that error correction decoding has failed in the ith iteration is received from the syndrome check unit 130. Here, the candidate symbols may represent all symbols existing in the galois field gf (q).

The reliability value initialization unit 122a may initialize a second reliability value, which is a reliability value corresponding to each variable node, at the start of the initial iteration. The second reliability value may represent unreliability of a current variable node value of the corresponding variable node. When adjusting the value of the correspondent variable node based on the second reliability value, the reliability value initialization unit 122a may initialize the second reliability value.

The reliability value initialization unit 122a may differently initialize the first reliability values of the candidate symbols respectively corresponding to the variable nodes. Accordingly, the first reliability values of the candidate symbols are initialized to different values from each other by the reliability value initialization unit 122 a. In order to initialize the first reliability values of the candidate symbols to be different from each other, the reliability value initialization unit 122a may employ various techniques, as discussed below.

In one embodiment, the reliability value initialization unit 122a may initialize the first reliability value of the corresponding candidate symbol differently based on a hamming distance between the initial symbol allocated to each of the plurality of variable nodes and the candidate symbol. In one embodiment, the reliability value initialization unit 122a may initialize the first reliability value of the candidate symbol to have a higher value when the hamming distance between the initial symbol and the candidate symbol is shorter, and initialize the first reliability value of the candidate symbol to have a lower value when the hamming distance between the initial symbol and the candidate symbol is longer. For example, assume that GF (4) symbols are used and the initial symbol assigned to any variable node is "01". In this case, there may be four types of candidate symbols corresponding to arbitrary variable nodes, for example, "00", "01", "10", and "11". Hereinafter, each of the symbols "00", "01", "10", and "11" represents a binary representation of a GF (4) symbol. The hamming distance of the candidate symbol "01" from the initial symbol "01" is 0, the hamming distance of each of the candidate symbols "00" and "11" from the initial symbol "01" is 1, and the hamming distance of the candidate symbol "10" from the initial symbol "01" is 2. In some implementations, the first reliability value of a candidate symbol "01" having a hamming distance of 0 from the initial symbol "01" may be initialized to 3, the first reliability values of candidate symbols "00" and "11" each having a hamming distance of 1 from the initial symbol "01" may be initialized to 1, and the first reliability value of a candidate symbol "10" having a hamming distance of 2 from the initial symbol "01" may be initialized to 0.

In one embodiment, the reliability value initialization unit 122a may initialize the first reliability value of the corresponding candidate symbol differently based on the iteration turns. In one embodiment, the reliability value initialization unit 122a may initialize the first reliability value to a higher value as the number of iteration rounds increases. In one embodiment, the reliability value initialization unit 122a may initialize the first reliability value of the candidate symbol to a higher value than in the previous iteration as the iteration round increases and the hamming distance between the initial symbol and the corresponding candidate symbol is shorter. For example, assume that GF (4) symbols are used and the initial symbol assigned to any variable node is "01". It is also assumed that in the ith iteration, the first reliability value of candidate symbol "01" is initialized to 3, the first reliability values of candidate symbols "00" and "11" are initialized to 1, and the first reliability value of candidate symbol "10" is initialized to 0. In some implementations, in the (i + 1) th iteration, the reliability value initialization unit 122a may initialize the first reliability value of the candidate symbol "01" having the shortest hamming distance to the initial symbol "01" to 4. In some implementations, the first reliability values of the remaining candidate symbols "00", "11", and "10" may be initialized to the same values as in the previous iteration round. Alternatively, in the (i + 1) th iteration, the reliability value initialization unit 122a may initialize the first reliability value of the candidate symbol "01" having the shortest hamming distance to the initial symbol "01" to 5, and may initialize the first reliability values of the candidate symbols "00" and "11" having the next shortest hamming distance to the initial symbol "01" to 4. In some implementations, the first reliability value of the remaining candidate symbol "10" may be initialized to the same value as in the previous iteration round. In one embodiment, as the iteration turns increase and the hamming distance between the initial symbol and the candidate symbol is shorter, the reliability value initialization unit 122a may initialize the first reliability value of the corresponding candidate symbol to a lower value than the previous iteration turn.

In one embodiment, the reliability value initialization unit 122a may initialize the first reliability value of each candidate symbol based on the number of Unsatisfied Check Nodes (UCNs). In one embodiment, the greater the number of UCNs in the ith iteration, the reliability value initialization unit 122a may initialize the first reliability value to a higher value in the (i + 1) th iteration. In one embodiment, the greater the number of UCNs in the ith iteration and the shorter the hamming distance between the initial symbol and the candidate symbol, the reliability value initialization unit 122a may initialize the first reliability value of the candidate symbol to a higher value in the (i + 1) th iteration. For example, assume that GF (4) symbols are used and the initial symbol assigned to any variable node is "01". It is also assumed that in the ith iteration, the first reliability value of candidate symbol "01" is initialized to 3, the first reliability values of candidate symbols "00" and "11" are initialized to 1, and the first reliability value of candidate symbol "10" is initialized to 0. In this case, when the number of UCNs is 3 in the ith iteration, the reliability value initialization unit 122a may initialize the first reliability values of all candidate symbols in the (i + 1) th iteration to the same value as that in the ith iteration. When the number of UCNs in the ith iteration is 5, the reliability value initialization unit 122a may initialize the first reliability value of the candidate symbol "01" having the shortest hamming distance from the initial symbol "01" to 4 in the (i + 1) th iteration. In some implementations, the first reliability values of the remaining candidate symbols "00", "11", and "10" may be initialized to the same values as in the previous iteration round. According to an embodiment, the greater the number of UCNs in the ith iteration and the shorter the hamming distance between the initial symbol and the candidate symbol, the reliability value initialization unit 122a may initialize the first reliability value of the candidate symbol to a lower value in the (i + 1) th iteration.

The symbol correction unit 122b may update the first reliability values of the candidate symbols corresponding to the respective variable nodes based on the C2V message received from the respective variable nodes in each iteration. In one embodiment, symbol correction unit 122b may increase the first reliability value of any candidate symbol by the number of receptions of the C2V message indicating any candidate symbol. For example, when one C2V message indicating candidate symbol "10" is received, symbol correction unit 122b may increase the first reliability value of candidate symbol "10" by 1. Further, when two C2V messages indicating candidate symbol "10" are received, symbol correction unit 122b may increase the first reliability value of candidate symbol "10" by 2.

After updating the first reliability value of the candidate symbol, the symbol correction unit 122b may adjust the value of the at least one variable node based on the updated first reliability value. For each variable node, the symbol correction unit 122b may determine whether the candidate symbol has a first reliability value equal to or greater than a first threshold. The symbol correction unit 122b may adjust the value of the variable node when the corresponding candidate symbol has a first reliability value equal to or greater than a first threshold value. For example, when any one of the candidate symbols has a first reliability value equal to or greater than a first threshold value, the symbol correction unit 122b may adjust the value of the variable node corresponding to the candidate symbol having the first reliability value equal to or greater than the first threshold value.

Thus, when there are any candidate symbols having a first reliability value equal to or greater than the first threshold value, the value of the variable node is adjusted based on the first reliability value. Meanwhile, in order to guarantee the reliability of the variable node even when there is no candidate symbol having a first reliability value equal to or greater than the first threshold value, a second reliability value other than the first reliability value is introduced. The second reliability value may indicate the reliability or unreliability of the current value of the variable node. To indicate the second reliability value, one bit or two or more bits may be allocated. Two cases where the second reliability value has one bit or more bits will be described below, respectively.

First, a case where one bit is allocated to indicate the second reliability value will be described below.

For each variable node whose corresponding candidate symbol has a first reliability value less than a first threshold, the symbol correction unit 122b may determine whether there is a candidate symbol having a first reliability value equal to or greater than a second threshold smaller than the first threshold among the candidate symbols. When there is a variable node whose corresponding candidate symbol has a first reliability value smaller than the first threshold value and equal to or larger than the second threshold value, the symbol correction unit 122b may determine whether to set the second reliability value in the corresponding variable node. For example, the symbol correction unit 122b may check whether a bit allocated to indicate the second reliability value is set to 1.

When the second reliability value is not set in the variable node corresponding to the candidate symbol having the first reliability value smaller than the first threshold value and equal to or larger than the second threshold value, the symbol correction unit 122b may set the second reliability value in the corresponding variable node. Therefore, when there is no candidate symbol having a first reliability value equal to or greater than the first threshold among the candidate symbols in the variable nodes but there is a candidate symbol having a first reliability value equal to or greater than the second threshold smaller than the first threshold among the candidate symbols, the symbol correction unit 122b may set the second reliability value in the corresponding variable node. For example, the symbol correction unit 122b may set the second reliability value to 1 for the correspondent variable node. The second reliability value corresponding to the arbitrary variable node may not be initialized before adjusting the value of the arbitrary variable node based on the second reliability value.

When the second reliability value is set in the variable node, the symbol correction unit 122b may adjust the value of the corresponding variable node. As described above, when there is a corresponding candidate symbol having the first reliability value smaller than the first threshold value and equal to or larger than the second threshold value, the second reliability value is set in the variable node. For example, when the second reliability value is set, the symbol correction unit 122b may adjust the value of the variable node to candidate symbols having the first reliability value smaller than the first threshold value and equal to or larger than the second threshold value. When the value of the variable node is adjusted, the symbol correction unit 122b may notify the reliability value initialization unit 122a of such adjustment. Accordingly, the reliability value initialization unit 122a may initialize the second reliability value of the correspondent variable node.

Next, a case where two or more bits are allocated to indicate the second reliability value will be described below.

When two or more bits are allocated to indicate the second reliability value, n (where n is a natural number of 4 or more) thresholds may be used. For each variable node where a corresponding candidate symbol having a first reliability value equal to or greater than a first threshold value does not exist, the symbol correction unit 122b may determine whether there exists a candidate symbol having a first reliability value equal to or greater than second to n-1 th threshold values smaller than the first threshold value among the candidate symbols. Such determinations may be performed sequentially from a higher threshold value, i.e., in the order of the second threshold value through the n-1 th threshold value. Here, when it is determined that there is a candidate symbol having a first reliability value equal to or greater than any one of the second to n-1 th thresholds among the candidate symbols, the determination regarding the remaining threshold may not be performed. For example, with respect to a variable node in which candidate symbols having a first reliability value equal to or greater than a second threshold value exist, determination of whether there exists candidate symbols having a first reliability value equal to or greater than third to n-1 th threshold values among the candidate symbols may not be performed.

When it is determined that there is a candidate symbol having a first reliability value equal to or greater than any one of the second to n-1 th thresholds, the symbol correction unit 122b may increase the second reliability value of the corresponding variable node by a set value corresponding to the correlation threshold. Here, the larger the correlation threshold value, the higher the setting value. For example, when there is a candidate symbol having a first reliability value equal to or greater than a second threshold value, the symbol correction unit 122b may increase the second reliability value of the corresponding variable node by a first set value, and when there is a candidate symbol having a first reliability value equal to or greater than a third threshold value, the symbol correction unit 122b may increase the second reliability value of the corresponding variable node by a second set value smaller than the first set value.

The symbol correction unit 122b may determine whether the updated second reliability value is equal to or greater than the nth threshold value. When the updated second reliability value is less than the nth threshold, the second reliability value may be cumulatively calculated in a next iteration. When the updated second reliability value is equal to or greater than the nth threshold value, the symbol correction unit 122b may adjust the value of the corresponding variable node. For example, the symbol correction unit 122b may adjust the value of the correspondent variable node to the candidate symbol that updated the second reliability value in the current iteration.

When adjusting the value of the variable node based on the second reliability value, the symbol correction unit 122b may notify the reliability value initialization unit 122a of such adjustment. Accordingly, the reliability value initialization unit 122a may initialize the second reliability value of the correspondent variable node.

Symbol correction unit 122b may provide the values of the variable nodes to syndrome check unit 130 in each iteration. At least one of the values of the variable nodes provided to the syndrome check unit 130 may be a value adjusted based on the first reliability value and the second reliability value.

The threshold setting unit 122c may set a threshold, which is a criterion for determining whether to adjust the value of the variable node.

In one embodiment, the threshold setting unit 122c may set the initial threshold to a predetermined value. There is an initial threshold before the first iteration is performed. In one embodiment, the threshold setting unit 122c may set the same nth threshold for all variable nodes. For example, the same first threshold value may be set for all variable nodes, and the same second threshold value may also be set for all variable nodes.

In one embodiment, the threshold setting unit 122c may set the initial threshold to different values according to degrees (degrees) of variable nodes. For example, the threshold setting unit 122c may set the initial threshold to a higher value for a variable node having a higher degree and set the initial threshold to a lower value for a variable node having a lower degree.

In one embodiment, the threshold setting unit 122c may change at least one of the thresholds according to the iteration turns. For example, the threshold setting unit 122c may set at least one of the thresholds to a higher value as the iteration round increases. In some implementations, the threshold setting unit 122c may set at least one of the thresholds to a lower value as the iteration round increases.

In one embodiment, the threshold setting unit 122c may change at least one of the thresholds according to the number of UCNs corresponding to syndrome check. For example, the larger the number of UCNs corresponding to the ith iteration, the threshold setting unit 122c may set at least one of the thresholds to a higher value in the (i + 1) th iteration. In some implementations, the greater the number of UCNs corresponding to the ith iteration, the lower the threshold setting unit 122c may set at least one of the thresholds to a lower value.

As a result of the ith iteration, syndrome check unit 130 may receive values of variable nodes (e.g., variable node vectors) from node processor 120. Syndrome check unit 130 may store values of the variable nodes in first buffer 132 and may perform syndrome checks on the received variable node vectors. For example, the syndrome vector S calculated by the following equation (1) may be checked_iIs "0" to perform syndrome checking.

Here, S_iRepresenting the syndrome vector in the ith iteration, H representing the parity check matrix of the error correction code,

represents the variable node vector C in the ith iteration_iThe transposing of (1).

Syndrome vector S_iThe case where all the entries of (1) are "0" means that the syndrome check has passed. This means that it has become established in the ith iterationError correction decoding is successfully performed, and thus, the syndrome check unit 130 may output the variable node vector stored in the first buffer 132 as a decoded codeword.

At the same time, in the syndrome vector S_iThe case where there is an entry other than "0" among the entries of (a) means that the syndrome check has failed. This means that error correction decoding fails in the ith iteration. When error correction decoding fails in the ith iteration, the syndrome checking unit 130 may correct the syndrome vector S corresponding to the ith iteration_iSent to the node processor 120 or may provide information about the syndrome vector S_iCorresponding information not satisfying the number of check nodes (UCNs) to the node processor 120. Here, the UCN may correspond to the syndrome vector S_iEach entry other than "0" among the entries of (1).

If a valid codeword satisfying the parity check matrix of the error correction code is not generated within the maximum number of iterations I, syndrome check unit 130 may output a failure signal indicating that error correction decoding has failed. The processing and operations performed by syndrome check unit 130, including determining a pass or fail and outputting a corresponding codeword or fail signal, will be further described later herein with reference to fig. 2-4.

The post-processor 200 may support the error correction decoder 100 such that the error correction decoder 100 is capable of generating valid codewords. For example, the post-processor 200 may assist the error correction decoder 100 when the error correction decoder 100 fails to generate a valid codeword within the maximum number of iterations. With the aid of the post-processor 200, various parameters for error correction decoding are modified, and the error correction decoder 100 performs error correction decoding again using the modified parameters.

Fig. 2 is a diagram showing an example of a parity check matrix.

In FIG. 2, an example of a parity check matrix H is depicted that defines an (n, k) code, which may be defined as a parity check matrix having a size of (n-k) x n, each entry in the parity check matrix may be represented by an element belonging to a Galois field, the Galois field GF (q) is a finite field of q elements, and the elements of the Galois field GF (q) may be represented as {0, α }⁰,α¹,...,α^q-2}. non-zero entry α when included in a parity check matrix⁰,α¹,...,α^q-2Is much smaller than the number of 0 terms, the (n, k) code may be referred to as an (n, k) LDPC code. Here, n and k may be natural numbers. Meanwhile, the LDPC code belonging to the galois field represented by GF (2) may be a binary LDPC code and belong to the galois field represented by GF (q) (where q is>2) The represented galois field LDPC code may be a non-binary LDPC (NB-LDPC) code. In fig. 2, a parity check matrix of an NB-LDPC code having an element of GF (4) as an entry is shown as an example.

Fig. 3 is a diagram showing an example of a Tanner graph for the parity check matrix of fig. 2.

The (n, k) code can be represented by a Tanner graph, which is an expression of a bipartite graph. The Tanner graph may be represented by check nodes, variable nodes, and edges. The check nodes may correspond to rows of a parity check matrix and the variable nodes may correspond to columns of the parity check matrix. Each edge couples a single check node to a single variable node and represents an entry represented by an element other than 0 in the parity check matrix.

As shown in FIG. 3, the parity check matrix of the (n, k) code shown in FIG. 2 may be constructed by including n-k check nodes CN₁To CN_n-kAnd n variable nodes VN₁To VN_nThe Tanner graph of (a). To check node CN₁To CN_n-kCoupled to variable nodes VN₁To VN_nThe solid and dashed lines of (a) indicate edges.

Can be based on the check node CN in the Tanner graph shown in fig. 3₁To CN_n-kAnd variable node VN₁To VN_nAn iterative message passing algorithm in between to perform iterative decoding. In each iteration, it may be at the check node CN₁To CN_n-kAnd variable node VN₁To VN_nIterative decoding is performed while transferring the C2V message and the V2C message. The variable nodes may perform error correction using C2V messages received from check nodes coupled thereto, and the check nodes may perform check using V2C messages received from variable nodes coupled theretoAnd (5) operating. When a result value obtained by any one check node performing an exclusive or (XOR) operation on the values of all the variable nodes coupled thereto consists of only 0, the corresponding check node may be determined to be satisfied. In contrast, when a result value obtained by any one check node performing an XOR operation on the values of all variable nodes coupled thereto contains an element other than 0, the corresponding check node may be determined not to be satisfied, and may be referred to as "UCN". Here, the value of the variable node on which the XOR operation is performed may be a value obtained after the edge gain processing.

Fig. 4 is a diagram illustrating an example of syndrome vectors calculated using the parity check matrix illustrated in fig. 2.

As described above, the variable node vector C, which is the result value from the ith iteration, may be based on the parity check matrix H_iIs used to calculate the syndrome vector S_i. Syndrome vector S_iEach item S of_i1、S_i2...S_in-kCorresponding to the check node CN in the Tanner graph shown in fig. 3₁To CN_n-k。

If the syndrome vector S_iAll items S of_i1、S_i2...S_in-kBoth indicate "0", the syndrome check is determined to be passed. Accordingly, iterative decoding of the corresponding read vector may be terminated, and a variable node vector C may be output as a result value from the ith iteration_iAs a decoded codeword.

If at the syndrome vector S_iItem S of_i1、S_i2...S_in-kWhere there is at least one entry other than 0, then the syndrome check is determined to have failed. Thus, when the number of iterations has not reached the maximum number of iterations, the next iteration may be performed. Here, an entry other than 0 is referred to as UCN.

Fig. 5 is a diagram illustrating an example of a symbol configuration process based on an embodiment of the disclosed technology.

In the embodiment shown in fig. 5, it is assumed that the read vector received from the channel consists of 14 bits.

The symbol configuration unit 110 may be included inThe bits in the read vector are grouped into a predetermined number of cells to configure a plurality of symbols. For example, when GF (4) symbols are used, the symbol configuration unit 110 may configure a single symbol to include two bits. Since the symbol configuration unit 110 can configure a total of seven symbols when the read vector is composed of 14 bits, each symbol includes two bits. The symbol configuration unit may assign the configured symbols sequentially to the variable nodes VN₁、...、VN₇。

In the following, it is assumed that the binary representation of "00" corresponds to the GF (4) representation of "0", the binary representation of "01" corresponds to the GF (4) representation of "1", the binary representation of "10" corresponds to the GF (4) representation of "α", and the binary representation of "11" corresponds to "α²"GF (4)" means.

Fig. 6 is a diagram for explaining a threshold value based on an embodiment of the disclosed technology. In setting the threshold value for adjusting the value of each variable node, the following different cases may be considered based on whether the second reliability value is used to adjust the value of each variable node and based on whether a single bit or a plurality of bits are allocated to indicate the second reliability value.

When only the first reliability value is used and the second reliability value is not used, a single threshold (i.e., the first threshold) may be used as a determination criterion for adjusting the value of each variable node.

When both the first reliability value and the second reliability value are used and a single bit is allocated to indicate the second reliability value, two thresholds, i.e., the first threshold and the second threshold, may be used as determination criteria for adjusting the value of each variable node.

When both the first reliability value and the second reliability value are used and two or more bits are allocated to indicate the second reliability value, n thresholds (where n is a natural number of 4 or more) may be used as determination criteria for adjusting the value of each variable node.

As an example, fig. 6 shows the following case: two or more bits are allocated to indicate the second reliability value using both the first reliability value and the second reliability value, and four thresholds are used as determination criteria for adjusting the values of the variable nodes.

For example, the first to third thresholds may be reference values to be compared with the first reliability value of the candidate symbol, and the fourth threshold may be reference values to be compared with the second reliability value of the variable node.

As described above, the threshold value may be set differently according to the degree of the variable node. For example, at least one of the thresholds may be set to a higher value in a variable node having a higher degree, and at least one of the thresholds may be set to a lower value in a variable node having a lower degree. In some implementations, the thresholds may also be set in the opposite manner, such that at least one of the thresholds is set to a lower value in variable nodes having a higher degree and at least one of the threshold voltages is set to a higher value in variable nodes having a lower degree.

In the example shown in fig. 6, VN is a variable node having a relatively high degree of 32₁And VN₃Is set to a higher threshold and is set at a variable node VN having a relatively low degree 26₂And VN_nSet a lower threshold.

Fig. 7 is a diagram illustrating an example of a process for initializing a first reliability value in accordance with an embodiment of the disclosed technology.

In fig. 7, for convenience of description, only some variable nodes and some check nodes included in the Tanner graph are shown. As shown in fig. 7, it is assumed that a GF (4) symbol is used and an initial symbol "1" is assigned to the variable node VN₁Assigning an initial symbol "0" to the variable node VN₂Assigning an initial symbol "α" to the variable node VN₃And will initiate the symbol "α²"assigned to variable node VN_n。

In the example of fig. 7, the shorter the hamming distance between the initial symbol assigned to each variable node and the candidate symbol corresponding to the variable node is, the higher the first reliability value of the candidate symbol is initialized to. For ease of description, in the following description, only the variable nodes VN will be discussed in detail as an example₁、...、VN_nTwo variable nodes VN₁And VN₂And the same configuration can also be applied to the remaining variable nodes VN₃、...、VN_n。

FIG. 7 shows candidate symbols "0", "1", "α", and "α for each variable node²"set first reliability value. Referring to FIG. 7, at variable node VN₁May be directed to having a variable node VN₁The nearest candidate symbol "1" of the shortest hamming distance 0 of the initial symbol "1" of (1) is set as the first reliability value of the highest value 3. At variable node VN₁May be directed to having a variable node VN₁The farthest candidate symbol "α" of the longest hamming distance 2 of the initial symbol "1" is set as the first reliability value of the lowest value 0₁Can be directed to having a variable to variable node VN₁The candidate symbols "0" and "α of hamming distance 1 of the initial symbol" 1²"a first reliability value of 1 is set as an intermediate value between the highest value of" 3 "and the lowest value of" 0 ".

Similarly, at variable node VN₂May be directed to having a variable node VN₂The nearest candidate symbol "0" of the shortest hamming distance 0 of the initial symbol "0" of is set as the first reliability value of the highest value 3. At variable node VN₂May be directed to having a variable node VN₂The farthest candidate symbol "α of the longest hamming distance 2 of the initial symbol" 0²"set the first reliability value as the lowest value 0. At variable node VN₂May be directed to having a variable node VN₂The candidate symbols "1" and "α" of the hamming distance 1 of the initial symbol "0" set the first reliability value 1 as an intermediate value between the highest value of "3" and the lowest value of "0".

Fig. 8 is a diagram illustrating an example of a process for correcting a symbol according to a first reliability value based on an embodiment of the disclosed technology.

The sign correction unit 122b may, in each iteration, depend on the inputs to the respective variable nodes VN₁、VN₂、VN₃...VN_nC2V message to update the respective variable node VN₁、VN₂、VN₃...VN_nFor example, when one C2V message indicating candidate symbol "α" is received, symbol correction unit 122b may increase the first reliability value of candidate symbol "α" by 1. further, when two C2V messages indicating candidate symbol "α" are received, symbol correction unit 122b may increase the first reliability value of candidate symbol "α" by 2.

In the example of fig. 8, the variable node VN₁And VN₂Are updated from their initial values as shown in fig. 7. It is assumed that the variable node VN after the initialization process described with reference to fig. 7₁Receiving 17C 2V messages indicating a candidate symbol of "0", receiving 4C 2V messages indicating a candidate symbol of "1", receiving 5C 2V messages indicating a candidate symbol of "α", and receiving a message indicating a candidate symbol of "α²"6C 2V messages. Thus, variable node VN₁May be updated from the initial value of 1 to 18, the variable node VN₁The first reliability value of the candidate symbol "1" of (b) may be updated from an initial value of 3 to 7, the variable node VN₁May be updated from an initial value of 0 to 5, and the variable node VN₁Candidate symbol of "α²"may be updated from an initial value of 1 to 7.

In the example of fig. 8, it is assumed that the variable node VN₂Receiving 8C 2V messages indicating a candidate symbol of "0", receiving 7C 2V messages indicating a candidate symbol of "1", receiving 4C 2V messages indicating a candidate symbol of "α", and receiving a message indicating a candidate symbol of "α²"7C 2V messages. Due to the fact thatHere, variable node VN₂May be updated from an initial value of 3 to 11, the variable node VN₂The first reliability value of the candidate symbol "1" of (1) may be updated from the initial value of 1 to 8, the variable node VN₂May be updated from an initial value of 1 to 5, and the variable node VN₂Candidate symbol of "α²"may be updated from an initial value of 0 to 7.

After updating the first reliability value, the symbol correction unit 122b may check, for each variable node, whether there is a candidate symbol having the first reliability value equal to or greater than a first threshold value among the candidate symbols, and may adjust the value of the variable node having the corresponding candidate symbol having the first reliability value equal to or greater than the first threshold value. In the example of fig. 8, it is assumed that VN corresponds to a variable node₁Is set to 13 and corresponds to the variable node VN₂Is set to 12.

At variable node VN₁Due to the fact that at the variable node VN₁Is equal to or greater than as corresponding to the variable node VN₁First threshold value 13, variable node VN₁The value of (c) can be adjusted from "1" to "0". At variable node VN₂Due to the fact that at the variable node VN₂Is equal to or greater than as corresponding to the variable node VN₂May not adjust the variable node VN₂The value of (c).

Fig. 9 is a diagram for explaining a second reliability value based on an embodiment of the disclosed technology.

Unlike the embodiment of fig. 7, in fig. 9, the second reliability value and the first reliability value are set for each variable node. As discussed above, when there is no candidate symbol having the first reliability value equal to or greater than the first threshold among the candidate symbols of the variable node, but there is a candidate symbol having the first reliability value equal to or greater than the predetermined threshold, the second reliability value may be set (or updated) in the corresponding variable node. When the variable node has the second reliability value, it can be considered that there is a possibility that the current value of the variable node has an error. In other words, the second reliability value may indicate the unreliability of the current value of the variable node.

The first reliability value may be initialized each time each iteration starts, but the second reliability value may not be initialized even if the iterative process is in progress. However, when the value of the variable node is adjusted to any one of the candidate symbols based on the second reliability value, the second reliability value may be initialized. As described above, one bit or two or more bits may be allocated to indicate the second reliability value.

Fig. 10 is a diagram illustrating an example of a process for setting a second reliability value based on an embodiment of the disclosed technology.

In the embodiment shown in fig. 10, one bit is allocated to indicate the second reliability value.

The sign correction unit 122b may be based on inputs to the respective variable nodes VN in each iteration₁、VN₂、VN₃...VN_nC2V message to update the respective variable node VN₁、VN₂、VN₃...VN_nA first reliability value of the corresponding candidate symbol.

In the example of fig. 10, the variable node VN after initializing the first reliability value and the second reliability value₁Receiving seventeen C2V messages indicating a candidate symbol of "0", receiving four C2V messages indicating a candidate symbol of "1", receiving five C2V messages indicating a candidate symbol of "α", and receiving a message indicating a candidate symbol of "α²"six C2V messages. Thus, variable node VN₁May be updated from the initial value of 1 to 18, the variable node VN₁The first reliability value of the candidate symbol "1" of (b) may be updated from an initial value of 3 to 7, the variable node VN₁May be updated from an initial value of 0 to 5, and the variable node VN₁Candidate symbol of "α²"may be updated from an initial value of 1 to 7.

Further, in the example of fig. 10, the variable node VN₂Receiving six C2V messages indicating a candidate symbol of "0", receiving nine C2V messages indicating a candidate symbol of "1", receiving four C2V messages indicating a candidate symbol of "α", and receiving a message indicating a candidate symbol of "α²"seven C2V messages. Thus, variable node VN₂May be updated from an initial value of 3 to 9, the variable node VN₂The first reliability value of the candidate symbol "1" of (1) may be updated from the initial value of 1 to 10, the variable node VN₂May be updated from an initial value of 1 to 5, and the variable node VN₂Candidate symbol of "α²"may be updated from an initial value of 0 to 7.

After updating the first reliability value, the symbol correction unit 122b may check, for each variable node, whether there is a candidate symbol having the first reliability value equal to or greater than a first threshold value among the candidate symbols, and may adjust the value of the variable node having the corresponding candidate symbol having the first reliability value equal to or greater than the first threshold value. In the example of fig. 10, it is assumed that VN corresponds to a variable node₁Is set to 13 and corresponds to the variable node VN₂Is set to 12.

At variable node VN₁Due to the fact that at the variable node VN₁Is equal to or greater than 13 (corresponding to the variable node VN)₁First threshold of) variable node VN₁The value of (c) can be adjusted from "1" to "0".

At variable node VN₂Due to the fact that at the variable node VN₂Has a first reliability value equal to or greater than 12 (corresponding to the variable node VN)₂First threshold of) the variable node VN may not be adjusted₂The value of (c).

Candidate as in variable nodeWhen there is no candidate symbol having the first reliability value equal to or greater than the first threshold value among the symbols, the symbol correction unit 122b may determine whether there is a candidate symbol having the first reliability value equal to or greater than the second threshold value among the candidate symbols of the variable nodes. When there is a candidate symbol having a first reliability value smaller than the first threshold value and equal to or larger than the second threshold value, the symbol correction unit 122b may set a second reliability value in the corresponding variable node. In the example of fig. 10, corresponding to variable node VN₂Is set to 10.

In this case, VN is the variable node₂Is equal to or greater than 10 (corresponding to the variable node VN)₂Second threshold of) may be at variable node VN₂Set a second reliability value. Thus, in FIG. 10, variable node VN₂Is set to 1.

Fig. 11 is a diagram illustrating an example of a process for correcting a symbol according to a second reliability value based on an embodiment of the disclosed technology.

Fig. 11 shows an example of a case of a next iteration in which the first reliability value is initialized and the second reliability value is maintained after the symbol modification and the second reliability value setting are completed as described above with reference to fig. 10. In the example of fig. 11, the value of the variable node is adjusted based on the number of C2V messages received by the variable node in the next iteration.

Similar to the configuration described with reference to fig. 10, the symbol correction unit 122b may update the first reliability value of the candidate symbol based on the number of C2V messages received by the variable node. When there is a candidate symbol whose updated first reliability value is equal to or greater than the first threshold value, the symbol correction unit 122b may adjust the value of the corresponding variable node to the candidate symbol. In the example of fig. 11, the variable node VN₁Candidate symbol of "α²"has a first reliability value equal to or greater than 13 (corresponding to the variable node VN)₁First threshold of) so will the variable node VN₁Is adjusted from "0" to "α²”。

Meanwhile, when there is no candidate symbol whose updated first reliability value is equal to or greater than the first threshold value, the symbol correction unit 122b may check whether there is a candidate symbol whose updated first reliability value is equal to or greater than the second threshold value. When there is a candidate symbol whose updated first reliability value is equal to or greater than the second threshold value, the symbol correction unit 122b may check whether the second reliability value is set in the corresponding variable node. The symbol correction unit 122b may set the second reliability value in the corresponding variable node when the second reliability value is not set in the corresponding variable node, and the symbol correction unit 122b may adjust the value of the corresponding variable node when the second reliability value is set in the corresponding variable node.

In the example of fig. 11, the variable node VN₂Is equal to or greater than 10 (corresponding to the variable node VN)₂Second threshold value of). Since the variable node VN has already been present in the previous iteration₂In which a second reliability value is set, the sign correction unit may adjust the variable node VN₂The value of (c). In this case, the symbol correction unit may adjust the value of the variable node to a candidate symbol having a first reliability value equal to or greater than the second threshold value in the current iteration.

For example, as described above with reference to FIG. 10, at variable node VN₂Even if the first reliability value of the candidate symbol "1" is equal to or greater than the second threshold value in the previous iteration and then at the variable node VN₂Is set to the second reliability value, but in the current iteration when at the variable node VN₂May be equal to or greater than a second threshold value, the variable node VN may be set₂The value of (d) is adjusted to "α" as shown in fig. 11.

Fig. 12 is a diagram illustrating an example of a process for setting a second reliability value in accordance with an embodiment of the disclosed technology.

In the example of fig. 12, two or more bits are allocated to indicate the second reliability value.

In the example of fig. 12, after initializing the first reliability value and the second reliability value, VN is based on the variable nodes VN₁And VN₂The received C2V message updates the first reliability value.

In the example of fig. 12, the variable node VN₁Is updated to 11, the variable node VN₁Is updated to 6, the variable node VN₁Is updated to 8, and the variable node VN₁Candidate symbol of "α²"is updated to 9. In addition, variable node VN₂Is updated to 7, the variable node VN₂Is updated to 8, the variable node VN₂Is updated to 6, and the variable node VN₂Candidate symbol of "α²"is updated to 7.

After updating the first reliability value, the symbol correction unit 122b may check, for each variable node, whether there is a candidate symbol having a first reliability value equal to or greater than a first threshold value among the candidate symbols, and may adjust the value of the variable node in which there is a candidate symbol having a first reliability value equal to or greater than the first threshold value. As an example, corresponding to a variable node VN₁Is set to 13 and corresponds to the variable node VN₂Is set to 12. Due to the fact that VN is a variable node₁And VN₂May not adjust the variable node VN if there is no candidate symbol that satisfies the first threshold value among the candidate symbols of (b), the variable node VN may not be adjusted₁And VN₂The value of (c).

For each variable node whose corresponding candidate symbol does not have a first reliability value equal to or greater than a first threshold, symbol correction unit 122b may determine whether there is a candidate symbol having a first reliability value equal to or greater than a second threshold. When there is a candidate having a first reliability value smaller than a first threshold value and equal to or larger than a second threshold valueIn sign, the sign correcting unit 122b may update the second reliability value of the corresponding variable node. In the example of fig. 12, corresponding to variable node VN₁Is set to 11 and corresponds to the variable node VN₂Is set to 10. In this case, VN is the variable node₁Is equal to or greater than 11 (corresponding to the variable node VN)₁Second threshold of) may be updated, the variable node VN may be updated₁The second reliability value of (1). At this time, the second reliability value may be updated to a set value corresponding to the second threshold value. The setting value may be different for each corresponding threshold value. For example, the set value corresponding to the second threshold value may be 2, and the set value corresponding to the third threshold value may be 1. In the example of fig. 12, the set value corresponding to the second threshold value is 2, and then the variable node VN₁Is updated to 2.

For each variable node whose corresponding candidate symbol does not have a first reliability value equal to or greater than the second threshold, the symbol correction unit 122b may determine whether there is a candidate symbol having a first reliability value equal to or greater than a third threshold. When it is determined that there is a candidate symbol having a first reliability value smaller than the second threshold value and equal to or larger than the third threshold value, the symbol correction unit 122b may update the second reliability value of the corresponding variable node. In the example of fig. 12, corresponding to variable node VN₂Is set to 8. In this case, VN is the variable node₂Is equal to or greater than 8 (corresponding to the variable node VN)₂Third threshold of) may be updated, the variable node VN may be updated₂The second reliability value of (1). In the example of fig. 12, the set value corresponding to the third threshold is 1, and then the variable node VN₂Is updated to 1.

Fig. 13 is a diagram illustrating an example of a process for correcting a symbol according to a second reliability value in accordance with an embodiment of the disclosed technology.

Fig. 13 shows an example of a next iteration, where the first reliability value is initialized and the second reliability value is maintained after an update of the second reliability value is performed as described above with reference to fig. 12. In the example of fig. 13, a C2V message is received in the next iteration, and the symbol correction unit 122b may update the first reliability value of the candidate symbol based on the number of C2V messages received by the variable node.

After updating the first reliability value, the symbol correction unit 122b may check, for each variable node, whether there is a candidate symbol having the first reliability value equal to or greater than the first threshold among the candidate symbols, and adjust the value of the variable node when there is a candidate symbol having the first reliability value equal to or greater than the first threshold. In the example of fig. 13, it is assumed that VN corresponds to a variable node₁Is set to 13 and corresponds to the variable node VN₂Is set to 12. In this case, VN is the variable node₁And VN₂May not adjust the variable node VN if there is no candidate symbol that satisfies the first threshold value among the candidate symbols of (b), the variable node VN may not be adjusted₁And VN₂The value of (c).

For each variable node whose candidate symbol does not have a first reliability value equal to or greater than a first threshold, symbol correction unit 122b may determine whether there is a candidate symbol having a first reliability value equal to or greater than a second threshold. When there is a candidate symbol having a first reliability value smaller than the first threshold value and equal to or larger than the second threshold value, the symbol correction unit 122b may update the second reliability value of the corresponding variable node. In the example of fig. 13, corresponding to variable node VN₁Is set to 11 and corresponds to the variable node VN₂Is set to 10. In this case, VN is the variable node₁And VN₂May not update the variable node VN if there is no candidate symbol satisfying the second threshold value among the candidate symbols of (b), the variable node VN may not be updated₁And VN₂The second reliability value of (1).

For each variable node whose candidate symbol does not have a first reliability value equal to or greater than a second threshold, symbol correction unit 122b may determine thatWhether there is a candidate symbol having a first reliability value equal to or greater than a third threshold. When it is determined that there is a candidate symbol having a first reliability value smaller than the second threshold value and equal to or larger than the third threshold value, the symbol correction unit 122b may update the second reliability value of the corresponding variable node. In the example of fig. 13, corresponding to variable node VN₁Is set to 9 and corresponds to the variable node VN₂Is set to 8. In this case, VN is the variable node₁Is equal to or greater than 9 (corresponding to the variable node VN)₁Third threshold of) may be updated, the variable node VN may be updated₁The second reliability value of (1). In the example of fig. 13, the set value corresponding to the third threshold is 1, and then the variable node VN₁Is updated from 2 to 3.

When the second reliability value of the variable node is updated, the symbol correction unit 122b may determine whether the updated second reliability value is equal to or greater than a fourth threshold value. The symbol correction unit 122b may adjust the value of the variable node if the updated second reliability value is equal to or greater than the fourth threshold value. Suppose corresponding to variable node VN₁Is set to 3. In this case, node VN is due to variable₁Is equal to or greater than 3 (corresponding to the variable node VN)₁Fourth threshold of) may be adjusted, the variable node VN may be adjusted₁The value of (c). Variable node VN₁May be adjusted to the candidate symbol, i.e., the candidate symbol "α" whose first reliability value caused the second reliability value to be updated in the current iteration.

Due to the fact that VN is a variable node₂Does not exist the candidate symbol satisfying the third threshold, the variable node VN may not be updated₂The second reliability value of (1).

FIG. 14 is a flow chart illustrating a method of operating an error correction circuit based on an embodiment of the disclosed technology. In some implementations, the operations shown in FIG. 14 may be performed by the error correction circuit 10 shown in FIG. 1.

In some implementations, at least one of the steps shown in fig. 14 may be omitted, and the order of the steps may be changed.

In step 1401, error correction circuit 10 may receive a read vector corresponding to a codeword.

In step 1403, the error correction circuit 10 may configure initial symbols based on the read vector, and may assign the configured initial symbols to the respective variable nodes in a one-to-one correspondence.

In step 1405, the error correction circuit 10 may initialize first reliability values of the candidate symbols that may be selected as values of the respective variable nodes based on the initial symbols assigned to the respective variable nodes. In one embodiment, the error correction circuit 10 may initialize the first reliability value of each candidate symbol differently according to a hamming distance between the initial symbol and the candidate symbol allocated to each variable node. For example, the error correction circuit 10 may initialize the first reliability value such that the shorter the hamming distance between the initial symbol and the candidate symbol, the higher the first reliability value of the candidate symbol is initialized, and the longer the hamming distance between the initial symbol and the candidate symbol, the lower the first reliability value of the candidate symbol is initialized. In one embodiment, error correction circuit 10 may initialize the first reliability value of each candidate symbol differently by considering the round of iteration. In some implementations, the first reliability value for each candidate symbol may be initialized in consideration of the round of iteration in addition to the hamming distance. In one embodiment, as the iteration round increases and the hamming distance between the initial symbol and the corresponding candidate symbol is shorter, the error correction circuit 10 may initialize the first reliability value of the candidate symbol to a higher value than in the previous iteration round. In one embodiment, error correction circuit 10 may initialize the first reliability value of the candidate symbol by considering the number of Unsatisfied Check Nodes (UCNs). In some implementations, the number of UCNs may be considered in addition to the hamming distance to initialize the first reliability value for each candidate symbol. In one embodiment, the larger the number of UCNs in the ith iteration and the shorter the hamming distance between the initial symbol and the candidate symbol, the error correction circuit 10 may initialize the first reliability value of the candidate symbol to a higher value in the (i + 1) th iteration.

In step 1407, the error correction circuit 10 may set a threshold value that is used as a criterion for determining whether to adjust the value of the variable node. In one embodiment, the error correction circuit 10 may set an initial threshold to a predetermined value, the threshold being present before the first iteration is performed. In one embodiment, the error correction circuit 10 may set the same nth threshold value for all variable nodes. For example, the same first threshold value may be set for all variable nodes, and the same second threshold value may also be set for all variable nodes. In one embodiment, the error correction circuit 10 may set the initial threshold to different values depending on the degree of the variable node. For example, the error correction circuit 10 may set the initial threshold to a higher value for variable nodes having a higher degree and set the initial threshold to a lower value for variable nodes having a lower degree. In one embodiment, the error correction circuit 10 may change at least one of the thresholds according to the round of iteration. For example, as the iteration round increases, the error correction circuit 10 may set at least one of the thresholds to a higher value. In one embodiment, the error correction circuit 10 may change at least one of the thresholds according to the number of UCNs corresponding to syndrome checks. For example, the larger the number of UCNs corresponding to the ith iteration, the higher the error correction circuit 10 may set at least one of the thresholds to a higher value in the (i + 1) th iteration.

In step 1409, the error correction circuitry 10 may perform a check node update and a variable node update. In step 1409, an exchange of C2V messages and V2C messages between the check nodes and the variable nodes may be performed.

In step 1411, the error correction circuit 10 may determine, for each variable node, whether there is a candidate symbol having a first reliability value equal to or greater than a first threshold. Step 1413 may be performed when it is determined that there is a candidate symbol having a first reliability value equal to or greater than a first threshold value (in the case of yes), and step 1421 may be performed otherwise (in the case of no). When there is a candidate symbol having a first reliability value equal to or greater than a first threshold, step 1413 is performed. When there is no candidate symbol having a first reliability value equal to or greater than the first threshold, step 1421 is performed.

In step 1413, the error correction circuit 10 may adjust the value of the variable node corresponding to the candidate symbol having the first reliability value equal to or greater than the first threshold value.

In step 1415, the error correction circuit 10 may perform syndrome checking based on the value of the variable node and may determine whether the syndrome checking has passed. When the syndrome check passes (in case of yes), step 1417 may be performed, otherwise (in case of no) step 1441 may be performed.

In step 1417, the error correction circuit 10 may output the value of the variable node that has passed the syndrome check as a decoded codeword.

When it is determined that there is no candidate symbol having the first reliability value equal to or greater than the first threshold among the candidate symbols of the variable node, step 1421 is performed, and at step 1421, the error correction circuit 10 may determine whether there is a candidate symbol having the first reliability value equal to or greater than the second threshold among the candidate symbols of the corresponding variable node. Step 1423 may be performed when it is determined that there is a candidate symbol having a first reliability value equal to or greater than the second threshold value among the candidate symbols of the corresponding variable node (in the case of "yes"), and step 1415 may be performed otherwise (in the case of "no").

In step 1423, the error correction circuit 10 may check whether a second reliability value is set in the variable node. Step 1425 may be performed when the second reliability value is set in the variable node (in case of yes), otherwise step 1431 may be performed (in case of no).

In step 1425, the error correction circuit 10 may adjust the value of the variable node to candidate symbols having a first reliability value equal to or greater than the second threshold.

At step 1427, the error correction circuit 10 may initialize a second reliability value corresponding to the variable node whose value has been adjusted at step 1425. Thereafter, step 1415 may be performed.

When it is determined in step 1423 that the second reliability value is not set, step 1431 is performed, and in step 1431, the error correction circuit 10 may set the second reliability value in the correspondent variable node. Thereafter, step 1415 may be performed.

When it is determined in step 1415 that the syndrome check has not been passed, step 1441 is performed, and in step 1441, the error correction circuit 10 may determine whether the number of iterations performed reaches the maximum number of iterations I. When the number of iterations performed reaches the maximum number of iterations I (in case of yes), step 1443 is performed to output a fail signal. When it is determined that the number of iterations performed does not reach the maximum number of iterations I (in the case of no), an I +1 th iteration may be performed at step 1451.

FIG. 15 is a flow chart illustrating a method of operating an error correction circuit based on an embodiment of the disclosed technology.

In the example of fig. 15, the description of the operation that has been described with reference to fig. 14 will be omitted. For example, step 1501, step 1503, step 1505, step 1507, step 1509, step 1511, step 1513, step 1515, step 1517, step 1541, step 1543 and step 1551 in fig. 15 may be performed in the same manner as step 1401, step 1403, step 1405, step 1407, step 1409, step 1411, step 1413, step 1415, step 1417, step 1441, step 1443 and step 1451 in fig. 14.

When it is determined in step 1511 that there is no candidate symbol having the first reliability value equal to or greater than the first threshold among the candidate symbols of the variable node to perform step 1521, the error correction circuit 10 may determine in step 1521 whether there is a candidate symbol having the first reliability value equal to or greater than the second threshold to the n-1 th threshold (where n is a natural number of 4 or greater) among the candidate symbols of the corresponding variable node. Such determinations may be performed sequentially from a higher threshold, i.e., in order from the second threshold to the n-1 th threshold. Upon determining that there is a candidate symbol having the first reliability value equal to or greater than any one of the second to n-1 th thresholds among the candidate symbols, the determining step may stop without performing the determination for the remaining thresholds. For example, if the correspondent variable node has candidate symbols having the first reliability value equal to or greater than the second threshold value, the determination of whether there is a candidate symbol having the first reliability value equal to or greater than the third threshold value through the n-1 th threshold value among the candidate symbols may not be performed. When it is determined that there are candidate symbols having the first reliability values equal to or greater than the second to n-1 th thresholds among the candidate symbols of the corresponding variable node (in case of yes), step 1523 may be performed, otherwise (in case of no), step 1515 may be performed.

At step 1523, error correction circuit 10 may update the second reliability value of the variable node. For example, the error correction circuit 10 may increase the second reliability value of the variable node by a set value corresponding to the highest threshold value that the first reliability value satisfies. For example, when there is a candidate symbol having a first reliability value equal to or greater than the second threshold value, the error correction circuit 10 may increase the second reliability value of the corresponding variable node by the first set value. Further, when there is a candidate symbol having a first reliability value equal to or greater than the third threshold value and less than the second threshold value, the error correction circuit may increase the second reliability value of the correspondent variable node by a second set value, the second set value being less than the first set value.

At step 1525, the error correction circuit 10 may determine whether the updated second reliability value is greater than the nth threshold value. Step 1527 may be performed when the updated second reliability value is greater than the nth threshold value (in case of yes), otherwise step 1515 may be performed (in case of no).

At step 1527, error correction circuit 10 may adjust the value of the variable node. For example, the error correction circuit 10 may adjust the value of the correspondent variable node to a candidate symbol whose first reliability value causes the second reliability value to be updated in the current iteration.

At step 1529, error correction circuit 10 may initialize a second reliability value for the variable node, the value of the variable node having been adjusted based on the second reliability value. Thereafter, step 1515 may be performed.

FIG. 16 is a diagram illustrating a memory system to which embodiments of the disclosed technology are applied.

Referring to fig. 16, the memory system 2000 may include a memory device 2200 storing data and a memory controller 2100 controlling the memory device 2200 under the control of a host 1000.

The host 1000 is capable of communicating with the memory system 2000 using an interface protocol, such as peripheral component interconnect express (PCI-E), Advanced Technology Attachment (ATA), Serial ATA (SATA), parallel ATA (PATA), or Serial Attached SCSI (SAS). The interface protocol used between the host 1000 and the memory system 2000 is not limited to the above example, and other interface protocols such as Universal Serial Bus (USB), Multi Media Card (MMC), Enhanced Small Disk Interface (ESDI), or Integrated Drive Electronics (IDE) interface protocol may be used.

The memory controller 2100 may control the overall operation of the memory system 2000 and may control data exchange between the host 1000 and the memory device 2200.

The memory controller 2100 may include a host interface 2110, a Central Processing Unit (CPU)2120, a memory interface 2130, a buffer memory 2140, an error correction circuit 2150, and an internal memory 2160. The host interface 2110, the memory interface 2130, the buffer memory 2140, the error correction circuit 2150, and the internal memory 2160 may be controlled by the CPU 2120.

Host interface 2110 may exchange data with host 1000 using a communications protocol.

CPU 2120 may perform various types of calculations or generate commands and addresses in order to control memory device 2200. For example, the CPU 2120 may generate various commands necessary for a program operation, a read operation, an erase operation, a data compression operation, and a copy-back operation.

The memory interface 2130 may communicate with the memory device 2200 using a communication protocol.

The buffer memory 2140 can temporarily store data while the memory controller 2100 controls the memory device 2200. For example, data received from the host may be temporarily stored in the buffer memory 2140 before the programming operation is completed. Further, during a read operation, data read from the memory device 2200 may also be temporarily stored in the buffer memory 2140.

The error correction circuit 2150 may perform encoding and decoding for error correction during a program operation or a read operation. The error correction circuit 2150 may be an error correction circuit using a non-binary LDPC (NB-LDPC) code.

Error correction circuit 2150 may include error correction decoder 2152 and post-processor 2154.

Error correction decoder 2152 may perform error correction decoding on the read data received from memory device 2200. When an error is detected in the iterative decoding process for error correction, the error correction decoder 2152 may correct the error using the parity check matrix. For example, error correction decoder 2152 may calculate a syndrome corresponding to the read data based on the parity check matrix, and may determine whether an error is included in the read data based on the calculated syndrome. When an error contained in the read data is correctable, the error correction decoder 2152 may correct the error and output the error-corrected data. When an error contained in the read data is uncorrectable, the error correction decoder 2152 may report a decoding failure to the CPU 2120.

Error correction decoder 2152 may include a symbol configuration unit 2152a, a node processor 2152b, and a syndrome check unit 2152 c. Error correction decoder 2152 may perform the same or similar operations as error correction decoder 100 described above with reference to fig. 1. For example, symbol configuration unit 2152a, node processor 2152b, and syndrome check unit 2152c shown in fig. 16 may perform operations corresponding to symbol configuration unit 110, node processor 120, and syndrome check unit 130, respectively, shown in fig. 1.

Post-processor 2154 may perform operations corresponding to post-processor 200 shown in fig. 1.

The internal memory 2160 may be used as a storage unit that stores various types of information necessary for the operation of the memory controller 2100. The internal memory 2160 may store a plurality of tables. For example, internal memory 2160 may store a mapping table for mapping between logical addresses and physical addresses.

The memory device 2200 may perform a program operation, a read operation, an erase operation, a data compression operation, and a copy-back operation under the control of the memory controller 2100. The memory device 2200 may be implemented as a volatile memory device in which stored data is lost when power supply is interrupted, or as a non-volatile memory device in which stored data is maintained even when power supply is interrupted.

Fig. 17 is a diagram illustrating a memory device based on an embodiment of the disclosed technology. The memory device shown in fig. 17 can be applied to the memory system of fig. 16.

The memory device 2200 may include control logic 2210, peripheral circuitry 2220, and a memory cell array 2240. The peripheral circuits 2220 may include a voltage generation circuit 2222, a row decoder 2224, input/output circuits 2226, a column decoder 2228, a page buffer group 2232, and a current sensing circuit 2234.

The control logic 2210 may control the peripheral circuits 2220 under the control of the memory controller 2100 of fig. 16.

The control logic 2210 may control the peripheral circuits 2220 in response to commands CMD and addresses ADD received from the memory controller 2100 through the input/output circuits 2226. For example, the control logic 2210 may output an operation signal OP _ CMD, a row address RADD, a column address CADD, a page buffer control signal PBSIGNALS, and an enable BIT VRY _ BIT < # > in response to a command CMD and an address ADD. Control logic 2210 may determine whether the verify operation passed or failed in response to PASS signal PASS or FAIL signal FAIL received from current sensing circuit 2234.

The peripheral circuit 2220 can perform a program operation of storing data in the memory cell array 2240, a read operation of outputting data stored in the memory cell array 2240, and an erase operation of erasing data stored in the memory cell array 2240.

The voltage generation circuit 2222 may generate various operation voltages Vop for program, read, and erase operations in response to the operation signal OP _ CMD received from the control logic 2210. For example, the voltage generation circuit 2222 may transmit a program voltage, a verify voltage, a pass voltage, a read voltage, an erase voltage, a turn-on voltage, and the like to the row decoder 2224.

The row decoder 2224 may transfer the operation voltage Vop to a local line LL coupled to a memory block selected from among memory blocks included in the memory cell array 2240 in response to a row address RADD received from the control logic 2210. The local lines LL may include local word lines, local drain select lines, and local source select lines. In addition, the local lines LL may include various lines coupled to the memory blocks, such as source lines.

Input/output circuit 2226 may transfer commands CMD and addresses ADD received from the memory controller via input/output (IO) lines to control logic 2210, or may exchange data with column decoder 2228.

The column decoder 2228 may transfer data between the input/output circuit 2226 and the page buffer set 2232 in response to a column address CADD received from the control logic 2210. For example, the column decoder 2228 may exchange data with the page buffers PB1 to PBm through the data lines DL, or may exchange data with the input/output circuit 2226 through the column lines CL.

The page buffer group 2232 may be coupled to bit lines BL1 through BLm commonly coupled with the memory blocks BLK1 through BLKi. The page buffer group 2232 may include a plurality of page buffers PB1 to PBm coupled to bit lines BL1 to BLm, respectively. For example, one page buffer may be coupled to each bit line. The page buffers PB1 through PBm may be operated in response to page buffer control signals PBSIGNALS received from the control logic 2210. For example, during a program operation, the page buffers PB1 to PBm may temporarily store program data received from a memory controller, and may control voltages to be applied to the bit lines BL1 to BLm based on the program data. Further, during a read operation, the page buffers PB1 to PBm may temporarily store data received through the bit lines BL1 to BLm, or may sense voltages or currents of the bit lines BL1 to BLm.

During a read operation or a verify operation, the current sensing circuit 2234 may generate a reference current in response to the enable BIT VRY _ BIT < # > received from the control logic 2210, and may compare a reference voltage generated by the reference current with the sensing voltage VPB received from the page buffer group 2232 and then output a PASS signal PASS or a FAIL signal FAIL.

The memory cell array 2240 may include a plurality of memory blocks BLK1 through BLKi storing data. In the memory blocks BLK1 through BLKi, user data and various types of information required for the operation of the memory device 2200 may be stored. The memory blocks BLK1 through BLKi may each be implemented as a two-dimensional (2D) structure or a three-dimensional (3D) structure, and may be equally configured.

Fig. 18 is a diagram showing an example of a memory block.

The memory cell array may include a plurality of memory blocks, and any one of the plurality of memory blocks BLKi is illustrated in fig. 18 for convenience of description.

A plurality of word lines arranged parallel to each other between the first and second select lines may be coupled to the memory block BLKi. The first selection line may be a source selection line SSL, and the second selection line may be a drain selection line DSL. In detail, the memory block BLKi may include a plurality of strings ST coupled between the bit lines BL1 through BLm and the source lines SL. The bit lines BL1 through BLm may be respectively coupled to the strings ST, and the source lines SL may be commonly coupled to the strings ST. The strings ST may be equally configured, and this will describe in detail the strings ST coupled to the first bit line BL1 by way of example.

The string ST may include a source select transistor SST, a plurality of memory cells F1 through F16, and a drain select transistor DST, which are coupled in series with each other between a source line SL and a first bit line BL 1. The single string ST may include at least one source selection transistor SST and at least one drain selection transistor DST. In some implementations, more memory cells than the memory cells F1 through F16 shown in the figure may be included in string ST.

A source of the source select transistor SST may be coupled to a source line SL, and a drain of the drain select transistor DST may be coupled to a first bit line BL 1. The memory cells F1 through F16 may be coupled in series between a source select transistor SST and a drain select transistor DST. The gates of the source select transistors SST included in different strings ST may be coupled to a source select line SSL, the gates of the drain select transistors DST included in different strings ST may be coupled to a drain select line DSL, and the gates of the memory cells F1 through F16 may be coupled to a plurality of word lines WL1 through WL16, respectively. Among the memory cells included in different strings ST, a group of memory cells coupled to the same word line may be referred to as a "physical page: PPG ". Accordingly, the memory block BLKi may include a plurality of physical pages PPG as many as the number of word lines WL1 to WL 16.

One memory cell can store one bit of data. This cell is called a single-level cell (SLC). Here, one physical page PPG may store data corresponding to one logical page LPG. The data corresponding to one logical page LPG may include a number of data bits as many as the number of cells included in one physical page PPG. For example, when two or more bits of data are stored in one memory unit, one physical page PPG may store data corresponding to two or more logical pages LPG. For example, in a memory device driven in MLC type, data corresponding to two logical pages may be stored in one physical page PPG. In a memory device driven in the TLC type, data corresponding to three logical pages may be stored in one physical page PPG.

FIG. 19 is a diagram illustrating an embodiment of a memory system including the memory controller of FIG. 16.

Referring to fig. 19, the memory system 30000 may be implemented as a cellular phone, a smart phone, a tablet computer, a Personal Computer (PC), a Personal Digital Assistant (PDA), or a wireless communication device. The memory system 30000 may include a memory device 2200 and a memory controller 2100 capable of controlling the operation of the memory device 2200.

The memory controller 2100 may control data access operations, such as program, erase, or read operations, of the memory device 2200 under the control of the processor 3100.

Under the control of the memory controller 2100, data programmed in the memory device 2200 may be output through the display 3200.

The radio transceiver 3300 may transmit and receive a radio signal through an antenna ANT. For example, the radio transceiver 3300 may change a radio signal received through the antenna ANT into a signal that may be processed by the processor 3100. Accordingly, the processor 3100 may process a signal output from the radio transceiver 3300 and transmit the processed signal to the memory controller 2100 or the display 3200. The memory controller 2100 may transmit signals processed by the processor 3100 to the memory device 2200. Further, the radio transceiver 3300 may change a signal output from the processor 3100 into a radio signal and output the changed radio signal to an external device through an antenna ANT. The input device 3400 may be used to input control signals for controlling the operation of the processor 3100 or data to be processed by the processor 3100. The input device 3400 may be implemented as a pointing device such as a touch pad or a computer mouse, a keypad, or a keyboard. The processor 3100 may control the operation of the display 3200 such that data output from the memory controller 2100, data output from the radio transceiver 3300, or data output from the input device 3400 is output through the display 3200.

In one embodiment, the memory controller 2100 capable of controlling the operation of the memory device 2200 may be implemented as part of the processor 3100 or as a chip provided separately from the processor 3100.

FIG. 20 is a diagram illustrating an embodiment of a memory system including the memory controller of FIG. 16.

Referring to fig. 20, the memory system 70000 may be implemented as a memory card or a smart card. The memory system 70000 may include a memory device 2200, a memory controller 2100, and a card interface 7100.

The memory controller 2100 may control data exchange between the memory device 2200 and the card interface 7100. In one embodiment, the card interface 7100 may be a Secure Digital (SD) card interface or a multimedia card (MMC) interface, but is not limited thereto.

The card interface 7100 may interface data exchanges between the host 60000 and the memory controller 2100 according to the protocol of the host 60000. In one embodiment, card interface 7100 may support the Universal Serial Bus (USB) protocol and the inter-chip (IC) -USB protocol. Here, the card interface 7100 may refer to hardware capable of supporting a protocol used by the host 60000, software installed in hardware, or a signal transmission method.

When the memory system 70000 is connected to a host interface 6200 of a host 60000 such as a PC, a tablet computer, a digital camera, a digital audio player, a cellular phone, console video game hardware, or a digital set-top box, the host interface 6200 can be in data communication with the memory device 2200 through the card interface 7100 and the memory controller 2100 under the control of a microprocessor (μ P) 6100.

According to the disclosed technology, the performance of an error correction circuit using an NB-LDPC code can be improved.

Although exemplary embodiments of the disclosed technology have been disclosed for illustrative purposes, those skilled in the art will appreciate that various modifications, additions and substitutions are possible. Accordingly, the scope of the disclosed technology must be determined by the appended claims and equivalents of the claims, rather than by the foregoing description.