阅读说明：本技术 一种基于RapidIO网络的路由表生成方法 (Method for generating routing table based on RapidIO network ) 是由 彭文攀 朱会柱 王洋 段冰冰 吴敏 吴亦航 于 2019-12-10 设计创作，主要内容包括：本发明提供一种基于RapidIO网络的路由表生成方法，是一种针对板级RapidIO系统网络的查找及路由分配策略，该查找分配策略优化了网络深度查找算法，使用树状重定义递归查找策略，加入网络监控实时的路由延迟权值算法，提升了网络的传输能力及降低网络平均延迟方差，适用于航空数据总线传输协议开发领域，提升航空电子系统内部RapidIO网络通信性能，能实时的查找更新网络拓扑结构，提升网络通信吞吐量，降低网络拥堵概率，降低网络传输延迟，提升网络查找通信的可靠性。(The invention provides a routing table generation method based on a RapidIO network, which is a searching and routing distribution strategy aiming at a board-level RapidIO system network, wherein the searching and distribution strategy optimizes a network depth searching algorithm, uses a tree redefinition recursion searching strategy, adds a real-time routing delay weight algorithm for network monitoring, improves the transmission capability of the network and reduces the average delay variance of the network, is suitable for the field of aviation data bus transmission protocol development, improves the RapidIO network communication performance in an aviation electronic system, can search and update a network topology structure in real time, improves the network communication throughput, reduces the network congestion probability, reduces the network transmission delay and improves the reliability of network searching communication.)

1. A method for generating a routing table based on a RapidIO network is characterized in that the RapidIO network comprises at least one switching chip and at least one node, and each node is connected to one switching chip; the method comprises the following steps:

step one, making the value of the hop number of the maintenance hop be 0, and making the value of i be 1;

step two, adding the switching chip connected with the master control root node into a switching device list, and determining that the traversal state of the ith switching chip is a non-traversal state; the ith exchange chip is an ith exchange chip added into the exchange equipment list;

step three, setting the traversal state of the ith exchange chip to be a traversal state;

step four, traversing all ports of the ith exchange chip, and adding the terminal equipment connected to the port of the ith exchange chip into the adjacent equipment list of the ith exchange chip; determining the traversal state of a switching chip connected to a port of an ith switching chip, and adding the switching chip connected to the port of the ith switching chip into a switching device list and an adjacent device list of the ith switching chip when the traversal state is a non-traversal state; when the traversal state is the traversed state, adding the switching chip connected to the port of the ith switching chip into the adjacent equipment list of the ith switching chip; setting the traversal state of the ith exchange chip to be a traversed state;

step five, judging whether a switching chip in an unretraversed state exists in the switching equipment list or not; if yes, executing step six; if not, executing the step nine;

step six, adding 1 to the hop count of the maintenance hop, and determining the hop count N of the search route; the N is the number of the switching chips in the non-traversal state in the switching equipment list; the value of N is a positive integer;

step seven, adding 1 to the value of i, and executing the step three and the step four;

step eight, judging whether the value of i reaches N; if yes, executing a fifth step; if not, executing the step seven;

and step nine, generating a routing table according to the switching equipment list and the adjacent equipment list of each switching chip.

2. The method of claim 1, wherein generating a routing table according to the switching device list and the neighbor device list of each switching chip comprises:

generating at least one virtual network according to the sequence from the back to the front of the exchange equipment list and the adjacent equipment list of each exchange chip;

and generating a routing table according to the connection relation of each virtual network.

3. The method of claim 2, further comprising:

generating a weight value of each virtual network according to maintenance data packets sent and received by each virtual network;

and correcting the routing table according to the weight value of each virtual network.

4. The method of claim 3, wherein modifying the routing table according to the weight of each virtual network comprises:

when the weight of the virtual network is abnormal, deleting the switching chip of the virtual network with the abnormal weight from the virtual network with the abnormal weight to obtain a modified virtual network;

and generating a routing table according to the modified virtual network.

5. The method according to claim 3, wherein the generating the weight of each virtual network according to the maintenance data packet sent and received by each virtual network comprises:

determining the bandwidth m and the average time delay t between each virtual network and the respective adjacent virtual network according to the maintenance data packets sent and received between each virtual network and the respective adjacent virtual network;

generating the weight of each virtual network according to the number n of the internal nodes of each virtual network, the bandwidth m, the average time delay t and the hop count h of each virtual network and the respective adjacent virtual network

6. The method of claim 1, wherein the generating at least one virtual network according to the order from back to front of the switch device list and according to the neighbor device list of each switch chip comprises:

determining whether the number of adjacent switching chips of the first switching chip is 1; the first switching chip is a switching chip which is not added into the virtual network and is added into the switching equipment list at last;

if the number of adjacent switching chips of a first switching chip is 1, establishing a first virtual network corresponding to the first switching chip, adding the first switching chip and a second switching chip into the first virtual network, further judging whether the number of the adjacent switching chips of the second switching chip is 1, if so, adding a third switching chip into the first virtual network, further judging whether the number of the adjacent switching chips of the third switching chip is 1, and until switching chips with the number of the adjacent switching chips not being 1 are touched; the second exchange chip is an adjacent exchange chip of the first exchange chip; and the third exchange chip is an adjacent exchange chip of the second exchange chip.

7. The method of claim 1, wherein step three further comprises:

and locking the ith exchange chip, wherein the routing table of the locked exchange chip cannot be changed.

8. The method of claim 1, further comprising:

and during initialization, the traversal state of each switching chip included in the RapidIO network is a non-traversal state.

Technical Field

The invention relates to the technical field of avionic information integrated network buses, in particular to a routing table generation method based on a RapidIO network.

Background

The aerial optical RapidIO network protocol is an interconnection standard of an international generalized embedded system, provides reliable transmission performance, and supports point-to-point and point-to-multipoint transmission modes. In the aspect of hardware, a small pin number is used, and a connection structure based on interconnection and intercommunication of data packet exchange meets the requirement of low time delay of an embedded system and supports transmission from a chip to the chip.

The RapidIO network protocol is composed of three layers of protocols, including a logic layer, a transmission layer and a physical layer, wherein the three layers of protocols mainly describe the format of a protocol frame, necessary information, flow control and electrical characteristics of a data packet transmission channel, a low-level error management strategy and the like.

When a routing table is generated in the conventional RapidIO network, a deep linear type search algorithm is usually adopted, but the RapidIO network is complex in topological structure, and the problem that the protocol advantage of the RapidIO network with low time delay cannot be fully played due to the adoption of the deep linear type search algorithm exists.

Disclosure of Invention

The embodiment of the invention provides a method for generating a routing table based on a RapidIO network, which can quickly and reliably search RapidIO network nodes.

The embodiment of the invention provides a routing table generation method based on a RapidIO network, wherein the RapidIO network comprises at least one exchange chip and at least one node, and each node is connected to one exchange chip; the method for generating the routing table comprises the following steps:

step one, making the value of the hop number of the maintenance hop be 0, and making the value of i be 1;

step two, adding the switching chip connected with the master control root node into a switching device list, and determining that the traversal state of the ith switching chip is a non-traversal state; the ith exchange chip is an ith exchange chip added into the exchange equipment list;

step three, setting the traversal state of the ith exchange chip to be a traversal state;

step four, traversing all ports of the ith exchange chip, and adding the terminal equipment connected to the port of the ith exchange chip into the adjacent equipment list of the ith exchange chip; determining the traversal state of a switching chip connected to a port of an ith switching chip, and adding the switching chip connected to the port of the ith switching chip into a switching device list and an adjacent device list of the ith switching chip when the traversal state is a non-traversal state; when the traversal state is the traversed state, adding the switching chip connected to the port of the ith switching chip into the adjacent equipment list of the ith switching chip; setting the traversal state of the ith exchange chip to be a traversed state;

step five, judging whether a switching chip in an unretraversed state exists in the switching equipment list or not; if yes, executing step six; if not, executing the step nine;

step six, adding 1 to the hop count of the maintenance hop, and determining the hop count N of the search route; the N is the number of the switching chips in the non-traversal state in the switching equipment list; the value of N is a positive integer;

step seven, adding 1 to the value of i, and executing the step three and the step four;

step eight, judging whether the value of i reaches N; if yes, executing a fifth step; if not, executing the step seven;

and step nine, generating a routing table according to the switching equipment list and the adjacent equipment list of each switching chip.

Optionally, the generating a routing table according to the switching device list and the neighbor device list of each switching chip includes:

generating at least one virtual network according to the sequence from the back to the front of the exchange equipment list and the adjacent equipment list of each exchange chip;

and generating a routing table according to the connection relation of each virtual network.

Optionally, the method for generating a routing table further includes:

generating a weight value of each virtual network according to maintenance data packets sent and received by each virtual network;

and correcting the routing table according to the weight value of each virtual network.

Optionally, the modifying the routing table according to the weight of each virtual network includes:

when the weight of the virtual network is abnormal, deleting the switching chip of the virtual network with the abnormal weight from the virtual network with the abnormal weight to obtain a modified virtual network;

and generating a routing table according to the modified virtual network.

Optionally, the generating a weight of each virtual network according to the maintenance data packet sent and received by each virtual network includes:

determining the bandwidth m and the average time delay t between each virtual network and the respective adjacent virtual network according to the maintenance data packets sent and received between each virtual network and the respective adjacent virtual network;

generating the weight of each virtual network according to the number n of the internal nodes of each virtual network, the bandwidth m, the average time delay t and the hop count h of each virtual network and the respective adjacent virtual network

K is the number of adjacent networks of the virtual network, and j takes a positive integer from 1 to K.

Optionally, the generating at least one virtual network according to the sequence from the back to the front of the switching device list and according to the adjacent device list of each switching chip includes:

determining whether the number of adjacent switching chips of the first switching chip is 1; the first switching chip is a switching chip which is not added into the virtual network and is added into the switching equipment list at last;

if the number of adjacent switching chips of a first switching chip is 1, establishing a first virtual network corresponding to the first switching chip, adding the first switching chip and a second switching chip into the first virtual network, further judging whether the number of the adjacent switching chips of the second switching chip is 1, if so, adding a third switching chip into the first virtual network, further judging whether the number of the adjacent switching chips of the third switching chip is 1, and until switching chips with the number of the adjacent switching chips not being 1 are touched; the second exchange chip is an adjacent exchange chip of the first exchange chip; and the third exchange chip is an adjacent exchange chip of the second exchange chip.

Optionally, the third step in the routing table generating method further includes:

and locking the ith exchange chip, wherein the routing table of the locked exchange chip cannot be changed.

Optionally, the method for generating a routing table further includes:

and during initialization, the traversal state of each switching chip included in the RapidIO network is a non-traversal state.

The routing table generation method based on the RapidIO network provided by the invention adopts a tree redefinition recursive search distribution algorithm, can quickly and reliably detect the topology switching structure of the whole network, and improves the network communication quality and reduces the network communication time delay by establishing a proper virtual interactive network. Meanwhile, a real-time monitoring weight strategy is adopted to adapt to the change of dynamic service data flow of the network, and the average variance of network delay is reduced by changing the number of sub-nodes at the edge of the virtual internal network and the distribution of hot spot exchange routes.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to these drawings without creative efforts.

Fig. 1 is a schematic flow chart of a routing table generation method based on a RapidIO network according to an embodiment of the present invention;

fig. 2 is a schematic structural diagram of a RapidIO network according to an embodiment of the present invention;

fig. 3 is a schematic diagram of virtual network establishment according to an embodiment of the present invention;

fig. 4 is a schematic structural diagram of a maintenance frame according to an embodiment of the present invention.

Detailed Description

Fig. 1 is a schematic flow diagram of a method for generating a routing table based on a RapidIO network according to an embodiment of the present invention, and fig. 2 is a schematic structural diagram of the RapidIO network according to an embodiment of the present invention. As shown in fig. 1 and 2, an execution main body of the method for generating a routing table based on a RapidIO network according to the embodiment of the present invention may be a device for generating a routing table based on a RapidIO network, and the device may be integrated on a master control root node in the RapidIO network, or may directly adopt a control module on the master control root node. Fig. 2 illustrates an exemplary method for generating a routing table based on a RapidIO network, which is provided by the present invention, by taking an example that the RapidIO network includes 6 child nodes. Each node in the RapidIO network in fig. 2 is connected to one switch chip, each switch chip comprising 6 ports. It will be appreciated that multiple nodes may be connected on each switch chip.

The method for generating the routing table based on the RapidIO network comprises the following steps:

step one, making the value of the hop number of the maintenance hop be 0, and making the value of i be 1;

step two, adding the switching chip connected with the master control root node into a switching device list, and determining that the traversal state of the ith switching chip is a non-traversal state; the ith exchange chip is an ith exchange chip added into the exchange equipment list;

step three, setting the traversal state of the ith exchange chip as a traversing state;

step four, traversing all ports of the ith exchange chip, and adding the terminal equipment connected to the port of the ith exchange chip into the adjacent equipment list of the ith exchange chip; determining the traversal state of the switching chip connected to the port of the ith switching chip, and adding the switching chip connected to the port of the ith switching chip into the switching device list and the adjacent device list of the ith switching chip when the traversal state is not the traversal state; when the traversal state is the traversed state, adding the switching chip connected to the port of the ith switching chip into the adjacent equipment list of the ith switching chip; setting the traversal state of the ith exchange chip as a traversed state;

the switching devices added in the switching device list are subtrees of the ith switching chip, and can independently form a maintenance cluster by taking the ith switching chip as a cluster head.

Step five, judging whether a switching chip in an unretraversed state exists in the switching equipment list or not; if yes, executing step six; if not, executing the step nine;

step six, adding 1 to the hop count of the maintenance hop, and determining the hop count N of the search route; n is the number of the switching chips in the non-traversal state in the switching equipment list; the value of N is a positive integer;

step seven, adding 1 to the value of i, and executing the step three and the step four;

step eight, judging whether the value of i reaches N; if yes, executing a fifth step; if not, executing the step seven;

and step nine, generating a routing table according to the switching equipment list and the adjacent equipment list of each switching chip.

The method adopts tree recursive search, and carries out network node search through the maintenance port, so as to avoid the unbalanced route search generated by the loop network.

The apparatus for generating a routing table based on a RapidIO network may further include: the node redefines the virtual sub-network allocation module.

The node redefining virtual sub-network distribution module is used for generating at least one virtual network according to the sequence from back to front of the switching equipment list and the adjacent equipment list of each switching chip; and generating a routing table according to the connection relation of each virtual network.

Fig. 3 is a schematic diagram of virtual network establishment according to an embodiment of the present invention, and as shown in fig. 3, the nodes redefine the virtual network allocation module to reduce network congestion and network transmission delay. The number of redefined switching chips is related to the number of switching chips in the vicinity of the node, the switching chips on each network having at least one redefined identity.

For example, the node redefinition virtual sub-network allocation module determines whether the number of neighboring switch chips of the first switch chip is 1; the first exchange chip is an exchange chip which is not added into the virtual network and is added into the exchange equipment list at last;

if the number of the adjacent exchange chips of the first exchange chip is 1, establishing a first virtual network corresponding to the first exchange chip, adding the first exchange chip and the second exchange chip into the first virtual network, further judging whether the number of the adjacent exchange chips of the second exchange chip is 1, if so, adding a third exchange chip into the first virtual network, further judging whether the number of the adjacent exchange chips of the third exchange chip is 1, and until meeting the exchange chips with the number of the adjacent exchange chips not being 1; the second exchange chip is an adjacent exchange chip of the first exchange chip; the third exchange chip is adjacent exchange chip of the second exchange chip.

If only one adjacent exchange chip II is arranged in the exchange chip IV in the figure 3, the exchange chip IV is redefined as IV 1 terminal equipment to the exchange chip II. Meanwhile, the exchange chip II has only one adjacent exchange chip III, so that the exchange chip II is redefined into the terminal equipment II 1 to the exchange chip III, and a virtual network 1 is established. Fig. 2 shows the routing ports of the communication between the switch chip i, the switch chip v and the virtual network 1.

Illustratively, if the number of neighboring switch chips of the first switch chip is not 1 or the switch chip with the number of neighboring switch chips not 1 is hit, virtualizing P re-egress nodes according to the number P of neighboring switch chips of the switch chip, and adding the P re-egress nodes into P virtual networks respectively.

For example, there are two neighboring switch chips, two virtual re-partition nodes are created for the switch chip v, one virtual re-partition node joins the virtual network 1, and the other virtual re-partition node and the neighboring switch chip i form the virtual network 2, as shown in fig. 3. For example, it is further determined whether there is a switch chip still not belonging to any virtual network in the adjacent switch chips of the virtual network 2, and if so, the number of the adjacent switch chips of the switch chip is determined, and the switch chip is added to the appropriate virtual network according to whether the number of the adjacent switch chips is 1.

In fig. 3, the number of neighboring virtual networks of any virtual network is k, the number of child nodes inside each virtual network is n, the bandwidth of the externally-exchanged data stream of the virtual network is m, the average time delay of the externally-exchanged data of the virtual network is t, and the internal hop count of the virtual network is h. For example, the neighboring virtual network data of the virtual networks 1 and 2 are both 1, the number of internal child nodes of the virtual network 1 is 4, the number of internal child nodes of the virtual network 2 is 2, the internal hop count from the virtual network 1 to the virtual network 2 is h, and h is (0+0+1+2)/4+ 1. It can be understood that, when the virtual network 1 has other adjacent virtual networks connected through other switch chips, the switch chip for connection is taken as hop count 0, and the hop count from the virtual network 1 to the other adjacent virtual networks is calculated. Weight of virtual network

m_jRepresenting the bandwidth from the current virtual network to the jth neighbor virtual network, h_jRepresenting the number of hops from the current virtual network to the jth neighbor virtual network, t_jRepresenting the average delay from the current virtual network to the jth neighbor virtual network.

The apparatus for generating a routing table based on a RapidIO network may further include: and monitoring a weight loop module.

Establishing a monitoring state of internal weights of virtual sub-networks, observing specific time delay and data bandwidth of virtual packets through a maintenance interface, and calculating the internal weights of the whole virtual network, wherein fig. 4 is a schematic structural diagram of a maintenance frame provided by an embodiment of the present invention, and as shown in fig. 4, the internal weights of the virtual networks can be determined according to the maintenance frame sent and received between the virtual networks.

Illustratively, the weight of the virtual network can be changed by increasing or decreasing the number of the edge switching chips in the virtual network, and if the time delay of a data packet is increased due to overlarge internal flow of a certain virtual network and the calculated weight is far larger than that of an adjacent virtual network, the same heavy node is divided into adjacent nodes, so that the data flow of the internal network is reduced. The edge switching chip is a switching chip directly connected with other virtual networks. When edge switch chips are reduced, the edge switch chip that last joined the virtual network may be selected.