Solid-state imaging device, method for driving solid-state imaging device, and electronic apparatus
阅读说明：本技术 固态摄像装置、固态摄像装置的驱动方法、以及电子设备 (Solid-state imaging device, method for driving solid-state imaging device, and electronic apparatus ) 是由 盛一也 高柳功 田中俊介 大高俊德 安田直人 于 2018-06-29 设计创作，主要内容包括：像素PXL的结构包含饱和电容比及灵敏度比不同的第一光电二极管PDSL及第二光电二极管PSLS、将各光电二极管的积累电荷传输至浮置扩散层FD的传输晶体管TGSL?Tr、TGLS?Tr、以及可根据电容变更信号而变更浮置扩散层的电容的电容可变部80。第一光电二极管PDSL的第一饱和电容小于第二光电二极管PDLS的第二饱和电容，第一光电二极管PDSL的第一灵敏度大于第二光电二极管PDLS的第二灵敏度。根据该结构，能够实现大动态范围化并防止读取噪声的影响，进而可提高画质。(The pixel PXL includes a first photodiode PDSL and a second photodiode PSLS having different saturation capacitance ratios and sensitivity ratios, transfer transistors TGSL-Tr and TGLS-Tr for transferring charges accumulated in the respective photodiodes to the floating diffusion layer FD, and a capacitance varying unit 80 for varying the capacitance of the floating diffusion layer in response to a capacitance varying signal. A first saturation capacitance of the first photodiode PDSL is less than a second saturation capacitance of the second photodiode PDLS, and a first sensitivity of the first photodiode PDSL is greater than a second sensitivity of the second photodiode PDLS. According to this configuration, it is possible to realize a wide dynamic range, prevent the influence of read noise, and improve image quality.)
1. A solid-state image pickup device characterized in that:
includes a pixel portion in which pixels are arranged,
the pixel includes:
at least one first photoelectric conversion portion that accumulates, during an accumulation period, electric charges generated by photoelectric conversion;
at least one second photoelectric conversion portion that accumulates, during an accumulation period, electric charges generated by photoelectric conversion;
at least one first transfer element that can transfer the electric charge accumulated by the first photoelectric conversion portion during a specified transfer period;
at least one second transfer element that can transfer the electric charge accumulated by the second photoelectric conversion portion during a specified transfer period;
a floating diffusion layer that transfers the electric charge accumulated in at least one of the first photoelectric conversion portion and the second photoelectric conversion portion through at least one of the first transfer element and the second transfer element;
a source follower element that converts the charge of the floating diffusion layer into a voltage signal with a gain corresponding to an amount of charge; and
a capacitance varying section for varying the capacitance of the floating diffusion layer in response to a capacitance varying signal,
the first photoelectric conversion portion has a first saturation capacitance and a first sensitivity,
the second photoelectric conversion portion has a second saturation capacitance different from the first saturation capacitance and a second sensitivity different from the first sensitivity.
2. The solid-state image pickup device according to claim 1, wherein:
the first saturation capacitance is less than the second saturation capacitance,
the first sensitivity is greater than the second sensitivity.
3. The solid-state image pickup device according to claim 1, wherein:
includes a reading section for reading a pixel signal from the pixel section,
the pixel includes:
a reset element which discharges charges of the floating diffusion layer during reset,
the reading section can perform a reading scan, that is,
reading a signal of a reset state in a reading period after a reset period in which the floating diffusion layer is reset by the reset element,
reading a signal corresponding to the accumulated charges during a reading period after the transfer period in which the accumulated charges of the first or second photoelectric conversion portion of the first saturation capacitance and the first sensitivity or the second photoelectric conversion portion of the second sensitivity are transferred to the floating diffusion layer by the first or second transfer element after the reading period after the reset period, and reading the signal
At least either of a first conversion gain mode read and a second conversion gain mode read are made during one such read,
the first conversion gain mode reading is reading of the pixel signal at a first conversion gain corresponding to a first capacitance set by the capacitance variable section,
the second conversion gain mode reading is reading of the pixel signal at a second conversion gain corresponding to a second capacitance set by the capacitance variable section.
4. The solid-state image pickup device according to claim 3, wherein:
the reading section:
in the first conversion gain mode, the capacitance of the floating diffusion layer is held at the first capacitance corresponding to the first conversion gain by the capacitance variable portion at least after the reset period,
a first one of the first conversion gain mode readings is made during a first reading period subsequent to the reset period,
performing a transfer process in a first transfer period using the first transfer element after the first read period in a state where the capacitance of the floating diffusion layer is held at the first capacitance corresponding to the first conversion gain,
a second one of the first conversion gain mode readings is taken during a second reading subsequent to the first transmission period.
5. The solid-state image pickup device according to claim 3, wherein:
the reading section:
in the second conversion gain mode, the capacitance of the floating diffusion layer is held at the second capacitance including the capacitance of the capacitor corresponding to the second conversion gain by the capacitance varying section at least after the reset period,
performing a first one of the second conversion gain mode reads during a third read period subsequent to the reset period,
performing transfer processing in a second transfer period using the second transfer element after the third read period in a state where the capacitance of the floating diffusion layer is held at the second capacitance corresponding to the second conversion gain,
a second one of the second conversion gain mode reads is performed during a fourth read period subsequent to the second transmission period.
6. The solid-state image pickup device according to claim 1, wherein:
the pixel includes:
one of the first photoelectric conversion portions, during an accumulation period, accumulates electric charges generated by photoelectric conversion;
at least two of the second photoelectric conversion portions, during an accumulation period, accumulating electric charges generated by photoelectric conversion;
one of the first transfer elements is capable of transferring the electric charge accumulated in the first photoelectric conversion portion during a specified transfer period; and
at least two of the second transfer elements that can transfer the electric charges accumulated by the second photoelectric conversion portions during a specified transfer period,
the floating diffusion layer transfers the electric charge accumulated in at least one of the first photoelectric conversion portion and the second photoelectric conversion portion through at least one of the first transfer element and the second transfer element.
7. The solid-state image pickup device according to claim 6, wherein:
the pixel includes the first photoelectric conversion portion and is formed in a rectangular shape, and the second photoelectric conversion portion and the second transfer element are arranged corresponding to four corner portions of the first photoelectric conversion portion, respectively.
8. The solid-state image pickup device according to claim 7, wherein:
includes a reading section for reading a pixel signal from the pixel section,
the pixel includes:
a first corner portion of the upper left corner portion, a second corner portion of the upper right corner portion, a third corner portion of the lower left corner portion, and a fourth corner portion of the lower right corner portion as the four corner portions,
a first one of the second photoelectric conversion portions and a first one of the second transmission elements are disposed in the first corner portion,
a second one of the second photoelectric conversion portions and a second one of the second transmission elements are disposed at the second corner portion,
a third photoelectric conversion part and a third transmission element are disposed in the third corner part,
a fourth photoelectric conversion part and a fourth transmission element are disposed in the fourth corner part,
the reading unit may perform reading that exhibits at least one of a large dynamic range function and a phase difference detection function of detecting a phase difference, by using a combination of accumulated charge reading processes for the first photoelectric conversion unit, the first second photoelectric conversion unit, the second photoelectric conversion unit, the third second photoelectric conversion unit, and the fourth second photoelectric conversion unit.
9. The solid-state image pickup device according to claim 7, wherein:
the pixel section includes:
the plurality of pixels are arranged in rows and columns, and
a pixel sharing structure in which the second photoelectric conversion element and the second transfer element of a plurality of adjacent pixels share one floating diffusion layer.
10. The solid-state image pickup device according to claim 9, wherein:
the pixel includes:
a first corner portion of the upper left corner portion, a second corner portion of the upper right corner portion, a third corner portion of the lower left corner portion, and a fourth corner portion of the lower right corner portion as the four corner portions,
a first one of the second photoelectric conversion portions and a first one of the second transmission elements are disposed in the first corner portion,
a second one of the second photoelectric conversion portions and a second one of the second transmission elements are disposed at the second corner portion,
a third photoelectric conversion part and a third transmission element are disposed in the third corner part,
a fourth photoelectric conversion part and a fourth transmission element are disposed in the fourth corner part,
the first one of the second photoelectric conversion portions and the first one of the second transmission elements:
one floating diffusion layer is shared with at least one of the second and second photoelectric conversion portions and the second transfer elements adjacent to the pixel on the left side in the column direction, the third and third second photoelectric conversion portions and the third and fourth second transfer elements adjacent to the pixel on the upper side in the row direction, and the fourth and fourth second photoelectric conversion portions and the fourth and second transfer elements adjacent to the pixel on the upper left side,
the second one of the second photoelectric conversion portions and the second one of the second transmission elements:
one floating diffusion layer is shared with at least one of the first and second photoelectric conversion portions and the first and second transfer elements adjacent to the pixel on the right side in the column direction, the fourth and second photoelectric conversion portions and the fourth and second transfer elements adjacent to the pixel on the upper side in the row direction, and the third and second photoelectric conversion portions and the third and second transfer elements adjacent to the pixel on the upper right side,
the third one of the second photoelectric conversion portions and the third one of the second transmission elements:
one floating diffusion layer is shared with at least one of the fourth second photoelectric conversion portion and the fourth second transfer element adjacent to the pixel on the left side in the column direction, the first second photoelectric conversion portion and the first second transfer element adjacent to the pixel on the lower side in the row direction, and the second photoelectric conversion portion and the second transfer element adjacent to the pixel on the lower left side,
the fourth second photoelectric conversion portion and the fourth second transmission element:
one floating diffusion layer is shared with at least one of the third second photoelectric conversion portion and the third second transfer element adjacent to the pixel on the right side in the column direction, the second photoelectric conversion portion and the second transfer element adjacent to the pixel on the lower side in the row direction, and the first second photoelectric conversion portion and the first second transfer element adjacent to the pixel on the lower right side.
11. The solid-state image pickup device according to claim 10, wherein:
includes a reading section for reading a pixel signal from the pixel section,
the pixel section:
the first pixel, the second pixel, the third pixel and the fourth pixel are arranged in a row and a column,
the first and second photoelectric conversion portions and the first and second transfer elements of the first pixel, the second and second photoelectric conversion portions and the second and second transfer elements of the second pixel, the third and third second photoelectric conversion portions and the third and third second transfer elements of the third pixel, and the fourth and fourth second photoelectric conversion portions and the fourth and fourth second transfer elements of the fourth pixel share one floating diffusion layer,
the reading section:
reading at least one of a function of widening a dynamic range and a function of detecting a phase difference can be performed by a combination of accumulated charge reading processes for the first photoelectric conversion portion of the first pixel, the first second photoelectric conversion portion of the first pixel, the second photoelectric conversion portion of the second pixel, the third second photoelectric conversion portion of the third pixel, and the fourth second photoelectric conversion portion of the fourth pixel.
12. The solid-state image pickup device according to claim 8, wherein:
the reading section may perform at least either one of a first conversion gain mode reading and a second conversion gain mode reading during one reading,
the first conversion gain mode reading is reading of the pixel signal at a first conversion gain corresponding to a first capacitance set by the capacitance variable section,
the second conversion gain mode reading is reading of the pixel signal at a second conversion gain corresponding to a second capacitance set by the capacitance variable section,
in the case of embodying the first large dynamic range function,
in order to obtain the first read processed signal,
maintaining the capacitance of the floating diffusion layer at the first capacitance corresponding to the first conversion gain by the capacitance variable portion at least after a reset period,
a first one of said first conversion gain mode readings is made during a first reading period subsequent to a reset period,
performing a transfer process in a first transfer period using the first transfer element after the first read period in a state where the capacitance of the floating diffusion layer is held at the first capacitance corresponding to the first conversion gain,
a second one of the first conversion gain mode readings is taken during a second reading subsequent to the first transmission period,
in order to obtain the first second read processed signal,
maintaining the capacitance of the floating diffusion layer at the second capacitance corresponding to the second conversion gain by the capacitance variable portion at least after the reset period,
performing a first one of the second conversion gain mode reads during a third read period subsequent to the reset period,
performing transfer processing in a second transfer period using the first transfer element, the second transfer element, the third transfer element, and the fourth transfer element after the third read period in a state where the capacitance of the floating diffusion layer is held at the second capacitance corresponding to the second conversion gain,
a second one of the second conversion gain mode reads is performed during a fourth read period subsequent to the second transmission period,
applying said first one of said second read processed signals as a first large dynamic range signal.
13. The solid-state image pickup device according to claim 8, wherein:
the reading section may perform at least either one of a first conversion gain mode reading and a second conversion gain mode reading during one reading,
the first conversion gain mode reading is reading of the pixel signal at a first conversion gain corresponding to a first capacitance set by the capacitance variable section,
the second conversion gain mode reading is reading of the pixel signal at a second conversion gain corresponding to a second capacitance set by the capacitance variable section,
in the case where the second large dynamic range function and the first phase difference detection function are embodied,
in order to obtain the second first read processed signal,
maintaining the capacitance of the floating diffusion layer at the first capacitance corresponding to the first conversion gain by the capacitance variable portion at least after a reset period,
a first one of said first conversion gain mode readings is made during a first reading period subsequent to a reset period,
performing a transfer process in a first transfer period using the first transfer element after the first read period in a state where the capacitance of the floating diffusion layer is held at the first capacitance corresponding to the first conversion gain,
a second one of the first conversion gain mode readings is taken during a second reading subsequent to the first transmission period,
in order to obtain the second read processed signal,
maintaining the capacitance of the floating diffusion layer at the second capacitance corresponding to the second conversion gain by the capacitance variable portion at least after the reset period,
performing a first one of the second conversion gain mode reads during a third read period subsequent to the reset period,
performing transfer processing of the first one of the second transfer elements and the second one of the second transfer elements after the third read period in a state where the capacitance of the floating diffusion layer is held at the second capacitance corresponding to the second conversion gain,
a second one of the second conversion gain mode reads is performed during a fourth read period subsequent to the second transmission period,
in order to obtain the third second read processed signal,
maintaining the capacitance of the floating diffusion layer at the second capacitance corresponding to the second conversion gain by the capacitance variable portion at least after the reset period,
a first one of the second conversion gain mode readings is made during a fifth reading period subsequent to the reset period,
performing transfer processing of the third and fourth second transfer elements after the fifth reading period in a state where the capacitance of the floating diffusion layer is held at the second capacitance corresponding to the second conversion gain,
a second one of the second conversion gain mode readings is taken during a sixth reading period following the second transmission period,
applying a differential signal of said second read processed signal and said third read processed signal as a first phase difference detection signal,
applying a summed signal of said second one of said second read processed signals and said third one of said second read processed signals as a second large dynamic range signal.
14. The solid-state image pickup device according to claim 8, wherein:
the reading section may perform at least either one of a first conversion gain mode reading and a second conversion gain mode reading during one reading,
the first conversion gain mode reading is reading of the pixel signal at a first conversion gain corresponding to a first capacitance set by the capacitance variable section,
the second conversion gain mode reading is reading of the pixel signal at a second conversion gain corresponding to a second capacitance set by the capacitance variable section,
in the case of embodying the third large dynamic range function and the second phase difference detection function,
in order to obtain the third first read processed signal,
maintaining the capacitance of the floating diffusion layer at the first capacitance corresponding to the first conversion gain by the capacitance variable portion at least after a reset period,
a first one of said first conversion gain mode readings is made during a first reading period subsequent to a reset period,
performing a transfer process in a first transfer period using the first transfer element after the first read period in a state where the capacitance of the floating diffusion layer is held at the first capacitance corresponding to the first conversion gain,
a second one of the first conversion gain mode readings is taken during a second reading subsequent to the first transmission period,
in order to obtain the fourth second read processed signal,
maintaining the capacitance of the floating diffusion layer at the second capacitance corresponding to the second conversion gain by the capacitance variable portion at least after the reset period,
performing a first one of the second conversion gain mode reads during a third read period subsequent to the reset period,
performing transfer processing of the first one of the second transfer elements and the third one of the second transfer elements after the third read period in a state where the capacitance of the floating diffusion layer is held at the second capacitance corresponding to the second conversion gain,
a second one of the second conversion gain mode reads is performed during a fourth read period subsequent to the second transmission period,
in order to obtain the fifth second read processed signal,
maintaining the capacitance of the floating diffusion layer at the second capacitance corresponding to the second conversion gain by the capacitance variable portion at least after the reset period,
a first one of the second conversion gain mode readings is made during a fifth reading period subsequent to the reset period,
performing transfer processing of the second one of the second transfer elements and the fourth one of the second transfer elements after the fifth read period in a state where the capacitance of the floating diffusion layer is held at the second capacitance corresponding to the second conversion gain,
a second one of the second conversion gain mode readings is taken during a sixth reading period following the second transmission period,
applying a differential signal of the fourth read processed signal and the fifth read processed signal as a second phase difference detection signal,
applying an addition signal of the fourth of the second read processed signals and the fifth of the second read processed signals as a third large dynamic range signal.
15. The solid-state image pickup device according to claim 8, wherein:
the reading section may perform at least either one of a first conversion gain mode reading and a second conversion gain mode reading during one reading,
the first conversion gain mode reading is reading of the pixel signal at a first conversion gain corresponding to a first capacitance set by the capacitance variable section,
the second conversion gain mode reading is reading of the pixel signal at a second conversion gain corresponding to a second capacitance set by the capacitance variable section,
in the case of embodying the fourth large dynamic range function and the third phase difference detection function,
in order to obtain the fourth first read processed signal,
maintaining the capacitance of the floating diffusion layer at the first capacitance corresponding to the first conversion gain by the capacitance variable portion at least after a reset period,
a first one of said first conversion gain mode readings is made during a first reading period subsequent to a reset period,
performing a transfer process in a first transfer period using the first transfer element after the first read period in a state where the capacitance of the floating diffusion layer is held at the first capacitance corresponding to the first conversion gain,
a second one of the first conversion gain mode readings is taken during a second reading subsequent to the first transmission period,
in order to obtain the sixth second read processed signal,
maintaining the capacitance of the floating diffusion layer at the second capacitance corresponding to the second conversion gain by the capacitance variable portion at least after the reset period,
performing a first one of the second conversion gain mode reads during a third read period subsequent to the reset period,
performing transfer processing of the first and fourth second transfer elements after the third read period in a state where the capacitance of the floating diffusion layer is held at the second capacitance corresponding to the second conversion gain,
a second one of the second conversion gain mode reads is performed during a fourth read period subsequent to the second transmission period,
in order to obtain the seventh second read processed signal,
maintaining the capacitance of the floating diffusion layer at the second capacitance corresponding to the second conversion gain by the capacitance variable portion at least after the reset period,
a first one of the second conversion gain mode readings is made during a fifth reading period subsequent to the reset period,
performing transfer processing of the second one of the second transfer elements and the third one of the second transfer elements after the fifth read period in a state where the capacitance of the floating diffusion layer is held at the second capacitance corresponding to the second conversion gain,
a second one of the second conversion gain mode readings is taken during a sixth reading period following the second transmission period,
applying a differential signal between the sixth read processed signal and the seventh read processed signal as a third phase difference detection signal,
applying an addition signal of the sixth of the second read processed signals and the seventh of the second read processed signals as a fourth large dynamic range signal.
16. The solid-state image pickup device according to claim 8, wherein:
the reading section may perform at least either one of a first conversion gain mode reading and a second conversion gain mode reading during one reading,
the first conversion gain mode reading is reading of the pixel signal at a first conversion gain corresponding to a first capacitance set by the capacitance variable section,
the second conversion gain mode reading is reading of the pixel signal at a second conversion gain corresponding to a second capacitance set by the capacitance variable section,
in the case of embodying the fifth maximum dynamic range function,
in order to obtain the fifth first read processed signal,
maintaining the capacitance of the floating diffusion layer at the first capacitance corresponding to the first conversion gain by the capacitance variable portion at least after a reset period,
a first one of said first conversion gain mode readings is made during a first reading period subsequent to a reset period,
performing a transfer process in a first transfer period using the first transfer element after the first read period in a state where the capacitance of the floating diffusion layer is held at the first capacitance corresponding to the first conversion gain,
a second one of the first conversion gain mode readings is taken during a second reading subsequent to the first transmission period,
in order to obtain the eighth second read processed signal,
maintaining the capacitance of the floating diffusion layer at the second capacitance corresponding to the second conversion gain by the capacitance variable portion at least after the reset period,
performing a first one of the second conversion gain mode reads during a third read period subsequent to the reset period,
performing transfer processing of the first one of the second transfer elements, the second one of the second transfer elements, and the third one of the second transfer elements after the third read period in a state where the capacitance of the floating diffusion layer is held at the second capacitance corresponding to the second conversion gain,
a second one of the second conversion gain mode reads is performed during a fourth read period subsequent to the second transmission period,
to obtain the ninth second read processed signal,
maintaining the capacitance of the floating diffusion layer at the second capacitance corresponding to the second conversion gain by the capacitance variable portion at least after the reset period,
a first one of the second conversion gain mode readings is made during a fifth reading period subsequent to the reset period,
performing transfer processing of the fourth of the second transfer elements after the fifth reading period in a state where the capacitance of the floating diffusion layer is held at the second capacitance corresponding to the second conversion gain,
a second one of the second conversion gain mode readings is taken during a sixth reading period following the second transmission period,
applying an addition signal of said eighth said second read processed signal and said third said ninth read processed signal as a fifth large dynamic range signal.
17. The solid-state image pickup device according to claim 1, characterized by comprising:
a substrate including a first substrate surface side and a second substrate surface side which is a side opposite to the first substrate surface side;
a first photoelectric conversion portion including a first conductive semiconductor layer formed so as to embed the substrate, and having a function of photoelectric conversion of received light and a function of charge accumulation;
a second conductivity type separation layer formed on at least one side portion of the first conductivity type semiconductor layer of the first photoelectric conversion portion; and
the second photoelectric conversion portion includes a first conductive semiconductor layer formed so as to be embedded in the substrate in parallel with the first photoelectric conversion portion with the second conductive separation layer interposed therebetween, and has a function of photoelectric conversion of received light and a charge accumulation function,
the opening of the light receiving region of the first photoelectric conversion portion is larger than the opening of the second photoelectric conversion portion,
the first conductivity type semiconductor layer of the first photoelectric conversion portion has an impurity concentration smaller than that of the first conductivity type semiconductor layer of the second photoelectric conversion portion.
18. The solid-state image pickup device according to claim 17, wherein:
the second photoelectric conversion portion includes at least one second conductivity type semiconductor layer having a junction capacitance component with the first conductivity type semiconductor layer in a direction orthogonal to a normal line of the substrate in at least a part of the first conductivity type semiconductor layer.
19. A method of driving a solid-state image pickup device, characterized in that the solid-state image pickup device comprises:
a pixel section in which pixels are arranged,
the pixel includes:
at least one first photoelectric conversion portion that accumulates, during an accumulation period, electric charges generated by photoelectric conversion;
at least one second photoelectric conversion portion that accumulates, during an accumulation period, electric charges generated by photoelectric conversion;
at least one first transfer element that can transfer the electric charge accumulated by the first photoelectric conversion portion during a specified transfer period;
at least one second transfer element that can transfer the electric charge accumulated by the second photoelectric conversion portion during a specified transfer period;
a floating diffusion layer that transfers the electric charge accumulated in at least one of the first photoelectric conversion portion and the second photoelectric conversion portion through at least one of the first transfer element and the second transfer element;
a source follower element that converts the charge of the floating diffusion layer into a voltage signal with a gain corresponding to an amount of charge;
a reset element that discharges charges of the floating diffusion layer during reset; and
a capacitance varying section for varying the capacitance of the floating diffusion layer in response to a capacitance varying signal,
the first photoelectric conversion portion has a first saturation capacitance and a first sensitivity,
the second photoelectric conversion portion has a second saturation capacitance different from the first saturation capacitance and a second sensitivity different from the first sensitivity,
the method of driving the solid-state image pickup device includes the steps of:
reading a signal of a reset state in a reading period after a reset period in which the floating diffusion layer is reset by the reset element,
in a reading scanning period during which a signal corresponding to accumulated charges is read in a reading period after the transfer period in which the accumulated charges of the first or second photoelectric conversion element having the first or second saturation capacitance and the second photoelectric conversion portion having the first or second sensitivity are transferred to the floating diffusion layer by the first or second transfer element after the reading period after the reset period,
at least either of a first conversion gain mode read and a second conversion gain mode read are made during one such read,
the first conversion gain mode reading is reading of the pixel signal corresponding to the accumulated charge of the first photoelectric conversion portion at a first conversion gain corresponding to a first capacitance set by the capacitance variable portion,
the second conversion gain mode reading is reading of the pixel signal corresponding to the accumulated charge of the second photoelectric conversion portion at a second conversion gain corresponding to a second capacitance set by the capacitance variable portion.
20. An electronic device, characterized by comprising:
a solid-state image pickup device; and
an optical system for forming an image of a subject in the solid-state image pickup device,
the solid-state image pickup device includes:
a pixel section in which pixels are arranged,
the pixel includes:
at least one first photoelectric conversion portion that accumulates, during an accumulation period, electric charges generated by photoelectric conversion;
at least one second photoelectric conversion portion that accumulates, during an accumulation period, electric charges generated by photoelectric conversion;
at least one first transfer element that can transfer the electric charge accumulated by the first photoelectric conversion portion during a specified transfer period;
at least one second transfer element that can transfer the electric charge accumulated by the second photoelectric conversion portion during a specified transfer period;
a floating diffusion layer that transfers the electric charge accumulated in at least one of the first photoelectric conversion portion and the second photoelectric conversion portion through at least one of the first transfer element and the second transfer element;
a source follower element that converts the charge of the floating diffusion layer into a voltage signal with a gain corresponding to an amount of charge; and
a capacitance varying section for varying the capacitance of the floating diffusion layer in response to a capacitance varying signal,
the first photoelectric conversion portion has a first saturation capacitance and a first sensitivity,
the second photoelectric conversion portion has a second saturation capacitance different from the first saturation capacitance and a second sensitivity different from the first sensitivity.
Technical Field
The present invention relates to a solid-state imaging device, a method of driving the solid-state imaging device, and an electronic apparatus.
Background
A Complementary Metal Oxide Semiconductor (CMOS) image sensor has been put to practical use as a solid-state image pickup device (image sensor) using a photoelectric conversion element that detects light and generates electric charges.
CMOS image sensors are widely used as a part of various electronic devices such as digital cameras, video cameras, monitoring cameras, medical endoscopes, Personal Computers (PCs), portable terminal devices (mobile devices) such as mobile phones, and the like.
A CMOS image sensor, which has an FD amplifier including a photodiode (photoelectric conversion element) and a Floating Diffusion layer (FD) in each pixel, is of a mainstream read type of a column parallel output type, that is, a certain row in a pixel array is selected while reading the rows in a column (column) direction.
In order to improve the characteristics, various methods have been proposed for realizing a high-quality CMOS image sensor having a large dynamic range (see, for example, patent document 1).
However, the wide dynamic range technique disclosed in
Therefore, a solid-state image pickup device has been proposed which obtains two image data having different sensitivities by arranging two Photodiodes (PDs) having different sensitivities in each pixel (for example, see non-patent document 1).
Fig. 1 is a diagram showing a structure of a pixel of a CMOS image sensor described in
Fig. 2(a) to (E) are diagrams showing the reading timing of the pixels in fig. 1.
The pixel of fig. 1 includes a small photodiode (photoelectric conversion element) SPD having small sensitivity and saturation capacitance and a large photodiode LPD having large sensitivity and saturation capacitance.
A small transfer transistor TGS and a small floating diffusion layer (floating diffusion layer) FDS are provided corresponding to the small photodiode SPD, and a large transfer transistor TGL and a large floating diffusion layer FDL are provided corresponding to the large photodiode LPD.
The small floating diffusion layer FDS and the large floating diffusion layer FDL are connected to each other by a connection switching transistor TDFD.
A reset transistor TRST is connected between the floating diffusion layer FDS for small size and the reset potential vrfd.
The source follower transistor TSF and the selection transistor TSEL are connected in series between the power supply line VDD and the vertical signal line vpix, and the large floating diffusion layer FDL is connected to the gate of the source follower transistor TSF.
In the pixel of fig. 1, a Low Conversion Gain (LCG) is obtained by setting the connection switching transistor TDFD to an on state. In this case, the equivalent capacitance of the gate of the source follower transistor TSF increases. A High Conversion Gain (HCG) is obtained by setting the connection switching transistor TDFD to a non-conductive state.
In the pixel of fig. 1, the large photodiode LPD can be used for reading both Low Conversion Gain (LCG) and High Conversion Gain (HCG), and the small photodiode SPD can only read Low Conversion Gain (LCG).
Disclosure of Invention
Technical problem to be solved by the invention
However, in the large dynamic range technique disclosed in
On the other hand, the small floating diffusion FD for the large photodiode LPD can reduce the read noise, but the SNR interval (gap) for reading by the other photodiodes PD is deteriorated.
The invention provides a solid-state imaging device, a driving method of the solid-state imaging device, and an electronic apparatus, which can realize a large dynamic range, prevent the influence of read noise, and improve image quality.
Means for solving the problems
A solid-state image pickup device of a first aspect of the present invention includes a pixel section in which pixels are arranged, the pixels including: at least one first photoelectric conversion portion that accumulates, during an accumulation period, electric charges generated by photoelectric conversion; at least one second photoelectric conversion portion that accumulates, during an accumulation period, electric charges generated by photoelectric conversion; at least one first transfer element that can transfer the electric charge accumulated by the first photoelectric conversion portion during a specified transfer period; at least one second transfer element that can transfer the electric charge accumulated by the second photoelectric conversion portion during a specified transfer period; a floating diffusion layer that transfers the electric charge accumulated in at least one of the first photoelectric conversion portion and the second photoelectric conversion portion through at least one of the first transfer element and the second transfer element; a source follower element that converts the charge of the floating diffusion layer into a voltage signal with a gain corresponding to an amount of charge; and a capacitance variable portion that can change a capacitance of the floating diffusion layer in accordance with a capacitance change signal, wherein the first photoelectric conversion portion has a first saturation capacitance and a first sensitivity, and the second photoelectric conversion portion has a second saturation capacitance different from the first saturation capacitance and a second sensitivity different from the first sensitivity.
A second aspect of the present invention is a driving method of a solid-state image pickup device including a pixel section in which pixels are arranged, the pixels including: at least one first photoelectric conversion portion that accumulates, during an accumulation period, electric charges generated by photoelectric conversion; at least one second photoelectric conversion portion that accumulates, during an accumulation period, electric charges generated by photoelectric conversion; at least one first transfer element that can transfer the electric charge accumulated by the first photoelectric conversion portion during a specified transfer period; at least one second transfer element that can transfer the electric charge accumulated by the second photoelectric conversion portion during a specified transfer period; a floating diffusion layer that transfers the electric charge accumulated in at least one of the first photoelectric conversion portion and the second photoelectric conversion portion through at least one of the first transfer element and the second transfer element; a source follower element that converts the charge of the floating diffusion layer into a voltage signal with a gain corresponding to an amount of charge; a reset element that discharges charges of the floating diffusion layer during reset; and a capacitance varying unit that varies a capacitance of the floating diffusion layer in accordance with a capacitance varying signal, the first photoelectric conversion unit having a first saturation capacitance and a first sensitivity, the second photoelectric conversion unit having a second saturation capacitance different from the first saturation capacitance and a second sensitivity different from the first sensitivity, the first photoelectric conversion unit reading a signal in a reset state during a reading period after a reset period in which the floating diffusion layer is reset by the reset element, and the second photoelectric conversion unit reading a signal corresponding to accumulated charges during a reading period after the transfer period in which the accumulated charges of the first photoelectric conversion element or the second photoelectric conversion element having the first saturation capacitance and the first sensitivity or the second photoelectric conversion element having the second saturation capacitance and the second sensitivity are transferred to the floating diffusion layer by the first transfer element or the second transfer element after the reading period after the reset period, in the scanning period, at least one of a first conversion gain mode reading in which the pixel signal corresponding to the accumulated electric charge of the first photoelectric conversion portion is read at a first conversion gain corresponding to a first capacitance set by the capacitance variable portion and a second conversion gain mode reading in which the pixel signal corresponding to the accumulated electric charge of the second photoelectric conversion portion is read at a second conversion gain corresponding to a second capacitance set by the capacitance variable portion is performed in one of the reading periods.
An electronic device according to a third aspect of the present invention includes: a solid-state image pickup device; and an optical system that forms an image of a subject in the solid-state imaging device, the solid-state imaging device including a pixel section in which pixels are arranged, the pixels including: at least one first photoelectric conversion portion that accumulates, during an accumulation period, electric charges generated by photoelectric conversion; at least one second photoelectric conversion portion that accumulates, during an accumulation period, electric charges generated by photoelectric conversion; at least one first transfer element that can transfer the electric charge accumulated by the first photoelectric conversion portion during a specified transfer period; at least one second transfer element that can transfer the electric charge accumulated by the second photoelectric conversion portion during a specified transfer period; a floating diffusion layer that transfers the electric charge accumulated in at least one of the first photoelectric conversion portion and the second photoelectric conversion portion through at least one of the first transfer element and the second transfer element; a source follower element that converts the charge of the floating diffusion layer into a voltage signal with a gain corresponding to an amount of charge; and a capacitance variable portion that can change a capacitance of the floating diffusion layer in accordance with a capacitance change signal, wherein the first photoelectric conversion portion has a first saturation capacitance and a first sensitivity, and the second photoelectric conversion portion has a second saturation capacitance different from the first saturation capacitance and a second sensitivity different from the first sensitivity.
Effects of the invention
According to the present invention, it is possible to realize a large dynamic range, prevent the influence of read noise, and improve image quality.
Drawings
Fig. 1 is a diagram showing a structure of a pixel of a CMOS image sensor described in
Fig. 2(a) to (E) are diagrams showing the reading timing of the pixels in fig. 1.
Fig. 3 is a block diagram showing a configuration example of the solid-state imaging device according to the first embodiment of the present invention.
Fig. 4 is a circuit diagram showing an example of the pixel according to the first embodiment.
Fig. 5 is a schematic cross-sectional view showing an example of the configuration of a main portion of each of the embedded first photodiode and the embedded second photodiode according to the first embodiment of the present invention, except for the charge transfer gate portion.
Fig. 6(a) and (B) are diagrams showing operation timings of the shutter scanning and the reading scanning in the normal pixel reading operation in the present embodiment.
Fig. 7(a) to (C) are diagrams for explaining configuration examples of a reading system for column output of a pixel section of a solid-state imaging device according to an embodiment of the present invention.
Fig. 8(a) to (E) are diagrams for explaining an operation of achieving a large dynamic range corresponding to a conversion gain when a capacitor and a switch are applied to the capacitance variable portion according to the first embodiment.
Fig. 9 is a diagram showing input/output characteristics of a high gain signal and a low gain signal in the solid-state image pickup device according to the first embodiment, and is for explaining a relationship between capacitance of a floating diffusion layer and read noise.
Fig. 10 is a diagram showing response characteristics of a high-gain signal and a low-gain signal in the solid-state imaging device according to the first embodiment.
Fig. 11 is a diagram showing SNR characteristics of a high gain signal and a low gain signal in the solid-state imaging device according to the first embodiment.
Fig. 12 is a graph showing response characteristics of a high gain signal and a low gain signal in a solid-state image pickup device as a comparative example.
Fig. 13 is a diagram showing SNR characteristics of a high gain signal and a low gain signal in a solid-state image pickup device as a comparative example.
Fig. 14 is a diagram showing a configuration example of a pixel portion and a capacitance variable portion according to a second embodiment of the present invention.
Fig. 15 is a diagram showing a configuration example of a pixel portion and a capacitance variable portion according to a third embodiment of the present invention.
Fig. 16 is a diagram showing a configuration example of a pixel portion and a capacitance variable portion according to a fourth embodiment of the present invention.
Fig. 17 is a diagram showing a configuration example of a pixel portion and a capacitance variable portion according to a fifth embodiment of the present invention.
Fig. 18(a) to (E) are diagrams for explaining the first reading operation corresponding to the conversion gain in the case where the capacitor and the switch are applied to the variable capacitance section according to the fifth embodiment.
Fig. 19(a) to (F) are diagrams for explaining the second reading operation corresponding to the conversion gain in the case where the capacitor and the switch are applied to the variable capacitance section according to the fifth embodiment.
Fig. 20 is a schematic cross-sectional view showing a configuration example of a main portion of an embedded first photodiode and two second photodiodes of a fifth embodiment of the present invention except for a charge transfer gate portion.
Fig. 21 is a diagram showing a configuration example of a pixel portion and a capacitance variable portion according to a sixth embodiment of the present invention.
Fig. 22 is a diagram illustrating an example of the arrangement of the first photodiode and the four second photodiodes in the pixel according to the sixth embodiment.
Fig. 23 is a diagram showing a configuration example of a layout of a pixel portion and a capacitance variable portion according to a seventh embodiment of the present invention.
Fig. 24 is a diagram showing a basic layout pattern of each pixel of the pixel portion of fig. 23 viewed from the back side.
Fig. 25 is a table showing an outline of the read mode embodying the large dynamic range function and the phase difference detection function according to the seventh embodiment.
Fig. 26(a) to (E) are timing charts showing the reading operation in the high dynamic range mode (HDR) according to the seventh embodiment.
Fig. 27(a) to (F) are timing charts showing the reading operation in the first phase difference detection mode (pdaf (v)) according to the seventh embodiment.
Fig. 28(a) to (F) are timing charts showing the reading operation in the second phase difference detection mode (pdaf (h)) according to the seventh embodiment.
Fig. 29(a) to (F) are timing charts showing the reading operation in the third phase difference detection mode (pdaf (d)) according to the seventh embodiment.
Fig. 30(a) to (F) are diagrams showing timing charts of the reading operation in the special high dynamic range mode (Extra-HDR) according to the seventh embodiment.
Fig. 31 is a graph showing sensitivity characteristics of the first photodiode and the second photodiode in each reading mode according to the seventh embodiment of the present invention.
Fig. 32(a) and (B) are graphs showing the sensitivity characteristics after linearization of the high dynamic range mode (HDR), the third phase difference detection mode (pdaf (d)), and the special high dynamic range mode (Extra-HDR) according to the seventh embodiment of the present invention.
Fig. 33(a) to (C) are views for explaining that the reading operation in each reading mode of the seventh embodiment can be similarly applied to the pixel of fig. 22 of the sixth embodiment.
Fig. 34 is a diagram illustrating an example of the arrangement of the first photodiode and the eight second photodiodes in the pixel according to the eighth embodiment.
Fig. 35 is a schematic cross-sectional view showing another example of the structure of the embedded first photodiode and the embedded second photodiode of the present embodiment shown in fig. 5.
Fig. 36(a) and (B) are diagrams for explaining that the solid-state imaging device according to the embodiment of the present invention can be applied to both a front-surface illumination type image sensor and a back-surface illumination type image sensor.
Fig. 37 is a diagram showing an example of a configuration of an electronic apparatus to which a solid-state imaging device according to an embodiment of the present invention is applied.
Detailed Description
Hereinafter, embodiments of the present invention will be described in connection with the drawings.
(first embodiment)
Fig. 3 is a block diagram showing a configuration example of the solid-state imaging device according to the first embodiment of the present invention.
In the present embodiment, the solid-state
As shown in fig. 3, the solid-state
Among these components, the
In the first embodiment, as described in detail below, the solid-
In the first embodiment, as described in detail below, the solid-
The solid-
In the first embodiment, the
The
In the present embodiment, the
Further, the solid-
In a normal pixel reading operation, the shutter scanning is performed by driving the
Hereinafter, the configuration and the function of each part of the solid-
(Structure of
A plurality of pixels including photodiodes (photoelectric conversion elements) and in-pixel amplifiers in the
Fig. 4 is a circuit diagram showing an example of a pixel according to the present embodiment.
The pixel PXL includes, for example, a plurality of (two in the first embodiment) photodiodes serving as photoelectric conversion units (photoelectric conversion elements) having different saturation capacitance ratios and sensitivity ratios, and a plurality of (two in the first embodiment) transfer transistors TGSL-Tr and TGLS-Tr serving as transfer elements for transferring accumulated charges of the respective photodiodes to the floating diffusion layer FD.
In the first embodiment, each pixel PXL includes the first photodiode PDSL as the first photoelectric conversion section having the first saturation capacitance and the first sensitivity, and the second photodiode PDLS as the second photoelectric conversion section having the second saturation capacitance different from the first saturation capacitance and the second sensitivity different from the first sensitivity.
In the first embodiment, the first saturation capacitance is smaller than the second saturation capacitance, and the first sensitivity is larger than the second sensitivity. For example, the first saturation capacitance is about 5ke, and the second saturation capacitance is about 20 ke. For example, the first sensitivity is about 5ke/lux, and the second sensitivity is about 25 ke/lux.
The first photodiode PDSL is connected to a transfer transistor TGSL-Tr as a first transfer element, and the second photodiode PDLS is connected to a transfer transistor TGLS-Tr as a second transfer element.
Further, the pixel PXL includes a reset transistor RST-Tr as a reset element, a source follower transistor SF-Tr as a source follower element, and a select transistor SEL-Tr as a select element.
In addition, the pixel PXL includes a
In the present first embodiment, the
The photodiodes PDSL, PDLS generate and accumulate signal charges (here, electrons) in an amount corresponding to the amount of incident light.
Hereinafter, a case where the signal charges are electrons and the transistors are n-type transistors will be described, but the signal charges may be holes (holes) and the transistors may be p-type transistors.
This embodiment is also effective in the case where each transistor is shared among a plurality of photodiodes or in the case where a pixel including no selection transistor is used.
In each pixel PXL, a buried photodiode (PPD) is used as the Photodiode (PD). Since the surface level of the substrate on which the Photodiode (PD) is formed is due to defects such as dangling bonds, a large amount of charges (dark current) are generated by thermal energy, and an accurate signal cannot be read.
The embedded photodiode (PPD) can reduce the mixing of a dark current into a signal by embedding a charge accumulation portion of a Photodiode (PD) into a substrate.
The first photodiode PDSL and the second photodiode PDLS formed as the embedded photodiode are configured as follows.
The first photodiode PDSL is formed so as to include a first conductivity type (n-type in this embodiment) semiconductor layer (n-layer in this embodiment) formed by embedding a semiconductor substrate on a side of a second substrate surface including the first substrate surface side and a side facing the first substrate surface side, and has a function of photoelectric conversion of received light and a function of charge accumulation.
A second-conductivity-type (p-type in this embodiment) separation layer is formed on a side portion of the first photodiode PDSL in a direction perpendicular to the normal line of the substrate.
The second photodiode PDLS includes an n layer (first conductive semiconductor layer) formed by embedding the substrate in parallel with the first photodiode PDSL with a second conductive separation layer interposed therebetween, and has a function of photoelectric conversion of received light and a function of charge accumulation.
In the present embodiment, the opening of the light receiving region of the first photodiode PDSL is formed to be larger than the opening of the light receiving region of the second photodiode PDSL, and the impurity concentration of the n layer of the first photodiode PDSL is formed to be smaller than the impurity concentration of the n layer of the second photodiode PDLS.
According to the above structure, the first photodiode PDSL realizes a characteristic structure of the pixel PXL in which the saturation capacitance is smaller than that of the second photodiode PDLS and the sensitivity is larger than that of the second photodiode PDLS.
In the present embodiment, the second photodiode PDLS is formed so that the photoelectric conversion portion thereof includes at least one p layer (second conductivity type semiconductor layer) having a junction capacitance component with the n layer (first conductivity type semiconductor layer) in a direction (X or Y direction) orthogonal to the normal line of the substrate in order to increase the accumulation capacitance (saturation capacitance).
(specific configuration examples of Embedded photodiode PDSL, PDLS)
Here, a specific configuration example of the embedded type first photodiode PDSL and the second photodiode PDLS will be described in association with fig. 5.
Fig. 5 is a schematic cross-sectional view showing an example of the configuration of a main portion of each of the embedded first photodiode and the embedded second photodiode according to the first embodiment of the present invention, except for the charge transfer gate portion.
Here, a portion of the embedded photodiode (PPD) is denoted by
The embedded photodiode (PPD)
The embedded
The embedded
In the embedded
In the example of fig. 5, the first photodiode 220(PDSL) is formed between the second conductivity type (p-type)
The second photodiode 240(PDLS) is formed between the p-
In the present embodiment, the opening AP1 of the light receiving region of the first photodiode PDSL is formed to be larger than the opening AP2 of the light receiving region of the second photodiode PDLS (AP1> AP2), and the impurity concentration DN1 of the
The first photodiode 220(PDSL) of fig. 5 is configured such that the n layer (first conductivity type semiconductor layer) 221n has a three-layer structure in the normal direction of the substrate 210 (Z direction of the orthogonal coordinate system in the figure).
In this example, n- - -
The second photodiode 240(PDLS) of fig. 5 is configured such that the n layer (first conductive type semiconductor layer) 241n has a two-layer structure in the normal direction of the substrate 210 (Z direction of the orthogonal coordinate system in the figure).
In this example, an n-
These structures are examples, and may have a single-layer structure, or may have a laminated structure of three or more layers.
The p-
In this example, a p-
The p-
In this example,
Further, a p + layer (second conductivity type semiconductor layer) 2323 having a capacitance component joined to the n layer (first conductivity type semiconductor layer) 2412 is formed on the side of the p-
The p-
In this example, a p-
Further, a p + layer (second conductive type semiconductor layer) 2333 having a capacitance component joined to the n layer (first conductive type semiconductor layer) 2412 is formed on the side of the p-
These structures are examples, and may have a single-layer structure, or may have a laminated structure of three or more layers.
The reason for forming the p + layers (second conductive type semiconductor layers) 2323 and 2333 having a capacitance component joined to the n layer (first conductive type semiconductor layer) 2412 will now be described.
In the case of a pixel having a large size and a large aspect ratio, for example, about 3 μm □, the accumulated charge is mainly limited to the pn junction capacitance (junction capacitance) in the vertical direction (the normal direction of the substrate: the depth direction of the substrate) of a portion near the surface of the Photodiode (PD) portion (photoelectric conversion portion), and it is difficult to increase the accumulated capacitance efficiently.
Therefore, in the solid-
According to this configuration, since the area of the n layer along the p + layer can be increased, a large accumulation capacitance can be secured despite the small PD area.
In the embedded
The structure of the embedded photodiode (PPD)200 of the first embodiment is described in detail above.
Here, the description returns to the pixel of fig. 4.
The first transfer transistor TGSL-Tr is connected between the first photodiode PDSL and the floating diffusion layer FD, and is controlled by a control signal TGSL applied to the gate through a control line LTGSL.
The first transfer transistor TGSL-Tr is selected to be in an on state during a transfer period in which the control signal TGSL is at a high (H) level, and transfers charges (electrons) photoelectrically converted and accumulated by the first photodiode PDSL to the floating diffusion layer FD.
The second transfer transistor TGLS-Tr is connected between the second photodiode PDLS and the floating diffusion layer FD, and is controlled by a control signal TGLS applied to the gate through a control line LTGLS.
The second transfer transistor TGLS-Tr is selected to be in a conductive state during a transfer period in which the control signal TGLS is at a high (H) level, and transfers charges (electrons) photoelectrically converted and accumulated by the second photodiode PDLS to the floating diffusion layer FD.
The reset transistor RST-Tr is connected between, for example, the power supply line VDD and the floating diffusion layer FD, and is controlled by a control signal RST applied to the gate through a control line LRST.
The reset transistor RST-Tr is selected to be in an on state while the control signal RST is at the H level, and resets the floating diffusion FD to the potential of the power supply line VDD.
The source follower transistors SF to Tr are connected in series with the selection transistors SEL to Tr between the power supply line VDD and the vertical signal line LSGN.
The gate of the source follower transistor SF-Tr is connected to the floating diffusion layer FD, and the selection transistor SEL-Tr is controlled by a control signal SEL applied to the gate through a control line LSEL.
The selection transistor SEL-Tr is selected to be in an on state while the control signal SEL is at the H level. Thereby, the source follower transistor SF-Tr outputs to the vertical signal line LSGN a column-output read signal VSL, which is a signal obtained by converting the charge of the floating diffusion layer FD into a voltage signal with a gain corresponding to the charge amount (potential).
For example, the gates of the transfer transistor TGSL-Tr or TGLS-Tr, the reset transistor RST-Tr, and the select transistor SEL-Tr are connected in units of rows, and therefore, the pixels in one row simultaneously perform the above-described operation in parallel.
Since N rows × M columns of pixels PXL are arranged in the
In fig. 1, the control lines LSEL, LRST, LTGSL, TGLS, LBIN are represented as one row scanning control line.
The
The
As described above, in the normal pixel reading operation, the shutter scanning is performed by the driving of the
Fig. 6(a) and (B) are diagrams showing operation timings of the shutter scanning and the reading scanning in the normal pixel reading operation in the present embodiment.
The control signal SEL for controlling the on (conduction) and off (non-conduction) of the selection transistor SEL-Tr is set to the L level during the shutter scanning period PSHT to keep the selection transistor SEL-Tr in the non-conduction state, and is set to the H level during the reading scanning period PRDO to keep the selection transistor SEL-Tr in the conduction state.
During the period in which the control signal RST is at the H level in the shutter scanning period PSHT, the control signal TGSL or TGLS is set at the H level for a predetermined period, and the photodiode PD and the floating diffusion layer FD are reset by the reset transistor RST-Tr and the transfer transistor TGSL-Tr or TGLS-Tr.
In the read scanning period PRDO, the control signal RST is set to the H level, the floating diffusion FD is reset by the reset transistor RST-Tr, and a signal in a reset state is read in the read period PRD1 after the reset period PR.
After the read period PRD1, the control signal TGSL or TGLS is set to the H level for a predetermined period, the accumulated charges of the photodiode PDSL or PDLS are transferred to the floating diffusion layer FD by the transfer transistor TGSL-Tr or TGLS-Tr, and a signal corresponding to the accumulated electrons (charges) is read in the read period PRD2 after the transfer period PT.
In the normal pixel reading operation according to the first embodiment, the accumulation period (exposure period) EXP is, for example, a period from when the photodiodes PDSL and PDLS and the floating diffusion layer FD are reset in the shutter scanning period PSHT and the control signal TGSL or TGLS is switched to the L level until the control signal TGSL or TGLS is switched to the L level to end the transfer period PT of the reading scanning period PRDO, as shown in fig. 6B.
The
The structure of the
As described above, for example, as shown in fig. 7(a), the configuration of the read
Alternatively, for example, as shown in fig. 7B, the
For example, as shown in fig. 7C, the
The
A CMOS image sensor that employs a global shutter as an electronic shutter is provided with, for example, a signal holding section that holds a signal read from a photoelectric conversion reading section in a signal holding capacitor within a pixel.
In a CMOS image sensor using a global shutter, for example, electric charges are simultaneously accumulated as voltage signals from photodiodes to signal holding capacitors of a signal holding section, and then sequentially read, thereby ensuring simultaneity of the entire image.
The CMOS image sensor is configured as a stacked CMOS image sensor, for example.
The stacked CMOS image sensor has a stacked structure in which a first substrate (Pixel die) and a second substrate (ASIC die) are connected by micro bumps (connection portions), for example. A photoelectric conversion reading portion for each pixel is formed over the first substrate, and a signal holding portion, a signal line, a vertical scanning circuit, a horizontal scanning circuit, a reading circuit, and the like for each pixel are formed over the second substrate.
Each pixel formed on the first substrate is connected to a signal holding portion formed on the second substrate, and the signal holding portion is connected to a
The
The
In the first embodiment, the
The
The outline of the structure and function of each part of the solid-
Next, the configuration of the
The
The capacitor C81 is connected between the reference potential VSS and the connection node ND81 of the reset transistor RST-Tr and the switching transistor SW 81-Tr.
The switch transistor SW81-Tr is connected between the connection node ND81 and the floating diffusion layer FD.
Next, a reading operation corresponding to a conversion gain in a case where a capacitor and a switch are applied to the capacitance variable portion according to the first embodiment will be described in association with fig. 8.
Fig. 8(a) to (E) are diagrams for explaining the reading operation corresponding to the conversion gain in the case where the capacitor and the switch are applied to the capacitance variable portion according to the first embodiment.
Fig. 8(a) shows the control signal SEL of the selection transistor SEL-Tr, fig. 8(B) shows the control signal TGSL of the first transfer transistor TGSL-Tr, fig. 8(C) shows the control signal TGLS of the second transfer transistor TGLS-Tr, fig. 8(D) shows the control signal RST of the reset transistor RST-Tr, and fig. 8(E) shows the control signal BIN of the switching transistor SW 81-Tr.
(read operation in the first conversion gain mode)
In the first conversion gain mode, the following reading operation is performed.
In the read scanning period PRDO, as shown in fig. 8(a), in order to select a certain row in the pixel array, the control signal SEL to the control line connected to each pixel PXL of the selected row is set to the H level, and the selection transistor SEL-Tr of the pixel PXL is turned on.
In this selected state, in the reset period PR, the reset transistor RST-Tr is selected to be in an on state while the control signal RST is at the H level, the switch transistor SW81-Tr of the
After the floating diffusion FD is reset, as shown in fig. 8(E) and (D), the capacitance change signal BIN is switched to the L level, and the switching transistors SW81-Tr of the
After the reset period PR elapses, the reset transistor RST-Tr is in a non-conductive state, and a period until the transfer period PT starts is a first read period PRD11 in which a pixel signal in the reset state is read.
In this case, since the switching transistor SW81-Tr of the
At time t1 after the start of the first read period PRD11, the
At this time, in each pixel PXL, the charge of the floating diffusion layer FD is converted into a voltage signal by a gain corresponding to the charge amount (potential) by the source follower transistor SF-Tr, a read signal VSL (HCG11) output as a column is output to the vertical signal line LSGN, and supplied to, for example, be held in the
Here, the first read period PRD11 ends, and the transfer period PT11 is reached. At this time, the capacitance change signal BIN is maintained at the L level even after the transmission period PT11 elapses.
As shown in fig. 8B, in the transfer period PT11, the transfer transistor TGSL-Tr is selected to be in the on state during the period when the control signal TGSL is at the H level, and the charges (electrons) photoelectrically converted and accumulated by the first photodiode PDSL are transferred to the floating diffusion FD during the period including the
After the transfer period PT11 elapses (the transfer transistor TGSL-Tr is in a non-conductive state), a second read period PRD12 is reached in which the pixel signal corresponding to the electric charge photoelectrically converted and accumulated by the first photodiode PDSL is read.
At time t3 after the start of the second read period PRD12, in a state where the capacitance change signal BIN is set to the L level, the
At this time, in each pixel PXL, the charge of the floating diffusion layer FD is converted into a voltage signal by a gain corresponding to the charge amount (potential) by the source follower transistor SF-Tr, a read signal VSL (HCG12) output as a column is output to the vertical signal line LSGN, and supplied to, for example, be held in the
Next, in the
(read operation in second conversion gain mode)
In the second conversion gain mode, the following reading operation is performed.
In the read scanning period PRDO, as shown in fig. 8(a), in order to select a certain row in the pixel array, the control signal SEL to the control line connected to each pixel PXL of the selected row is set to the H level, and the selection transistor SEL-Tr of the pixel PXL is turned on.
In this selected state, the switching transistors SW81-Tr of the
In this case, since the switching transistor SW81-Tr of the
Next, in the reset period PR, the reset transistor RST-Tr is selected to be in an on state while the control signal RST is at the H level, the switch transistor SW81-Tr of the
After the floating diffusion FD is reset, as shown in fig. 8(D) and (E), the capacitance change signal BIN is held at the H level, and the switching transistors SW81-Tr of the
After the reset period PR elapses, the reset transistor RST-Tr is in a non-conductive state, and a period until the transfer period PT starts is a first read period PRD21 in which a pixel signal in the reset state is read.
In this case, since the switching transistor SW81-Tr of the
At time t11 after the start of the first read period PRD21, the
At this time, in each pixel PXL, the charge of the floating diffusion layer FD is converted into a voltage signal by a gain corresponding to the charge amount (potential) by the source follower transistor SF-Tr, a read signal VSL (LCG11) output as a column is output to the vertical signal line LSGN, and supplied to, for example, be held in the
Here, the first read period PRD21 ends, and the transfer period PT21 is reached. At this time, the capacitance change signal BIN is maintained at the H level even after the transmission period PT21 elapses.
As shown in fig. 8C, in the transfer period PT21, the transfer transistor TGLS-Tr is selected to be in the on state during the period when the control signal TGLS is at the H level, and the charges (electrons) photoelectrically converted and accumulated by the second photodiode PDLS are transferred to the floating diffusion FD during the period including the time 12.
After the transfer period PT21 elapses (the transfer transistor TGLS-Tr is in a non-conductive state), a second read period PRD22 is reached in which the pixel signal corresponding to the charge photoelectrically converted and accumulated by the second photodiode PDLS is read.
At time t13 after the start of the second read period PRD22, the
At this time, in each pixel PXL, the charge of the floating diffusion layer FD is converted into a voltage signal by a gain corresponding to the charge amount (potential) by the source follower transistor SF-Tr, a read signal VSL (LCG12) output as a column is output to the vertical signal line LSGN, and supplied to, for example, be held in the
Next, for example, in the
As described above, according to the first embodiment, the pixel PXL includes, for example, the first photodiode PDSL and the second photodiode PSLS as the photoelectric conversion sections (photoelectric conversion elements) having a plurality of (two in the first embodiment) different in saturation capacitance ratio and sensitivity ratio, and the transfer transistors TGSL-Tr and TGLS-Tr as the transfer elements for transferring the accumulated charges of the respective photodiodes to the floating diffusion layer FD.
In each pixel PXL, the first photodiode PDSL has a first saturation capacitance and a first sensitivity, and the second photodiode PDLS has a second saturation capacitance different from the first saturation capacitance of the first photodiode PDSL and a second sensitivity different from the first sensitivity.
A first saturation capacitance of the first photodiode PDSL is less than a second saturation capacitance of the second photodiode PDLS, and a first sensitivity of the first photodiode PDSL is greater than a second sensitivity of the second photodiode PDLS.
In the first embodiment, the configuration of the pixel (or the pixel section 20) of the solid-
Thus, according to the present first embodiment, in the case of reading a dark signal (signal at the time of low illuminance) using the first photodiode PDSL having a large sensitivity, the capacitance of the floating diffusion layer FD is changed to a smaller capacitance to read the first photodiode PDSL, and on the other hand, to a larger capacitance to read the second photodiode PDLS.
The result is that the SNR of the first photodiode PDSL can be maintained and read noise can be further reduced.
That is, according to the first embodiment, it is possible to prevent the influence of the read noise while increasing the dynamic range, and further improve the image quality.
Here, the input/output characteristics and SNR characteristics of the high gain signal and the low gain signal of the solid-
The pixel of the comparative example includes a small photodiode pdss (spd) having small sensitivity and saturation capacitance and a large photodiode pdll (lpd) having large sensitivity and saturation capacitance, as in the pixel of fig. 1.
Fig. 9 is a diagram showing input/output characteristics of a high gain signal and a low gain signal in the solid-state
Fig. 10 is a diagram showing response characteristics of a high gain signal and a low gain signal in the solid-state
Fig. 11 is a diagram showing SNR characteristics of a high gain signal and a low gain signal in the solid-state
Fig. 12 is a graph showing response characteristics of a high gain signal and a low gain signal in a solid-state image pickup device as a comparative example. In fig. 12, the horizontal axis represents the exposure amount (time), and the vertical axis represents the charge (electron) amount.
Fig. 13 is a diagram showing SNR characteristics of a high gain signal and a low gain signal in a solid-state image pickup device as a comparative example. In fig. 13, the horizontal axis represents exposure amount (time) and the vertical axis represents SNR.
In the comparative example, as shown in fig. 12 and 13, when reading a dark signal (signal at the time of low illuminance) using pdll (lpd) having high sensitivity, the capacitance of the floating diffusion FD needs to be further increased to read all the signals, but the read noise is deteriorated due to the large capacitance of the floating diffusion FD.
On the other hand, the small floating diffusion FD for the large photodiode pdll (lpd) has a capacitance that can reduce the read noise, but the SNR interval for reading by the other photodiodes pdss (spd) is deteriorated.
In contrast, according to the solid-state
In the solid-
This has the advantage that the accumulation capacitance can be increased efficiently.
(second embodiment)
Fig. 14 is a diagram showing a configuration example of a pixel portion and a capacitance variable portion according to a second embodiment of the present invention.
The differences between the PXLA and the
As shown in fig. 14, the configuration of the
The reading operation corresponding to the conversion gain in the case where the capacitor and the switch are applied to the capacitance variable portion according to the second embodiment is performed in the same manner as the reading operation corresponding to the conversion gain in the first embodiment described with reference to fig. 8.
Therefore, detailed description thereof is omitted.
According to the second embodiment, the same effects as those of the first embodiment can be obtained.
(third embodiment)
Fig. 15 is a diagram showing a configuration example of a pixel portion and a capacitance variable portion according to a third embodiment of the present invention.
The differences between the drawing PXLB and the
In the third embodiment, the
In this third embodiment, the first merged switch 81(·, n-1, n +1, ·) is formed of an insulated gate field effect transistor, such as an n-channel mos (nmos) transistor.
In the following description, the merged switch is also referred to as a merged transistor.
In the third embodiment, the first merge switches 81n-1, 81n +1 are turned on and off in accordance with the capacitance change signals BIN1n-1, BIN1n, and BIN1n +1, whereby the number of connected floating diffusions FD is changed to one or more, the capacitance of the floating diffusion FD of the pixel to be read is changed, and the conversion gain of the floating diffusion FD of the pixel PXLBn or PXLBn +1 to be read is changed.
In the third embodiment, the reset element is shared by all the pixels PXLBn-1, PXLBn, and PXLBn + 1. of one column, for example, the floating diffusion layer FD of the pixel PXLB0 (not shown in fig. 15) on one end side of one column and the power supply line VDD (not shown in fig. 15) formed adjacent to the pixel PXLBn-1 on the other end side of one column are connected to each other via the first merge transistors (switches) · 81n-1, 81n, and 81n + 1. formed on the wiring WR so as to correspond to the respective pixels and to be connected in series, and the nodes · NDn-1, NDn, and NDn + 1. on the wiring WR between the first merge switches are connected to the floating diffusion layers FD of the corresponding pixels PXLBn-1, PXLBn, and lbn + 1. cndot.
In the first embodiment, the first merge transistor (switch) 81N-1, not shown, located on the other end side functions as a shared reset element.
With this configuration, the solid-
In addition, the solid-
In addition, in the solid-
(fourth embodiment)
Fig. 16 is a diagram showing a configuration example of a pixel portion and a capacitance variable portion according to a fourth embodiment of the present invention.
The differences between the picture PXLC and the
In the fourth embodiment, in addition to the first merge transistors (merge switches) 81n-1, 81n +1 connected in series to the wiring WR and formed so as to correspond to the respective pixels, second merge transistors (merge switches) 82n-1, 82n +1 formed of, for example, NMOS transistors are connected between the floating diffusion layer FD of the respective pixels PXLCn-1, PXLCn +1 and the nodes NDn-1, NDn +1 of the wiring WR.
The
In the fourth embodiment, the first capacitance change signals BIN1n-1, BIN1n, and BIN1n +1 are paired with the second capacitance change signals BIN2n-1, BIN2n, and BIN2n +1, and switched to the H level and the L level at the same timing (phase).
In this structure, the
The
In the
The
Further, by setting the voltages of the
In addition, the
According to the fourth embodiment, it is needless to say that the same effects as those of the third embodiment can be obtained, and the capacitance of the floating diffusion layer FD can be further optimized, and a conversion gain of an arbitrary further optimized value can be obtained depending on the mode. This makes it possible to further optimize SN at the change point of the conversion gain, obtain desired output characteristics, and obtain an image with high image quality.
(fifth embodiment)
Fig. 17 is a diagram showing a configuration example of a pixel portion and a capacitance variable portion according to a fifth embodiment of the present invention.
The difference between the pixel PXLA of the second embodiment and the picture PXLD of the fifth embodiment is as follows.
In the fifth embodiment, the pixel PXLD is provided with a plurality of (two in the fifth embodiment) second photodiodes PDLS and second transfer transistors TGLS-Tr.
Specifically, the pixel PXLD is provided with a first second photodiode PDLS1, a second photodiode PDLS2, a first second transfer transistor TGLS1-Tr and a second transfer transistor TGLS 2-Tr.
In the pixel PXLD, the first second transfer transistor TGLS1-Tr is connected between the first second photodiode PDLS1 and the output side node ND21, and the second transfer transistor TGLS2-Tr is connected between the second photodiode PDLS2 and the output side node ND 22.
The output side node ND21 of the first second transfer transistor TGLS1-Tr is connected to the output side node ND22 of the second transfer transistor TGLS 2-Tr. The connection point is connected to the capacitor C82 of the
Fig. 18(a) to (E) are diagrams for explaining the first reading operation corresponding to the conversion gain in the case where the capacitor and the switch are applied to the variable capacitance section according to the fifth embodiment.
Fig. 19(a) to (F) are diagrams for explaining the second reading operation corresponding to the conversion gain in the case where the capacitor and the switch are applied to the variable capacitance section according to the fifth embodiment.
The reading operation corresponding to the conversion gain when the capacitor and the switch are applied to the capacitance variable portion according to the fifth embodiment is performed in the same manner as the reading operation corresponding to the conversion gain in the first embodiment described in association with fig. 8(a) to (E).
Therefore, detailed description thereof is omitted.
However, as for the pixel PXLD, for example, the first method shown in fig. 18(a) to (E) or the second method shown in fig. 19(a) to (F) can be adopted as the method of performing the first transfer process of transferring the accumulated charges of the first and second photodiodes PDLS1 by using the first and second photodiodes PDLS1, and the second transfer process of transferring the accumulated charges of the second and second photodiodes PDLS2 by using the second and second transfer transistors TGLS 2-Tr.
In the first method, as shown in fig. 18(a) to (E), the first transfer process and the second transfer process are performed simultaneously in parallel.
In the second method, as shown in fig. 19(a) to (F), the first transfer process and the second transfer process are performed, respectively.
(concrete examples of the construction of the Embedded photodiode PDSL, PDLS1, PDLS2)
Here, a specific configuration example of the embedded first and second photodiodes PDSL, PDLS1, PDLS2 will be described in association with fig. 20.
Fig. 20 is a schematic cross-sectional view showing a configuration example of a main portion of an embedded first photodiode and two second photodiodes of a fifth embodiment of the present invention except for a charge transfer gate portion.
The embedded photodiode (PPD)
That is, the embedded photodiode (PPD)
The embedded
The embedded
In the embedded
In the example of fig. 20, the first photodiode 220(PDSL) is formed between the second conductivity type (p-type)
The first second photodiode 240-1(PDLS1) is formed between the p-
The second photodiode 240-2(PDLS2) is formed between p-
In the present embodiment, the opening AP1 of the light receiving region of the first photodiode PDSL is formed to be larger than the opening AP2 of the light receiving region of the second photodiode PDLS1, 2(AP1> AP2), and the impurity concentration DN1 of the
According to the fifth embodiment, the same effects as those of the first and second embodiments can be obtained.
In addition, by providing a plurality of second photodiodes PDLS and second transfer transistors TGLS, a phase difference detection system that can function to acquire phase difference information of Auto Focus (AF), for example, is available.
Thus, phase difference information in the horizontal (left-right), vertical (up-down), and oblique directions can be obtained.
For example, when reading is performed by the second method in fig. 19(a) to (F), the signal of the first second photodiode PDLS1 and the signal of the second photodiode PDLS2 may be read without reading the signal of the first photodiode PDSL. Thereby, only the phase difference information can be read.
The phase difference detection function is based on a so-called pupil division phase difference system.
The pupil-divided phase difference method forms a pair of divided images by pupil-dividing a light flux passing through an imaging lens, and detects a defocus amount of the imaging lens by detecting a pattern shift (phase shift amount) thereof.
(sixth embodiment)
Fig. 21 is a diagram showing a configuration example of a pixel portion and a capacitance variable portion according to a sixth embodiment of the present invention.
The difference between the pixel PXLA of the second embodiment and the pixel PXLD of the fifth embodiment and the image PXLE of the sixth embodiment is as follows.
In the sixth embodiment, the pixel PXLE is provided with four second photodiodes PDLS and four second transfer transistors TGLS-Tr.
Specifically, the pixel PXLE is provided with a first second photodiode PDLS1, a second photodiode PDLS2, a third second photodiode PDLS3, a fourth second photodiode PDLS4, a first second transfer transistor TGLS1-Tr, a second transfer transistor TGLS2-Tr, a third second transfer transistor TGLS3-Tr, and a second transfer transistor TGLS 4-Tr.
In the pixel PXLE, the first second transfer transistor TGLS1-Tr is connected between the first second photodiode PDLS1 and the output side node ND21, and the second transfer transistor TGLS2-Tr is connected between the second photodiode PDLS2 and the output side node ND 21.
The third second transfer transistor TGLS3-Tr is connected between the third second photodiode PDLS3 and the output side node ND22, and the fourth second transfer transistor TGLS4-Tr is connected between the fourth second photodiode PDLS4 and the output side node ND 22.
The output side node ND21 of the first second transfer transistor TGLS1-Tr and the second transfer transistor TGLS2-Tr is connected to the output side node ND22 of the third second transfer transistor TGLS3-Tr and the third second transfer transistor TGLS3-Tr, and its connection point is connected to the capacitor C82 of the
Thus, according to the sixth embodiment, by providing four second photodiodes PDLS and four second transfer transistors TGLS, phase difference information in the horizontal (left-right), vertical (up-down), and oblique directions can be obtained with the phase difference detection system that can function to obtain phase difference information of, for example, Auto Focus (AF).
(example of arrangement of first and second photodiodes in Pixel PXLE)
Here, an example of the arrangement of the first photodiode and the four second photodiodes in the pixel PXLE of the sixth embodiment will be described.
Fig. 22 is a diagram illustrating an example of the arrangement of the first photodiode and the four second photodiodes in the pixel PXLE according to the sixth embodiment.
The pixel PXLE of the sixth embodiment includes, for example, a first photodiode PDSL and is formed in a rectangular RCT, and second photodiodes PDLS1 to PDLS4 and second transfer transistors TGLS1-Tr to TGLS4-Tr are arranged corresponding to four corners of the first photodiode PDSL, respectively.
In the figure, the pixel PXLE includes four corner portions, i.e., a first corner portion CRN1 of the upper left corner portion, a second corner portion CRN2 of the upper right corner portion, a third corner portion CRN3 of the lower left corner portion, and a fourth corner portion CRN4 of the lower right corner portion.
In the pixel PXLE, for example, the first second photodiode PDLS1 and the first second transfer transistor TGLS1-Tr are arranged in the first
The second photodiode PDLS2 and the second transfer transistor TGLS2-Tr are disposed at the
The third falling portion CRN3 is provided with a third second photodiode PDLS3 and a third second transfer transistor TGLS 3-Tr.
The fourth corner section CRN4 is provided with a fourth second photodiode PDLS4 and a fourth second transfer transistor TGLS 4-Tr.
In the sixth embodiment, the
The reading operation in the reading mode in which the function of widening the dynamic range and the function of detecting a phase difference are embodied will be described in association with the seventh embodiment to be described later.
According to the sixth embodiment, it is needless to say that the same effects as those of the first and second embodiments can be obtained, and by providing four second photodiodes PDLS and four second transfer transistors TGLS, it is possible to be used as a phase difference detection system for obtaining phase difference information of Auto Focus (AF), for example, and to obtain phase difference information in the horizontal (left-right), vertical (up-down), and oblique directions.
(seventh embodiment)
Fig. 23 is a diagram showing a configuration example of a layout of a pixel portion and a capacitance variable portion according to a seventh embodiment of the present invention.
Fig. 24 is a diagram showing a basic layout pattern of each pixel of the pixel portion of fig. 23 viewed from the back side.
In fig. 23 and 24, four pixels are arranged in a 2 × 2 row and column pattern for simplification of the drawings.
The difference between the picture PXLF of the seventh embodiment and the pixel PXLE of the sixth embodiment is as follows.
In the seventh embodiment, the
In fig. 23, the pixel PXLF includes four corners, i.e., a first corner CRN1 of the upper left corner, a second corner CRN2 of the upper right corner, a third corner CRN3 of the lower left corner, and a fourth corner CRN4 of the lower right corner.
In the pixel PXLF, for example, the first second photodiode PDLS1 and the first second transfer transistor TGLS1-Tr are arranged in the first
The second photodiode PDLS2 and the second transfer transistor TGLS2-Tr are disposed at the
The third falling portion CRN3 is provided with a third second photodiode PDLS3 and a third second transfer transistor TGLS 3-Tr.
The fourth corner section CRN4 is provided with a fourth second photodiode PDLS4 and a fourth second transfer transistor TGLS 4-Tr.
In the seventh embodiment, basically, the first second photodiode PDLS1 and the first second transfer transistor TGLS1-Tr of each pixel PXLF share one floating diffusion layer FD with at least one of the second photodiode PDLS2 and the second transfer transistor TGLS2-Tr of the pixel adjacent to the left side in the column direction, the third second photodiode PDLS3 and the third second transfer transistor TGLS3-Tr of the pixel adjacent to the upper side in the row direction, and the fourth second photodiode PDLS4 and the fourth second transfer transistor TGLS4-Tr of the pixel adjacent to the upper left side.
The second photodiode PDLS2 and the second transfer transistor TGLS2-Tr of each pixel PXLF share one floating diffusion layer FD with at least any one of the first second photodiode PDLS1 and the first second transfer transistor TGLS1-Tr of the pixel adjacent to the right side in the column direction, the fourth second photodiode PDLS4 and the fourth second transfer transistor TGLS4-Tr of the pixel adjacent to the upper side in the row direction, and the third second photodiode PDLS3 and the third second transfer transistor TGLS3-Tr of the pixel adjacent to the upper right side.
The third second photodiode PDLS3 and the third second transfer transistor TGLS3-Tr of each pixel PXLF share one floating diffusion layer FD with at least one of the fourth second photodiode PDLS4 and the fourth second transfer transistor TGLS4-Tr of the pixel adjacent to the left side in the column direction, the first second photodiode PDLS1 and the first second transfer transistor TGLS1-Tr of the pixel adjacent to the lower side in the row direction, and the second photodiode PDLS2 and the second transfer transistor TGLS2-Tr of the pixel adjacent to the lower left side.
The fourth second photodiode PDLS4 and the fourth second transfer transistor TGLS4-Tr of each pixel PXLF share one floating diffusion layer FD with at least one of the third second photodiode PDLS3 and the third second transfer transistor TGLS3-Tr of the pixel adjacent to the right side in the column direction, the second photodiode PDLS2 and the second transfer transistor TGLS2-Tr of the pixel adjacent to the lower side in the row direction, and the first second photodiode PDLS1 and the first second transfer transistor TGLS1-Tr of the pixel adjacent to the lower right side.
In the example shown in fig. 23 and 24, the first pixel PXLF1, the second pixel PXLF2, the third pixel PXLF3, and the fourth pixel PXLF4 of the
The first second photodiode PDLS1 and the first second transfer transistor TGLS1-Tr of the first pixel PXLF1, the second photodiode PDLS2 and the second transfer transistor TGLS2-Tr of the second pixel PXLF2, the third second photodiode PDLS3 and the third second transfer transistor TGLS3-Tr of the third pixel PXLF3, and the fourth second photodiode PDLS4 and the fourth second transfer transistor TGLS4-Tr of the fourth pixel PXLF4 share one floating diffusion layer FD.
In the seventh embodiment, the
Next, a reading operation in a reading mode in which the large dynamic range function and the phase difference detection function for detecting the phase difference are embodied in the seventh embodiment will be described.
Fig. 25 is a table showing an outline of the read mode embodying the large dynamic range function and the phase difference detection function according to the seventh embodiment.
The following six read modes are illustrated in fig. 25.
(1) Non-wide dynamic Range mode (Non-HDR),
(2) High dynamic Range mode (HDR),
(3) A first phase difference detection mode (PDAF (V)),
(4) A second phase difference detection mode (PDAF (H)),
(5) A third phase difference detection mode (PDAF (D)), and
(6) in particular, the high dynamic Range mode (Extra-HDR).
An outline of the reading operation in these reading modes will be described.
In the following description, although there is a pattern illustrating a timing chart, a reading operation corresponding to a conversion gain in a case where a capacitor and a switch are applied to the capacitance variable portion according to the seventh embodiment (fig. 21) is basically performed in the same manner as the reading operation corresponding to the conversion gain in the first embodiment described in association with fig. 8.
As described above, the
(1) Non-dynamic Range mode (Non-HDR):
in the Non-high dynamic range mode (Non-HDR), the high dynamic range function and the phase difference detection function cannot be realized.
In this case, the switching transistor SW82-Tr of the
(2) High dynamic Range mode (HDR):
fig. 26(a) to (E) are timing charts showing the reading operation in the high dynamic range mode (HDR) according to the seventh embodiment.
In the case where the first high dynamic range function is implemented in the high dynamic range mode (HDR), the capacitance of the floating diffusion layer FD is held at the first capacitance corresponding to the first conversion gain (HCG) by the
Next, in a first reading period subsequent to the reset period, first conversion gain mode reading is performed, and in a state where the capacitance of the floating diffusion layer FD is held at a first capacitance corresponding to the first conversion gain (HCG), transfer processing in a first transfer period by the first transfer transistor TGSL-Tr after the first reading period is performed, and second first conversion gain mode reading is performed in a second reading period after the first transfer period.
In the high dynamic range mode (HDR), in order to obtain the first second read processing signal Sig2, the capacitance of the floating diffusion layer FD is held at the second capacitance including the capacitance of the capacitor C82 corresponding to the second conversion gain (LCG) by the
Next, in a third read period following the reset period, first second conversion gain mode reading is performed, and in a state where the capacitance of the floating diffusion layer FD is held at a second capacitance corresponding to the second conversion gain (LCG), a transfer process is performed in a second transfer period using the first second transfer transistor TGLS1-Tr, the second transfer transistor TGLS2-Tr, the third second transfer transistor TGLS3-Tr, and the fourth second transfer transistor TGLS4-Tr after the third read period, and second conversion gain mode reading is performed in a fourth read period following the second transfer period.
In the high dynamic range mode (HDR), the first second read processing signal Sig2 is applied as the first high dynamic range signal HDRSig.
In the high dynamic range mode (HDR), the dynamic range is 103dB, the accumulation capacitance (LFWC) corresponds to, for example, 150Ke, and a sufficient saturation capacitance can be obtained, so that the dynamic range can be sufficiently expanded.
(3) First phase difference detection mode (pdaf (v)):
fig. 27(a) to (F) are timing charts showing the reading operation in the first phase difference detection mode (pdaf (v)) according to the seventh embodiment.
In the case where the second wide dynamic range function and the first phase difference detection function are implemented in the first phase difference detection mode (pdaf (v)), the capacitance of the floating diffusion layer FD is held at the first capacitance corresponding to the first conversion gain (HCG) by the
Next, in a first reading period subsequent to the reset period, first conversion gain mode reading is performed, and in a state where the capacitance of the floating diffusion layer FD is held at a first capacitance corresponding to the first conversion gain (HCG), transfer processing in a first transfer period by the first transfer transistor TGSL-Tr after the first reading period is performed, and second first conversion gain mode reading is performed in a second reading period after the first transfer period.
In this case, only the phase difference signal can be read by reading two times without performing this mode.
In the first phase difference detection mode (pdaf (v)), the capacitance of the floating diffusion layer FD is held at the second capacitance including the capacitance of the capacitor C82 corresponding to the second conversion gain (LCG) by the
Next, in a third read period subsequent to the reset period, first second conversion gain mode reading is performed, and in a state where the capacitance of the floating diffusion layer FD is held at a second capacitance corresponding to a second conversion gain (LCG), transfer processing of the first second transfer transistor TGLS1-Tr and the second transfer transistor TGLS2-Tr after the third read period is performed, and second conversion gain mode reading is performed in a fourth read period after the second transfer period.
In the first phase difference detection mode (pdaf (v)), the capacitance of the floating diffusion layer FD is held at the second capacitance including the capacitance of the capacitor C82 corresponding to the second conversion gain (LCG) by the
Next, in a fifth read period following the reset period, the first second conversion gain mode read is performed, and in a state where the capacitance of the floating diffusion layer FD is held at the second capacitance corresponding to the second conversion gain (LCG), the transfer process of the third second transfer transistor TGLS3-Tr and the fourth second transfer transistor TGLS4-Tr after the fifth read period is performed, and the second conversion gain mode read is performed in a sixth read period after the second transfer period.
In the first phase difference detection mode (pdaf (v)), a differential signal (Sig2-Sig3) between the second read processed signal Sig2 and the third second read processed signal Sig3 is applied as the first phase difference detection signal PDAFSig.
In the first phase difference detection mode (pdaf (v)), an added signal (Sig2+ Sig3) of the second read processing signal Sig2 and the third second read processing signal Sig3 is applied as the second large dynamic range signal HDRSig.
In the first phase difference detection mode (pdaf (v)), the dynamic range is 103dB, the accumulation capacitance (LFWC) corresponds to, for example, 150Ke, and a sufficient saturation capacitance can be obtained, so that the dynamic range can be sufficiently expanded.
(4) Second phase difference detection mode (pdaf (h)):
fig. 28(a) to (F) are timing charts showing the reading operation in the second phase difference detection mode (pdaf (h)) according to the seventh embodiment.
In the second phase difference detection mode (pdaf (h)), when the third large dynamic range function and the second phase difference detection function are implemented, the capacitance of the floating diffusion layer FD is held at the first capacitance corresponding to the first conversion gain (HCG) by the
Next, in a first reading period subsequent to the reset period, first conversion gain mode reading is performed, and in a state where the capacitance of the floating diffusion layer FD is held at a first capacitance corresponding to the first conversion gain (HCG), transfer processing in a first transfer period by the first transfer transistor TGSL-Tr after the first reading period is performed, and second first conversion gain mode reading is performed in a second reading period after the first transfer period.
In the second phase difference detection mode (pdaf (h)), the capacitance of the floating diffusion layer FD is held at the second capacitance including the capacitance of the capacitor C82 corresponding to the second conversion gain (LCG) by the
Next, in a third read period subsequent to the reset period, first second conversion gain mode reading is performed, and in a state where the capacitance of the floating diffusion layer FD is held at a second capacitance corresponding to the second conversion gain (LCG), transfer processing of the first second transfer transistor TGLS1-Tr and the third second transfer transistor TGLS3-Tr after the third read period is performed, and second conversion gain mode reading is performed in a fourth read period after the second transfer period.
In the second phase difference detection mode (pdaf (h)), the capacitance of the floating diffusion layer is held at the second capacitance including the capacitance of the capacitor C82 corresponding to the second conversion gain (LCG) by the
Next, in a fifth read period subsequent to the reset period, first second conversion gain mode read is performed, and in a state where the capacitance of the floating diffusion layer FD is held at a second capacitance corresponding to the second conversion gain (LCG), transfer processing of the second transfer transistor TGLS2-Tr and the fourth second transfer transistor TGLS4-Tr after the fifth read period is performed, and second conversion gain mode read is performed in a sixth read period after the second transfer period.
In the second phase difference detection mode (pdaf (h)), a differential signal (Sig2-Sig3) between the fourth second read processing signal Sig2 and the fifth second read processing signal Sig3 is applied as the second phase difference detection signal PDAFSig.
In the second phase difference detection mode (pdaf (h)), an added signal (Sig2+ Sig3) of the fourth second read processing signal Sig2 and the fifth second read processing signal Sig3 is applied as the third large dynamic range signal HDRSig.
In the second phase difference detection mode (pdaf (h)), the dynamic range is 103dB, the accumulation capacitance (LFWC) is 150Ke, and sufficient saturation capacitance can be obtained, and the dynamic range can be sufficiently expanded.
(5) Third phase difference detection mode (pdaf (d)):
fig. 29(a) to (F) are timing charts showing the reading operation in the third phase difference detection mode (pdaf (d)) according to the seventh embodiment.
In the third phase difference detection mode (pdaf (d)), when the fourth large dynamic range function and the third phase difference detection function are implemented, the capacitance of the floating diffusion layer FD is held at the first capacitance corresponding to the first conversion gain (HCG) by the
Next, in a first reading period subsequent to the reset period, first conversion gain mode reading is performed, and in a state where the capacitance of the floating diffusion layer FD is held at a first capacitance corresponding to the first conversion gain (HCG), transfer processing in a first transfer period by the first transfer transistor TGLS1-Tr after the first reading period is performed, and second first conversion gain mode reading is performed in a second reading period after the first transfer period.
In the third phase difference detection mode (pdaf (d)), the capacitance of the floating diffusion layer FD is held at the second capacitance including the capacitance of the capacitor C82 corresponding to the second conversion gain (LCG) by the
Next, in a third read period subsequent to the reset period, first second conversion gain mode reading is performed, and in a state where the capacitance of the floating diffusion layer FD is held at a second capacitance corresponding to the second conversion gain (LCG), transfer processing of the first second transfer transistor TGLS1-Tr and the fourth second transfer transistor TGLS4-Tr after the third read period is performed, and second conversion gain mode reading is performed in a fourth read period after the second transfer period.
In the third phase difference detection mode (pdaf (d)), the capacitance of the floating diffusion layer FD is held at the second capacitance including the capacitance of the capacitor C82 corresponding to the second conversion gain (LCG) by the
Next, in a fifth read period subsequent to the reset period, first second conversion gain mode read is performed, and in a state where the capacitance of the floating diffusion layer FD is held at a second capacitance corresponding to the second conversion gain (LCG), transfer processing of the second transfer transistor TGLS2-Tr and the third second transfer transistor TGLS3-Tr after the fifth read period is performed, and second conversion gain mode read is performed in a sixth read period after the second transfer period.
In the third phase difference detection mode (pdaf (d)), a differential signal (Sig2-Sig3) between the sixth second read processed signal Sig2 and the seventh second read processed signal Sig3 is applied as the third phase difference detection signal PDAFSig.
In the third phase difference detection mode (pdaf (d)), an added signal (Sig2+ Sig3) of the sixth second read processing signal Sig2 and the seventh second read processing signal Sig3 is applied as the fourth large dynamic range signal HDRSig.
In the third phase difference detection mode (pdaf (d)), the dynamic range is 103dB, the accumulation capacitance (LFWC) corresponds to, for example, 150Ke, and a sufficient saturation capacitance can be obtained, so that the dynamic range can be sufficiently expanded.
(6) Special high dynamic Range mode (Extra-HDR):
fig. 30(a) to (F) are diagrams showing timing charts of the reading operation in the special high dynamic range mode (Extra-HDR) according to the seventh embodiment.
In the case where the fifth high dynamic range function is implemented in the special high dynamic range mode (Extra-HDR), the capacitance of the floating diffusion layer FD is held at the first capacitance corresponding to the first conversion gain (HCG) by the
Next, in a first reading period subsequent to the reset period, first conversion gain mode reading is performed, and in a state where the capacitance of the floating diffusion layer FD is held at a first capacitance corresponding to the first conversion gain (HCG), transfer processing in a first transfer period by the first transfer transistor TGLS1-Tr after the first reading period is performed, and second first conversion gain mode reading is performed in a second reading period after the first transfer period.
In the special high dynamic range mode (Extra-HDR), in order to obtain the eighth second read processing signal Sig2, the capacitance of the floating diffusion layer FD is held at the second capacitance including the capacitance of the capacitor C82 corresponding to the second conversion gain (LCG) by the
Next, in a third read period following the reset period, first second conversion gain mode reading is performed, and in a state where the capacitance of the floating diffusion layer FD is held at a second capacitance corresponding to the second conversion gain (LCG), transfer processing of the first second transfer transistor TGLS1-Tr, the second transfer transistor TGLS2-Tr, and the third second transfer transistor TGLS3-Tr after the third read period is performed, and second conversion gain mode reading is performed in a fourth read period following the second transfer period.
In the special high dynamic range mode (Extra-HDR), in order to obtain the ninth second read processing signal Sig3, the capacitance of the floating diffusion layer FD is held at the second capacitance including the capacitance of the capacitor C82 corresponding to the second conversion gain (LCG) by the
Next, in a fifth reading period subsequent to the reset period, first second conversion gain mode reading is performed, and in a state where the capacitance of the floating diffusion layer FD is held at a second capacitance corresponding to the second conversion gain (LCG), transfer processing of the fourth second transfer transistor TGLS4-Tr after the fifth reading period is performed, and second conversion gain mode reading is performed in a sixth reading period after the second transfer period.
In this case, it is preferable to reduce the sensitivity of the fourth
In the special large dynamic range mode (Extra-HDR), an added signal (Sig2+ Sig3) of the eighth second read processing signal Sig2 and the third ninth read processing signal Sig3 is applied as the fifth large dynamic range signal HDRSig.
In the special high dynamic range mode (Extra-HDR), the dynamic range is 108dB, the accumulation capacitance (LFWC) corresponds to 250Ke, for example, and a sufficient saturation capacitance can be obtained, and the dynamic range can be sufficiently expanded.
According to the seventh embodiment, for example, the readout of at least one of the phase difference detection functions that exhibits at least the large dynamic range function and the phase difference detection function that detects the phase difference can be performed by a combination of the accumulated charge readout processes for the first photodiode PDSL1 of the first pixel PXLF1, the first second photodiode PDLS1 of the first pixel PXLF1, the second photodiode PDLS2 of the second pixel PXLF2, the third second photodiode PDLS3 of the third pixel PXLF3, and the fourth second photodiode PDLS4 of the
Fig. 31 is a graph showing sensitivity characteristics of the first photodiode PDSL and the second photodiode PDLS in each read mode according to the seventh embodiment of the present invention.
Fig. 32(a) and (B) are graphs showing the sensitivity characteristics after linearization of the high dynamic range mode (HDR), the third phase difference detection mode (pdaf (d)), and the special high dynamic range mode (Extra-HDR) according to the seventh embodiment of the present invention.
Fig. 32(a) shows the input-output characteristics of the signal, and fig. 32(B) shows the SNR characteristics.
As shown in fig. 32(a) and (B), it is known that the seventh embodiment is improved by 10dB in the high dynamic range mode (HDR) and the third phase difference detection mode (pdaf (d)), and further improved by 5dB in the special high dynamic range mode (Extra-HDR).
Further, according to the seventh embodiment, it is needless to say that the same effects as those of the first and second embodiments can be obtained, and by providing four second photodiodes PDLS and four second transfer transistors TGLS, it is possible to be used as a phase difference detection system for obtaining phase difference information of Auto Focus (AF), for example, and to obtain phase difference information in the horizontal (left-right), vertical (up-down), and oblique directions.
The read operation in each read mode can be similarly applied to the pixel PXLE in fig. 22 in the sixth embodiment.
Fig. 33(a) to (C) are diagrams for explaining that the reading operation in each reading mode of the seventh embodiment can be similarly applied to the pixel PXLE of fig. 22 of the sixth embodiment.
However, fig. 33(a) to (C) show only the phase difference detection mode (PDAF), but other modes of reading operation can be applied.
Fig. 33(a) shows an outline of the reading operation in the first phase difference detection mode (pdaf (v)), fig. 33(B) shows an outline of the reading operation in the second phase difference detection mode (pdaf (h)), and fig. 33(C) shows an outline of the reading operation in the third phase difference detection mode (pdaf (d)).
(eighth embodiment)
Fig. 34 is a diagram illustrating an example of the arrangement of the first photodiode and the eight second photodiodes in the pixel according to the eighth embodiment.
The pixel PXLG of the eighth embodiment is different from the pixel PXLE of fig. 22 in that it includes eight second photodiodes PDLS (1 to 8).
The pixel PXLG is, for example, formed of a rectangular RCT including a first photodiode PDSL, and second photodiodes PDLS1 to PDLS8 (second transfer transistors TGLS1-Tr to TGLS8-Tr) are arranged corresponding to four corner portions of the first photodiode PDSL, respectively.
Similarly to the example of fig. 22, the pixel PXLG includes four corner portions, i.e., a first corner portion CRN1 of the upper left corner portion, a second corner portion CRN2 of the upper right corner portion, a third corner portion CRN3 of the lower left corner portion, and a fourth corner portion CRN4 of the lower right corner portion.
In the pixel PXLG, the first second photodiode PDLS1 and the first second transfer transistor TGLS1-Tr, and the second photodiode PDLS2 and the second transfer transistor TGLS2-Tr are arranged in pairs in the first
At the second corner, a third second photodiode PDLS3 and a third second transfer transistor TGLS3-Tr, and a fourth second photodiode PDSL4 and a fourth second transfer transistor TGLS4-Tr are arranged in pairs.
In the third corner section CRN3, a fifth second photodiode PDLS5 and a fifth second transfer transistor TGLS5-Tr, and a sixth second photodiode PDLS6 and a sixth second transfer transistor TGLS6-Tr are arranged in pairs.
In the fourth corner section CRN4, a seventh second photodiode PDLS7 and a seventh second transfer transistor TGLS7-Tr, and an eighth second photodiode PDLS8 and an eighth second transfer transistor TGLS8-Tr are arranged in pairs.
In the eighth embodiment, the
According to the eighth embodiment, it is needless to say that the same effects as those of the first and second embodiments can be obtained, and by providing eight second photodiodes PDLS and eight second transfer transistors TGLS, it is possible to be used as a phase difference detection system for obtaining phase difference information of Auto Focus (AF), for example, and to obtain phase difference information in the horizontal (left-right), vertical (up-down), and oblique directions.
(application example 1)
Fig. 35 is a schematic cross-sectional view showing another example of the structure of the embedded first photodiode and the embedded second photodiode of the present embodiment shown in fig. 5.
While the description has been made in connection with fig. 5 (and fig. 20) on an example of the structure of the pixel including the embedded first photodiode PDSL and the second photodiode PDLS, the pixel structure is not limited to this, and for example, as shown in fig. 35, a more compact structure in which the junction (junction) portion 250 and the accumulation region 260 are stacked on the photoelectric conversion region can be adopted.
The first photodiode 220h (pdsl) of fig. 35 is configured such that the n layer (first conductive type semiconductor layer) 221n has a three-layer structure in the normal direction of the substrate 210 (Z direction of the orthogonal coordinate system in the figure).
In this example, an n-
Further,
The second photodiode 240h (pdls) of fig. 35 is configured such that the n layer (first conductive type semiconductor layer) 241n has a single-layer structure in the normal direction of the substrate 210 (Z direction of the orthogonal coordinate system in the figure).
In this example,
The p-
In this example,
The p-
In this example,
The p-
In this example, a p-
In the example of fig. 35, n +
This structure is an example, and other laminated structures may be employed.
(application example 2)
Fig. 36(a) and (B) are diagrams for explaining that the solid-state imaging device according to the embodiment of the present invention can be applied to both a front-surface illumination type image sensor and a back-surface illumination type image sensor.
Fig. 36(a) shows a schematic configuration of a front-side illumination type image sensor, and fig. 36(B) shows a schematic configuration of a back-side illumination type image sensor.
In fig. 36(a) and (B), reference numeral 91 denotes a microlens array, 92 denotes a color filter group, 93 denotes a wiring layer, and 94 denotes a silicon substrate.
As shown in fig. 36(a) and (B), the solid-
The solid-
Fig. 37 is a diagram showing an example of a configuration of an electronic apparatus mounted with a camera system to which the solid-state imaging device according to the embodiment of the present invention is applied.
As shown in fig. 37, the present
The
The
The
The image signal processed by the
As described above, by mounting the solid-state
Further, it is possible to realize an electronic device such as a monitoring camera and a medical endoscope camera which is used for applications in which there are restrictions on installation conditions of the camera, such as an installation size, the number of connectable cables, a cable length, and an installation height.
Description of the main elements
10. 10A to 10G: solid-state image pickup device
20. 20A to 20G: pixel section
PDSL: first photodiode (first photoelectric conversion part)
PDLS, PDLS 1-PDLS 8: second photodiode (second photoelectric conversion part)
TGSL-Tr: first transfer transistor (first transfer element)
TGLS-Tr, TGLS1-Tr to TGLS 8-Tr: second transfer transistor (second transfer element)
210: semiconductor substrate
220: a first photodiode
240: second photodiode
30: vertical scanning circuit
40: reading circuit
50: horizontal scanning circuit
60: sequential control circuit
70: reading unit
80. 80A-80C: variable capacitance section
C81, C82: capacitor with a capacitor element
SW81-Tr, SW 82-Tr: switch transistor (switch element)
81: first combination switch
82: second combination switch
83: overflow drain (OFD) gate
91: microlens array
92: color filter set
93: wiring layer
94: silicon substrate
100: electronic device
110: CMOS image sensor
120: optical system
130: signal processing circuit (PRC)
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