阅读说明：本技术 Tdc控制系统、方法和膜厚检测装置 (TDC control system, method and film thickness detection device ) 是由 弗拉基米尔·克雷姆尼察 王龙 敬文华 于 2019-11-20 设计创作，主要内容包括：本发明的实施例提供了一种TDC控制系统、方法和膜厚检测装置,涉及质量检测技术领域。该TDC控制系统包括均与微处理器电连接的状态机、所述第一数据选择输出模块和时间数字转换器,状态机与第二数据选择输出模块电连接,第一数据选择输出模块、第二数据选择输出模块均与时间数字转换器电连接,第一数据选择输出模块和第二数据选择输出模块均包括多个具有不同延时时长的延时通道。通过第一数据选择输出模块和第二数据选择输出模块可调节开始信号和结束信号向时间数字转换器发送的时间,使得较短延时链长度的时间数字转换器能够得到准确和稳定的第一时间间隔值和第二时间间隔值,从而获得更准确和稳定的待测频率波形的频率。(The embodiment of the invention provides a TDC control system, a TDC control method and a film thickness detection device, and relates to the technical field of quality detection. The TDC control system comprises a state machine, a first data selection output module and a time-to-digital converter, wherein the state machine, the first data selection output module and the time-to-digital converter are electrically connected with a microprocessor, the state machine is electrically connected with a second data selection output module, the first data selection output module and the second data selection output module are electrically connected with the time-to-digital converter, and the first data selection output module and the second data selection output module respectively comprise a plurality of delay channels with different delay time lengths. The time for sending the start signal and the end signal to the time-to-digital converter can be adjusted through the first data selection output module and the second data selection output module, so that the time-to-digital converter with shorter delay chain length can obtain an accurate and stable first time interval value and a stable second time interval value, and more accurate and stable frequency of the frequency waveform to be measured is obtained.)

1. A TDC control system is characterized by comprising a microprocessor, a state machine, a first data selection output module, a second data selection output module and a time-to-digital converter, wherein the state machine, the first data selection output module and the time-to-digital converter are electrically connected with the microprocessor, the state machine is electrically connected with the second data selection output module, the first data selection output module and the second data selection output module are electrically connected with the time-to-digital converter, and the first data selection output module and the second data selection output module respectively comprise a plurality of delay channels with different delay time lengths;

the state machine is used for generating a first measuring signal according to the received frequency waveform to be measured and the reference waveform when receiving a first working signal sent by the microprocessor, and sending the first measuring signal to the first data selection output module; when a second working signal sent by the microprocessor is received, generating a second measuring signal according to the frequency waveform to be measured and the reference waveform, and sending the second measuring signal to the second data selection output module;

the microprocessor is used for sending a first control instruction to the first data selection output module and sending a second control instruction to the state machine so that the state machine can generate a selection instruction according to the second control instruction, and the state machine sends the selection instruction to the second data selection output module;

the first data selection output module is used for selecting a delay channel corresponding to the first control instruction according to the first control instruction to perform delay processing on the first measurement signal to obtain a start signal and sending the start signal to the time-to-digital converter;

the second data selection output module is used for selecting a delay channel corresponding to the selection instruction according to the selection instruction to perform delay processing on the second measurement signal to obtain an end signal and sending the end signal to the time-to-digital converter;

the time-to-digital converter is used for calculating a first time interval value and a second time interval value according to the starting signal and the ending signal and sending the first time interval value and the second time interval value to the microprocessor;

and the microprocessor is used for calculating the frequency of the frequency waveform to be measured according to the first time interval value and the second time interval value.

2. The TDC control system according to claim 1, wherein the state machine is configured to, when receiving a first working signal sent by the microprocessor, if receiving the frequency waveform to be measured and the reference waveform, output the first measurement signal at a time when an amplitude of the reference waveform jumps after the amplitude of the frequency waveform to be measured jumps; and the second measuring signal is also used for outputting the second measuring signal at the moment when the amplitude of the reference waveform jumps after the amplitude of the frequency waveform to be measured jumps when the second working signal sent by the microprocessor is received.

3. The TDC control system according to claim 1, wherein the first data selection output module comprises a first data selector and a plurality of buffers, the plurality of buffers are electrically connected to the state machine in sequence, the first data selector is electrically connected to the state machine and the plurality of buffers to form a plurality of delay paths with different delay durations, and the first data selector is further electrically connected to both the microprocessor and the time-to-digital converter.

4. The TDC control system according to claim 1, wherein the second data selection output module comprises a second data selector electrically connected to the state machine and an inverter electrically connected between the state machine and the second data selector to form a plurality of delay paths having different delay durations, and the second data selector is further electrically connected to the time-to-digital converter.

5. The TDC control system according to claim 1, further comprising a delay module, wherein the state machine is electrically connected to the first data selection output module and the second data selection output module through the delay module;

the time delay module is used for carrying out time delay processing on the first measuring signal or the second measuring signal, sending the first measuring signal after time delay to the first data selection output module, and sending the second measuring signal after time delay to the second data selection output module.

6. The TDC control system of claim 5, further comprising a counting module electrically connected to the state machine, the microprocessor, and the delay module;

the counting module is used for calculating the number of pulses of the frequency waveform to be detected and the number of pulses of the reference waveform according to the delayed first measuring signal and the delayed second measuring signal output by the delay module, and transmitting the number of pulses of the frequency waveform to be detected and the number of pulses of the reference waveform to the microprocessor;

and the microprocessor is used for calculating the frequency of the frequency waveform to be detected according to the number of pulses of the frequency waveform to be detected, the number of pulses of the reference waveform, the first time interval value and the second time interval value.

7. The TDC control system of claim 6, wherein the counting module comprises a first counter and a second counter, the first counter is electrically connected to the state machine, the microprocessor and the delay module, and the second counter is electrically connected to the state machine, the microprocessor and the delay module;

the first counter is used for starting to count the pulses of the frequency waveform to be measured according to the delayed first measuring signal and stopping counting the pulses of the frequency waveform to be measured according to the delayed second measuring signal so as to obtain the number of the pulses of the frequency waveform to be measured;

and the second counter is used for starting to count the pulses of the reference waveform according to the delayed first measuring signal and stopping counting the pulses of the reference waveform according to the delayed second measuring signal so as to obtain the number of the pulses of the reference waveform.

8. A TDC control method is characterized in that the TDC control method is applied to a TDC control system, the TDC control system comprises a microprocessor, a state machine, a first data selection output module, a second data selection output module and a time-to-digital converter, the state machine, the first data selection output module and the time-to-digital converter are all electrically connected with the microprocessor, the state machine is electrically connected with the second data selection output module, the first data selection output module and the second data selection output module are all electrically connected with the time-to-digital converter, the first data selection output module and the second data selection output module both comprise a plurality of delay channels with different delay time lengths, and the method comprises the following steps:

when the state machine receives a first working signal sent by the microprocessor, a first measuring signal is generated according to the received frequency waveform to be measured and the reference waveform, and the first measuring signal is sent to the first data selection output module; when a second working signal sent by the microprocessor is received, generating a second measuring signal according to the frequency waveform to be measured and the reference waveform, and sending the second measuring signal to the second data selection output module;

the microprocessor sends a first control instruction to the first data selection output module and a second control instruction to the state machine so that the state machine can generate a selection instruction according to the second control instruction, and the state machine sends the selection instruction to the second data selection output module;

the first data selection output module selects a delay channel corresponding to the first control instruction according to the first control instruction to perform delay processing on the first measurement signal to obtain a start signal, and sends the start signal to the time-to-digital converter;

the second data selection output module selects a delay channel corresponding to the selection instruction according to the selection instruction to perform delay processing on the second measurement signal to obtain an end signal, and sends the end signal to the time-to-digital converter;

the time-to-digital converter calculates a first time interval value and a second time interval value according to the starting signal and the ending signal and sends the first time interval value and the second time interval value to the microprocessor;

and the microprocessor calculates the frequency of the frequency waveform to be measured according to the first time interval value and the second time interval value.

9. The TDC control method according to claim 8, wherein the microprocessor is preset with preset interval values, the microprocessor is prestored with a mapping table, the mapping table is used for representing the corresponding relationship between each first time interval value and each delay channel of the first data selection output module, and the corresponding relationship between each second time interval value and each delay channel of the second data selection output module, the step of sending the first control command to the first data selection output module by the microprocessor, and the step of sending the second control command to the state machine comprises:

when the microprocessor sends a first control instruction to the first data selection output module for the first time and sends a second control instruction to the state machine for the first time, the microprocessor determines the first control instruction and the second control instruction according to preset initial channel parameters;

when the microprocessor sends a first control instruction to the first data selection output module for a non-first time and sends a second control instruction to the state machine for a non-first time, the microprocessor matches a first time interval value and a second time interval value generated by the time-to-digital converter with the mapping relation table to determine the first control instruction and the second control instruction; so that the new first and second time interval values generated by the time to digital converter match the preset interval value.

10. A film thickness detection device is characterized by comprising a quartz crystal microbalance, a high-frequency oscillator and the TDC control system as claimed in any one of claims 1 to 7, wherein the quartz crystal microbalance and the high-frequency oscillator are electrically connected with the TDC control system;

the quartz crystal microbalance is used for generating a frequency waveform to be detected;

the high frequency oscillator is used for generating a reference waveform.

Technical Field

The invention relates to the technical field of quality detection, in particular to a TDC control system and method and a film thickness detection device.

Background

The quartz crystal microbalance is a very sensitive mass detection instrument, the measurement precision of which can reach nanogram level, and the mass change which can be measured theoretically is equal to a fraction of a single sub-layer or an atomic layer. The quartz crystal microbalance utilizes the piezoelectric effect of quartz crystal, converts the surface quality change of the quartz crystal electrode into the frequency change of the output electric signal of the quartz crystal oscillation circuit, and further obtains high-precision data through frequency detection equipment.

The length of a delay chain of a Time-to-Digital converter (TDC) used in the conventional frequency detection device is related to a start signal and an end signal generated by a frequency waveform to be detected output by a quartz crystal microbalance. When the time difference between the start signal and the end signal is large, the delay chain of the time-to-digital converter is long, so that the time-to-digital converter is easily interfered by the outside, the measurement precision is reduced, the hardware cost is increased, and the hardware resource is wasted.

Disclosure of Invention

The invention aims to provide a TDC control system, a TDC control method and a film thickness detection device, which can generate a proper start signal and an end signal, reduce the interference of the outside on a time-to-digital converter, improve the measurement precision and save hardware resources.

Embodiments of the invention may be implemented as follows:

in a first aspect, an embodiment of the present invention provides a TDC control system, including a microprocessor, a state machine, a first data selection output module, a second data selection output module, and a time-to-digital converter, where the state machine, the first data selection output module, and the time-to-digital converter are all electrically connected to the microprocessor, the state machine is electrically connected to the second data selection output module, the first data selection output module and the second data selection output module are all electrically connected to the time-to-digital converter, and the first data selection output module and the second data selection output module both include a plurality of delay channels with different delay durations; the state machine is used for generating a first measuring signal according to the received frequency waveform to be measured and the reference waveform when receiving a first working signal sent by the microprocessor, and sending the first measuring signal to the first data selection output module; when a second working signal sent by the microprocessor is received, generating a second measuring signal according to the frequency waveform to be measured and the reference waveform, and sending the second measuring signal to the second data selection output module; the microprocessor is used for sending a first control instruction to the first data selection output module and sending a second control instruction to the state machine so that the state machine can generate a selection instruction according to the second control instruction, and the state machine sends the selection instruction to the second data selection output module; the first data selection output module is used for selecting a delay channel corresponding to the first control instruction according to the first control instruction to perform delay processing on the first measurement signal to obtain a start signal and sending the start signal to the time-to-digital converter; the second data selection output module is used for selecting a delay channel corresponding to the selection instruction according to the selection instruction to perform delay processing on the second measurement signal to obtain an end signal and sending the end signal to the time-to-digital converter; the time-to-digital converter is used for calculating a first time interval value and a second time interval value according to the starting signal and the ending signal and sending the first time interval value and the second time interval value to the microprocessor; and the microprocessor is used for calculating the frequency of the frequency waveform to be measured according to the first time interval value and the second time interval value.

In a second aspect, an embodiment of the present invention provides a TDC control method, which is applied to a TDC control system, where the TDC control system includes a microprocessor, a state machine, a first data selection output module, a second data selection output module, and a time-to-digital converter, the state machine, the first data selection output module, and the time-to-digital converter are all electrically connected to the microprocessor, the state machine is electrically connected to the second data selection output module, the first data selection output module and the second data selection output module are all electrically connected to the time-to-digital converter, and the first data selection output module and the second data selection output module each include a plurality of delay channels with different delay durations, and the method includes: when the state machine receives a first working signal sent by the microprocessor, a first measuring signal is generated according to the received frequency waveform to be measured and the reference waveform, and the first measuring signal is sent to the first data selection output module; when a second working signal sent by the microprocessor is received, generating a second measuring signal according to the frequency waveform to be measured and the reference waveform, and sending the second measuring signal to the second data selection output module; the microprocessor sends a first control instruction to the first data selection output module and a second control instruction to the state machine so that the state machine can generate a selection instruction according to the second control instruction, and the state machine sends the selection instruction to the second data selection output module; the first data selection output module selects a delay channel corresponding to the first control instruction according to the first control instruction to perform delay processing on the first measurement signal to obtain a start signal, and sends the start signal to the time-to-digital converter; the second data selection output module selects a delay channel corresponding to the selection instruction according to the selection instruction to perform delay processing on the second measurement signal to obtain an end signal, and sends the end signal to the time-to-digital converter; the time-to-digital converter calculates a first time interval value and a second time interval value according to the starting signal and the ending signal and sends the first time interval value and the second time interval value to the microprocessor; and the microprocessor calculates the frequency of the frequency waveform to be measured according to the first time interval value and the second time interval value.

In a third aspect, an embodiment of the present invention provides a film thickness detection apparatus, including a quartz crystal microbalance and a TDC control system according to any one of the foregoing embodiments of a high-frequency oscillator, where the quartz crystal microbalance and the high-frequency oscillator are both electrically connected to the TDC control system; the quartz crystal microbalance is used for generating a frequency waveform to be detected; the high frequency oscillator is used for generating a reference waveform.

The embodiment of the invention has the advantages that the first data selection output module selects the delay channel corresponding to the first control instruction according to the first control instruction sent by the microprocessor to carry out delay processing on the first measurement signal to obtain a start signal, and sends the start signal to the time-to-digital converter; selecting a delay channel corresponding to the selection instruction according to the selection instruction sent by the state machine through a second data selection output module to perform delay processing on the second measurement signal to obtain an end signal, and sending the end signal to the time-to-digital converter; and the time-to-digital converter calculates a first time interval value and a second time interval value according to the start signal and the end signal, and sends the first time interval value and the second time interval value to the microprocessor so that the microprocessor can calculate the frequency of the frequency waveform to be measured according to the first time interval value and the second time interval value. Therefore, the time of the start signal sent to the time digital converter can be adjusted by the first data selection output module through selection of the delay channels of the first data selection output module and the second data selection output module by the microprocessor, the time of the end signal sent to the time digital converter can be adjusted by the second data selection output module, the condition that the time difference between the start signal and the end signal is large can be avoided, the time digital converter with the shorter delay chain length can obtain the accurate and stable first time interval value and second time interval value, the more accurate and stable frequency of the frequency waveform to be detected is obtained, and hardware resources of the TDC control system are saved.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed to be used in the embodiments will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present invention and therefore should not be considered as limiting the scope, and for those skilled in the art, other related drawings can be obtained according to the drawings without inventive efforts.

Fig. 1 is a block diagram of a film thickness detection apparatus according to an embodiment of the present invention;

fig. 2 is a block diagram of a TDC control system according to an embodiment of the present invention;

FIG. 3 is a circuit diagram of a TDC control system according to an embodiment of the present invention;

FIG. 4 is a circuit diagram of a time-to-digital converter according to an embodiment of the present invention;

fig. 5 is a schematic diagram of a frequency waveform to be measured and a reference waveform obtained by the TDC control system according to the embodiment of the present invention;

fig. 6 is a block diagram of another TDC control system according to an embodiment of the present invention;

FIG. 7 is a circuit diagram of another TDC control system according to an embodiment of the present invention;

fig. 8 is a flowchart illustrating a TDC control method according to an embodiment of the present invention.

Icon: 10-a film thickness detection device; 100-TDC control system; 110-a state machine; 120-a first data selection output module; 121-a first data selector; 122-a buffer; 130-a second data selection output module; 131-a second data selector; 132-an inverter; 140-a time-to-digital converter; 150-a delay module; 160-a counting module; 161-a first counter; 162-a second counter; 170-a communication module; 180-a microprocessor; 300-quartz crystal microbalance; 400-high frequency oscillator.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. The components of embodiments of the present invention generally described and illustrated in the figures herein may be arranged and designed in a wide variety of different configurations.

Thus, the following detailed description of the embodiments of the present invention, presented in the figures, is not intended to limit the scope of the invention, as claimed, but is merely representative of selected embodiments of the invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined and explained in subsequent figures.

In the description of the present invention, it should be noted that if the terms "upper", "lower", "inside", "outside", etc. indicate an orientation or a positional relationship based on that shown in the drawings or that the product of the present invention is used as it is, this is only for convenience of description and simplification of the description, and it does not indicate or imply that the device or the element referred to must have a specific orientation, be constructed in a specific orientation, and be operated, and thus should not be construed as limiting the present invention.

Furthermore, the appearances of the terms "first," "second," and the like, if any, are used solely to distinguish one from another and are not to be construed as indicating or implying relative importance.

It should be noted that the features of the embodiments of the present invention may be combined with each other without conflict.

Referring to fig. 1, a block diagram of an implementable structure of a film thickness detection apparatus 10 provided in the present embodiment is shown, in which the film thickness detection apparatus 10 includes a quartz crystal microbalance 300, a high-frequency oscillator 400 and a TDC control system 100, and both the quartz crystal microbalance 300 and the high-frequency oscillator 400 are electrically connected to the TDC control system 100. The quartz crystal microbalance 300 is used for generating a frequency waveform to be detected and sending the frequency waveform to be detected to the TDC control system 100; the high frequency oscillator 400 is configured to generate a reference waveform and send the reference waveform to the TDC control system 100; the TDC control system 100 is configured to calculate a frequency waveform to be measured and a reference waveform to obtain a number of pulses of the frequency waveform to be measured, a number of pulses of the reference waveform, a first time interval value and a second time interval value between the frequency waveform to be measured and the reference waveform, and calculate a frequency of the frequency waveform to be measured according to the number of pulses of the frequency waveform to be measured, the number of pulses of the reference waveform, the first time interval value and the second time interval value between the frequency waveform to be measured and the reference waveform.

Referring to fig. 2, which is a block diagram of an implementable structure of the TDC control system 100 shown in fig. 1, the TDC control system 100 includes a microprocessor 180, a state machine 110, a first data selection output module 120, a second data selection output module 130, and a time-to-digital converter 140, the state machine 110, the first data selection output module 120, and the time-to-digital converter 140 are all electrically connected to the microprocessor 180, the state machine 110 is electrically connected to the second data selection output module 130, the first data selection output module 120, and the second data selection output module 130 are all electrically connected to the time-to-digital converter 140, and the first data selection output module 120 and the second data selection output module 130 both include a plurality of delay channels with different delay durations.

In this embodiment, the state machine 110 is configured to generate a first measurement signal according to the received frequency waveform to be measured and the reference waveform when receiving a first working signal sent by the microprocessor 180, and send the first measurement signal to the first data selection output module 120; when receiving the second working signal sent by the microprocessor 180, a second measurement signal is generated according to the frequency waveform to be measured and the reference waveform, and the second measurement signal is sent to the second data selection output module 130. The microprocessor 180 is configured to send a first control instruction to the first data selection output module 120, and is further configured to send a second control instruction to the state machine 110, so that the state machine 110 generates a selection instruction according to the second control instruction, and the state machine 110 sends the selection instruction to the second data selection output module 130. The first data selection output module 120 is configured to select a delay channel corresponding to the first control instruction according to the first control instruction to perform delay processing on the first measurement signal, obtain a start signal, and send the start signal to the time-to-digital converter 140. The second data selection output module 130 is configured to select a delay channel corresponding to the selection instruction according to the selection instruction to perform delay processing on the second measurement signal to obtain an end signal, and send the end signal to the time-to-digital converter 140. The time-to-digital converter 140 is configured to calculate a first time interval value and a second time interval value according to the start signal and the end signal, and send the first time interval value and the second time interval value to the microprocessor 180. The microprocessor 180 is configured to calculate a frequency of the frequency waveform to be measured according to the first time interval value and the second time interval value.

It can be understood that the state machine 110 is electrically connected to both the quartz crystal microbalance 300 and the high frequency oscillator 400, and when receiving the first working signal sent by the microprocessor 180, if receiving the frequency waveform to be measured and the reference waveform, the state machine 110 is configured to output a first measurement signal at a time when the amplitude of the reference waveform jumps after the amplitude of the frequency waveform to be measured jumps; and is further configured to output a second measurement signal at a time when the amplitude of the reference waveform jumps after the amplitude of the frequency waveform to be measured jumps when receiving a second working signal sent by the microprocessor 180.

In other words, after the state machine 110 receives the first working signal, the frequency waveform to be measured, and the reference waveform sent by the microprocessor 180, the state machine 110 outputs the first measurement signal at the time when the reference waveform has a rising edge or a falling edge (i.e., after the amplitude of the frequency waveform to be measured jumps) after the frequency waveform to be measured has a rising edge or a falling edge (i.e., after the amplitude of the frequency waveform to be measured jumps); the state machine 110 outputs the first measurement signal at a time when the rising edge or the falling edge of the reference waveform occurs for the first time after the rising edge or the falling edge of the frequency waveform to be measured occurs; or after the rising edge or the falling edge of the frequency waveform to be measured occurs, the rising edge or the falling edge of the frequency waveform to be measured occurs for a preset number of times, and the preset number of times is a parameter preset by a worker according to actual requirements. When receiving the second working signal, the state machine 110 outputs a second measurement signal at the moment when the rising edge or the falling edge of the reference waveform occurs after the rising edge or the falling edge of the frequency waveform to be measured occurs; the second measurement signal output by the state machine 110 may refer to a time when the waveform of the frequency to be measured has a rising edge or a falling edge, where the rising edge or the falling edge has a preset number of times, the preset number of times is a parameter preset by a worker according to an actual requirement, and the preset number of times may be 1 time or multiple times. Because the frequency of the frequency waveform to be measured is lower than the frequency of the reference waveform, the rising edge and the falling edge of the frequency waveform to be measured are generally not synchronous with the rising edge and the falling edge of the reference waveform, and the frequency waveform to be measured and the reference waveform can be synchronized by outputting the measurement signal by the state machine 110.

As shown in fig. 3, which is a circuit diagram of an implementation of the TDC control system 100 shown in fig. 2, the first data selection output module 120 includes a first data selector 121 and a plurality of buffers 122, the plurality of buffers 122 are electrically connected to the state machine 110 in sequence, the first data selector 121 is electrically connected to both the state machine 110 and the plurality of buffers 122, so as to form a plurality of delay channels with different delay durations, and the first data selector 121 is further electrically connected to both the microprocessor 180 and the time-to-digital converter 140.

In this embodiment, the number of the buffers 122 can be set according to actual situations, and now the details are described by taking 3 buffers 122 as an example: the plurality of buffers 122 include a first buffer, a second buffer, and a third buffer, the first data selector 121 is a 1-out-of-4 data selector, the state machine 110, the first buffer, the second buffer, and the third buffer are electrically connected in sequence, and the first data selector 121 is electrically connected to the state machine 110, the first buffer, the second buffer, and the third buffer, so as to form 4 delay channels with different delay durations. The 4 delay channels with different delay durations are respectively first delay channels with a first delay duration, which are formed by the state machine 110 and the first input end of the first data selector 121; a second delay path having a second delay duration formed by the state machine 110, the first buffer, and a second input terminal of the first data selector 121; a third delay path having a third delay duration, which is formed by the state machine 110, the first buffer, the second buffer, and a third input terminal of the first data selector 121; a fourth delay path having a fourth delay duration is formed by the state machine 110, the first buffer, the second buffer, the third buffer, and a fourth input terminal of the first data selector 121.

It is understood that the state machine 110 is electrically connected to both the input terminal of the first buffer and the first input terminal of the first data selector 121, the output terminal of the first buffer is electrically connected to both the input terminal of the second buffer and the second input terminal of the first data selector 121, the output terminal of the second buffer is electrically connected to both the input terminal of the third buffer and the third input terminal of the first data selector 121, the output terminal of the third buffer is electrically connected to the fourth input terminal of the first data selector 121, the output terminal of the first data selector 121 is electrically connected to the time-to-digital converter 140, and the control terminal of the first data selector 121 is electrically connected to the microprocessor 180.

The first buffer, the second buffer and the third buffer all play a role of delay, and the delay duration of each buffer 122 may be the same or different. The first delay time of the first delay channel is 0, the second delay time of the second delay channel is the delay time of the first buffer, the third delay time of the third delay channel is the sum of the delay times of the first buffer and the second buffer, and the fourth delay time of the fourth delay channel is the sum of the delay times of the first buffer, the second buffer and the third buffer. If the first measurement signal is transmitted from the first delay channel to the time-to-digital converter 140, the start signal obtained by the time-to-digital converter 140 is obtained by the first measurement signal after 0 delay time duration; if the first measurement signal is transmitted from the second delay channel to the time-to-digital converter 140, the start signal obtained by the time-to-digital converter 140 is obtained by the delay time of the first measurement signal passing through the first buffer; if the first measurement signal is transmitted from the third delay channel to the time-to-digital converter 140, the start signal obtained by the time-to-digital converter 140 is obtained by summing the delay time lengths of the first measurement signal passing through the first buffer and the second buffer; if the first measurement signal is transmitted from the fourth delay channel to the time-to-digital converter 140, the time-to-digital converter 140 obtains the start signal by summing the delay time lengths of the first measurement signal passing through the first buffer, the second buffer and the third buffer.

In this embodiment, the second data selection output module 130 includes a second data selector 131 and an inverter 132, the second data selector 131 is electrically connected to the state machine 110, and the inverter 132 is electrically connected between the state machine 110 and the second data selector 131, so as to form a plurality of delay paths with different delay durations.

It is understood that a first input terminal of the second data selector 131 is electrically connected to the state machine 110, an input terminal of the inverter 132 is electrically connected to the state machine 110, an output terminal of the inverter 132 is electrically connected to a second input terminal of the second data selector 131, a control terminal of the second data selector 131 is electrically connected to the state machine 110, and an output terminal of the second data selector 131 is electrically connected to the time-to-digital converter 140.

The state machine 110 and the first input end of the second data selector 131 form a fifth delay channel with a fifth delay duration; the state machine 110, the inverter 132 and the second input of the second data selector 131 form a sixth delay path having a sixth delay duration. The second data selection output module 130 has 2 delay channels with different delay durations, and the second data selector 131 may be a 1-out-of-2 data selector.

In the present embodiment, the inverter 132 functions as a delay. The fifth delay time of the fifth delay channel is 0, and the sixth delay time of the sixth delay channel is the delay time of the inverter 132. Therefore, when the second measurement signal is transmitted from the fifth delay channel to the time-to-digital converter 140, the time-to-digital converter 140 obtains the end signal after the second measurement signal is delayed for 0; when the second measurement signal is transmitted from the sixth delay channel to the time-to-digital converter 140, the ending signal obtained by the time-to-digital converter 140 is obtained by the delay time of the second measurement signal through the inverter 132.

Referring to fig. 4, which is a schematic structural diagram of an implementation of the time-to-digital converter 140 according to an embodiment of the present invention, the time-to-digital converter 140 includes a plurality of delay units τ and a plurality of D flip-flops FF, the first data selector 121, the second data selector 131, and the plurality of delay units τ are electrically connected in sequence, the plurality of delay units τ are respectively electrically connected to the plurality of D flip-flops FF in a one-to-one correspondence, and the plurality of D flip-flops FF, the microprocessor 180 are electrically connected in sequence. The number of the plurality of delay units τ is the same as the number of the plurality of D flip-flops FF, and the plurality of D flip-flops FF are configured by D flip-flops FF1 to FFn.

The time-to-digital converter 140 forms a delay chain by a plurality of delay units τ and a plurality of D flip-flops FF, and when the delay unit τ electrically connected to the first data selector 121 and the second data selector 131 receives a start signal, the start signal is continuously transmitted through the delay chain formed by the plurality of delay units τ and the plurality of D flip-flops FF until the delay unit τ electrically connected to the first data selector 121 and the second data selector 131 receives an end signal, the start signal is transmitted to a certain delay unit τ and stops being transmitted, and at this time, the D flip-flops FF sample, and the time intervals of the start signal and the end signal can be calculated by analyzing binary digits of 0 or 1 of outputs Q1 to Qn of each D flip-flop FF, so as to calculate a first time interval value and a second time interval value. For example, the outputs Q1 through Qn of each D flip-flop FF are 1111110000, and there are 61, 40, so the first time interval value is 6t or the second time interval value is 6 t. Where t is the delay time duration of the delay unit τ.

As shown in fig. 5, which is a schematic diagram of a frequency waveform to be measured and a reference waveform provided in the embodiment of the present invention, in fig. 5, tau1 is a first time interval value, tau2 is a second time interval value, Nq is the number of pulses of the frequency waveform to be measured, Nr is the number of pulses of the reference waveform, and Tm is a measurement duration of one-time frequency detection. It is understood that the first time interval value may be a time difference between a rising edge or a falling edge of the frequency waveform to be measured and an adjacent rising edge or a falling edge of the reference waveform, and the second time interval value may be a time difference between a rising edge or a falling edge of the frequency waveform to be measured and an adjacent rising edge or a falling edge of the reference waveform. The first time interval shown in fig. 5 is the time difference between the rising edge of the frequency waveform to be measured and the adjacent rising edge of the reference waveform, and the second time interval is also the time difference between the rising edge of the frequency waveform to be measured and the adjacent rising edge of the reference waveform.

In the present embodiment, the first control instruction transmitted from the microprocessor 180 to the first data selector 121 and the second control instruction transmitted to the state machine 110 are determined according to the first time interval value and the second time interval value generated by the time-to-digital converter 140. That is, the microprocessor 180 determines which delay channel of the first data selection output module 120 and the second data selection output module 130 delays the first measurement signal and the second measurement signal according to the first time interval value and the second time interval value generated by the time-to-digital converter 140, so as to obtain a start signal and an end signal.

It is understood that, when the microprocessor 180 sends the first control instruction to the first data selector 121 for the first time and sends the second control instruction to the state machine 110 for the first time, since the time-to-digital converter 140 has not generated the first time interval value and the second time interval value, the microprocessor 180 sends the initial first control instruction to the first data selector 121 and sends the initial second control instruction to the state machine 110 for the first time according to the preset initial channel parameter. The first data selection output module 120 selects a delay channel corresponding to the initial first control instruction according to the initial first control instruction to perform delay processing on the first measurement signal, so as to obtain an initial start signal, and sends the initial start signal to the time-to-digital converter 140. The state machine 110 generates an initial selection instruction according to the initial second control instruction, and sends the initial selection instruction to the second data selection output module 130, so that the second data selection output module 130 selects a corresponding delay channel according to the initial selection instruction to perform delay processing on the second measurement signal, to obtain an initial end signal, and sends the initial end signal to the time-to-digital converter 140. The time-to-digital converter 140 calculates an initial first time interval value and an initial second time interval value according to the initial start signal and the initial end signal. The microprocessor 180 compares the initial first time interval value and the initial second time interval value with a preset interval value, and if the initial first time interval value and the initial second time interval value are close to the preset interval value, the frequency of the frequency waveform to be measured is calculated according to the initial first time interval value and the initial second time interval value; if the difference between the initial first time interval value and the initial second time interval value is larger than the preset interval value, the microprocessor 180 matches the initial first time interval value and the initial second time interval value with a pre-stored mapping relationship table, determines the delay channel of the first data selection output module 120 and the delay channel of the second data selection output module 130 corresponding to the initial first time interval value and the initial second time interval value, and then generates a new start signal and a new end signal, so that the time-to-digital converter 140 generates a new first time interval value and a new second time interval value. The microprocessor 180 repeats the above operations to process the new first time interval value and the new second time interval value until the first time interval value and the second time interval value output by the time-to-digital converter 140 are close to the preset interval value, and then calculates the frequency of the frequency waveform to be measured according to the first time interval value and the second time interval value close to the preset interval value.

The mapping relationship table includes a corresponding relationship between each of the first time interval value and the second time interval value and each of the delay channels of the first data selection output module 120 and each of the delay channels of the second data selection output module 130. The specific principle of determining which delay channel of the first data selection output module 120 and the second data selection output module 130 performs the delay processing on the first measurement signal and the second measurement signal according to the first time interval value and the second time interval value is as follows: if the delay chain length of the time-to-digital converter 140 is n, the maximum delay of the entire time-to-digital converter 140 is nt, t is the delay duration of each delay unit τ, and the selection of n is required to make the TDC control system 100 count that the first time interval value and the second time interval value within a longer time are around 0.5nt (i.e., a preset interval value). After n is determined, the microprocessor 180 may determine whether the received first time interval value and the received second time interval value are around 0.5nt, and if the difference is large, the microprocessor may control the first data selection output module 120 and the second data selection output module 130 to change the delay paths through the first control instruction and the second control instruction, so as to adjust the start signal and the end signal, so that the first time interval value and the second time interval value output by the time-to-digital converter 140 are around 0.5 nt. The microprocessor 180 adjusts the first time interval value and the second time interval value of the next time to be about 0.5nt according to the current first time interval value and the current second time interval value, so that the time-to-digital converter 140 can calculate the start signal and the end signal at the intermediate position to obtain the accurate and stable first time interval value and second time interval value. For example, if the digitizer calculates the start signal and the end signal at the start position, all binary digits of 0 can be easily obtained, which results in that the first time interval value and the second time interval value cannot be accurately obtained; if the digitizer calculates the start signal and the end signal at the end position, all binary digits of 1 are easily obtained, and the first time interval value and the second time interval value cannot be accurately obtained.

It can be seen that, by selecting the delay channels of the first data selection output module 120 and the second data selection output module 130 through the microprocessor 180, the first data selection output module 120 can adjust the time for sending the start signal to the time-to-digital converter, and the second data selection output module 130 can adjust the time for sending the end signal to the time-to-digital converter, so that the situation that the time difference between the start signal and the end signal is large can be avoided, and the time-to-digital converter 140 with a short delay chain length can obtain an accurate and stable first time interval value and a stable second time interval value, thereby obtaining a more accurate and stable frequency of the frequency waveform to be measured; the delay chain of the time-to-digital converter 140 is not too long, so that the time-to-digital converter 140 has improved anti-interference capability and measurement accuracy, and hardware resources of the TDC control system 100 are saved.

Referring to fig. 6, which is a block diagram of another implementable structure of the TDC control system 100 according to the embodiment of the present invention, based on the TDC control system 100 shown in fig. 2, the TDC control system 100 further includes a delay module 150, and the state machine 110 is electrically connected to the first data selection output module 120 and the second data selection output module through the delay module 150.

In this embodiment, the delay module 150 is configured to perform a delay process on the first measurement signal or the second measurement signal, send the delayed first measurement signal to the first data selection output module 120, and send the delayed second measurement signal to the second data selection output module 130.

It can be understood that the delay processing performed by the delay module 150 on the first measurement signal may generate two first measurement signals with different delay durations, that is, the first measurement signal may obtain a first delay measurement signal and a second delay measurement signal after passing through the delay module 150, and the delay duration of the first delay measurement signal is shorter than that of the second delay measurement signal. Similarly, the delay module 150 performs delay processing on the second measurement signal to generate two second measurement signals with different delay durations, that is, the second measurement signal passes through the delay module 150 to obtain a third delay measurement signal and a fourth delay measurement signal, and the delay duration of the third delay measurement signal is shorter than that of the fourth delay measurement signal.

The first delay measurement signal and the third delay measurement signal are sent to the first data selection output module 120, and the second delay measurement signal and the fourth delay measurement signal are sent to the second data selection output module 130. Although the first delay measurement signal is sent to the first data selection output module 120 and the second delay measurement signal is sent to the second data selection output module 130, the first data selection output module 120 selects the delay channel corresponding to the first control instruction according to the first control instruction sent by the microprocessor 180 to perform delay processing on the first delay measurement signal, so as to obtain the start signal. However, at this time, the state machine 110 does not send the selection instruction to the second data selection output module 130, so the second data selection output module 130 does not select the delay channel to perform the delay processing on the second delay measurement signal, that is, the second delay measurement signal is sent to the second data selection output module 130, but is not delayed by the second data selection output module 130. Similarly, while the third delay measurement signal is sent to the first data selection output module 120, the fourth delay measurement signal is sent to the second data selection output module 130, and the second data selection output module 130 selects the delay channel corresponding to the selection instruction according to the selection instruction sent by the state machine 110 to perform delay processing on the fourth delay measurement signal, so as to obtain an end signal. However, at this time, the microprocessor 180 does not send the first control instruction to the first data selection output module 120, so the first data selection output module 120 does not select the delay channel to perform the delay processing on the third delay measurement signal, that is, the third delay measurement signal is sent to the first data selection output module 120 but is not delayed by the first data selection output module 120.

Further, as shown in fig. 7, which is an implementable schematic diagram of the TDC control system 100 shown in fig. 6, the delay module 150 includes a plurality of D flip-flops, the D flip-flops are electrically connected in sequence, a first D flip-flop of the D flip-flops is electrically connected to the first data selection output module 120, a second D flip-flop of the D flip-flops is electrically connected to the second data selection output module 130, and a third D flip-flop of the D flip-flops is electrically connected to the state machine; the first D flip-flop, the second D flip-flop and the third D flip-flop are three D flip-flops in the plurality of D flip-flops.

In this embodiment, the number of the plurality of D flip-flops may be set according to actual situations, and the detailed description is given by taking 3D flip-flops as an example. The plurality of D flip-flops include a D flip-flop a, a D flip-flop b, and a D flip-flop c, and the state machine 110, the D flip-flop a, the D flip-flop b, and the D flip-flop c are electrically connected in sequence, the D flip-flop b is electrically connected to the first data selector 121, and the D flip-flop c is electrically connected to the second data selector 131. The D flip-flop a may be understood as a third D flip-flop, the D flip-flop b may be understood as a first D flip-flop, and the D flip-flop c may be understood as a second D flip-flop.

After the state machine 110 generates the first measurement signal, the first measurement signal generates a first delay measurement signal through the D flip-flop a and the D flip-flop b, and the first measurement signal generates a second delay measurement signal through the D flip-flop a, the D flip-flop b, and the D flip-flop C. Similarly, the second measurement signal may generate a third delay measurement signal through the D flip-flop a and the D flip-flop b, and the second measurement signal may generate a fourth delay measurement signal through the D flip-flop a, the D flip-flop b, and the D flip-flop C. It can be understood that the first measurement signal generates a first delay measurement signal after passing through the sum of the delay durations of the D flip-flop a and the D flip-flop b, and the first measurement signal generates a second delay measurement signal after passing through the sum of the delay durations of the D flip-flop a, the D flip-flop b and the D flip-flop C; the second measurement signal generates a third delay measurement signal after passing through the sum of the delay time of the D trigger a and the D trigger b, and the second measurement signal generates a fourth delay measurement signal after passing through the sum of the delay time of the D trigger a, the delay time of the D trigger b and the delay time of the D trigger C.

In another embodiment, D flip-flop a is electrically connected to first data selector 121, but D flip-flop b is electrically connected to first data selector 121, that is, D flip-flop a is the first D flip-flop. It can be seen that the position of the first D flip-flop on the state machine 110 and the line where the plurality of D flip-flops are sequentially electrically connected is not fixed, the position of the first D flip-flop may be determined according to actual requirements, and the first D flip-flop and the third D flip-flop may also be the same D flip-flop.

In this embodiment, by setting the delay module 150, the frequency waveform to be measured, the reference waveform, the start signal and the end signal can be synchronized, so as to eliminate the competition hazard phenomenon generated by the asynchronism of the frequency waveform to be measured, the reference waveform, the start signal and the end signal, and reduce the external interference.

Further, as shown in fig. 6, the TDC control system 100 further includes a counting module 160, wherein the counting module 160 is electrically connected to the state machine 110, the microprocessor 180, and the delay module 150; the counting module 160 is configured to calculate the number of pulses of the frequency waveform to be measured and the number of pulses of the reference waveform according to the delayed first measurement signal and the delayed second measurement signal output by the delay module 150, and transmit the number of pulses of the frequency waveform to be measured and the number of pulses of the reference waveform to the microprocessor 180; the microprocessor 180 is configured to calculate the frequency of the frequency waveform to be measured according to the number of pulses of the frequency waveform to be measured, the number of pulses of the reference waveform, the first time interval value, and the second time interval value.

It can be understood that, as shown in fig. 7, the counting module 160 includes a first counter 161 and a second counter 162, the first counter 161 is electrically connected to the state machine 110, the microprocessor 180 and the delay module 150, and the second counter 162 is electrically connected to the state machine 110, the microprocessor 180 and the delay module 150; the first counter 161 is configured to start counting pulses of the frequency waveform to be measured according to the delayed first measurement signal, and stop counting pulses of the frequency waveform to be measured according to the delayed second measurement signal, so as to obtain the number of pulses of the frequency waveform to be measured; the second counter 162 is configured to start counting the pulses of the reference waveform according to the delayed first measurement signal, and stop counting the pulses of the reference waveform according to the delayed second measurement signal, so as to obtain the number of the pulses of the reference waveform.

The first counter 161 is electrically connected to the quartz crystal microbalance 300, the first D flip-flop and the microprocessor 180, and the second counter 162 is electrically connected to the high frequency oscillator 400, the second D flip-flop and the microprocessor 180. The first counter 161 receives the frequency waveform to be measured through the quartz crystal microbalance 300, and also receives a first delay measurement signal or a third delay measurement signal through the first D flip-flop; the second counter 162 receives the waveform to be measured through the high frequency oscillator 400, and also receives the second delay measurement signal or the fourth delay measurement signal through the second D flip-flop. The first counter 161 starts counting the pulses of the frequency waveform to be measured after receiving the first delay measurement signal, and stops counting the pulses of the frequency waveform to be measured after receiving the third delay measurement signal, so as to obtain the number of the pulses of the frequency waveform to be measured; the second counter 162 starts counting the pulses of the reference waveform after receiving the second delay measurement signal, and stops counting the pulses of the reference waveform after receiving the fourth delay measurement signal, thereby obtaining the number of the pulses of the reference waveform.

In this embodiment, after receiving the number of pulses of the frequency waveform to be measured, the number of pulses of the reference waveform, the first time interval value, and the second time interval value, the microprocessor 180 calculates the frequency of the frequency waveform to be measured according to the following formula.

fq＝Nq*fr/(Nr+fr(tau1-tau2))；

Wherein Nq represents the number of pulses of the frequency waveform to be measured, and fr represents the frequency of the reference waveform; nr represents the number of pulses of the reference waveform; tau1 represents a first time interval value; tau2 represents the second time interval value.

In this embodiment, the number of pulses of the frequency waveform to be measured, the number of pulses of the reference waveform, the first time interval value, and the second time interval value can be generated synchronously by the delay function of the delay module 150, the plurality of buffers 122, and the inverter 132. Therefore, the phenomenon of competition hazard caused by the fact that the pulse number of the frequency waveform to be detected, the pulse number of the reference waveform, the first time interval value and the second time interval value are not synchronously generated can be eliminated, and spike pulses generated due to interference can be reduced and input into the time-to-digital converter 140, so that the time-to-digital converter 140 can output the first time interval value and the second time interval value accurately and stably.

Further, in the present embodiment, the TDC control system 100 further includes a communication module 170, and the communication module 170 is electrically connected to the microprocessor 180, the state machine 110, the counting module 160, the first data selection output module 120, and the time-to-digital converter 140.

In this embodiment, the communication module 170 may be I²A C (Inter-Integrated Circuit) communication module or an SPI (Serial Peripheral Interface) communication module. The state machine 110, the first data selection output module 120, the second data selection output module 130, the time-to-digital converter 140, the delay module 150, the counting module 160, and the communication module 170 may be integrated on an FPGA (Field Programmable Gate Array) chip. Therefore, the state machine 110, the first data selection output module 120, the second data selection output module 130, the time-to-digital converter 140, the delay module 150, the counting module 160, and the communication module 170 are all digital circuits.

Fig. 8 is a schematic flow chart of the TDC control method according to the present embodiment. It should be noted that the TDC control method according to the embodiment of the present application is not limited by fig. 8 and the following specific sequence, and it should be understood that, in other embodiments, the sequence of some steps in the TDC control method according to the embodiment of the present application may be interchanged according to actual needs, or some steps may be omitted or deleted. It should be noted that the basic principle and the generated technical effects of the TDC control method provided by the present embodiment are the same as those of the foregoing embodiments, and for the sake of brief description, no part of the present embodiment is mentioned, and reference may be made to the corresponding contents in the foregoing embodiments. The TDC control method can be applied to the TDC control system 100 described above, and the specific flow shown in fig. 8 will be described in detail below.

Step S101, when receiving a first working signal sent by a microprocessor, a state machine generates a first measuring signal according to a received frequency waveform to be measured and a reference waveform, and sends the first measuring signal to a first data selection output module; and when a second working signal sent by the microprocessor is received, generating a second measuring signal according to the frequency waveform to be measured and the reference waveform, and sending the second measuring signal to a second data selection output module.

It is understood that step S101 may be performed by the state machine 110 described above.

And step S102, the microprocessor sends a first control instruction to the first data selection output module and sends a second control instruction to the state machine so that the state machine can generate a selection instruction according to the second control instruction, and the state machine sends the selection instruction to the second data selection output module.

In this embodiment, the microprocessor 180 is preset with a preset interval value, where the preset interval value is a delay value determined by a worker according to the maximum delay time of the time-to-digital converter 140 when the worker sets the time-to-digital converter 140; the microprocessor 180 further stores a mapping table for representing a corresponding relationship between each first time interval value and each delay channel of the first data selection output module 120, and a corresponding relationship between each second time interval value and each delay channel of the second data selection output module 130.

When the microprocessor 180 sends the first control instruction to the first data selection output module 120 for the first time and sends the second control instruction to the state machine 110 for the first time, the microprocessor 180 determines the first control instruction and the second control instruction according to the preset initial channel parameter. When the microprocessor 180 does not send the first control instruction to the first data selection output module 120 for the first time and does not send the second control instruction to the state machine 110 for the first time, the microprocessor 180 matches the first time interval value and the second time interval value generated by the time-to-digital converter 140 with the mapping relationship table to determine the first control instruction and the second control instruction; so that the new first time interval value and the second time interval value generated by the time-to-digital converter 140 match the preset interval value.

It is understood that step S102 may be performed by the microprocessor 180 described above.

And step S103, the first data selection output module selects a delay channel corresponding to the first control instruction according to the first control instruction to perform delay processing on the first measurement signal to obtain a start signal, and sends the start signal to the time-to-digital converter.

It is understood that step S103 may be performed by the first data selection output module 120 described above.

And step S104, the second data selection output module selects a delay channel corresponding to the selection instruction according to the selection instruction to perform delay processing on the second measurement signal to obtain an end signal, and the end signal is sent to the time-to-digital converter.

It is understood that step S104 may be performed by the second data selection output module 130 described above.

And step S105, calculating a first time interval value and a second time interval value by the time-to-digital converter according to the starting signal and the ending signal, and sending the first time interval value and the second time interval value to the microprocessor.

It is understood that step S105 may be performed by the time-to-digital converter 140 described above.

And step S106, calculating the frequency of the frequency waveform to be measured by the microprocessor according to the first time interval value and the second time interval value.

It is understood that step S106 may be performed by the microprocessor 180 described above.

In summary, embodiments of the present invention provide a TDC control system, a method, and a film thickness detection apparatus, where the TDC control system includes a state machine, a first data selection output module, a second data selection output module, and a time-to-digital converter, the state machine, the first data selection output module, and the time-to-digital converter are all electrically connected to a microprocessor, the state machine is electrically connected to the second data selection output module, the first data selection output module, and the second data selection output module are both electrically connected to the time-to-digital converter, and the first data selection output module and the second data selection output module each include a plurality of delay channels with different delay durations. Selecting a delay channel corresponding to a first control instruction according to the first control instruction sent by the microprocessor through a first data selection output module to perform delay processing on the first measurement signal to obtain a start signal, and sending the start signal to a time-to-digital converter; selecting a delay channel corresponding to the selection instruction according to the selection instruction sent by the state machine through a second data selection output module to perform delay processing on the second measurement signal to obtain an end signal, and sending the end signal to the time-to-digital converter; and the time-to-digital converter calculates a first time interval value and a second time interval value according to the start signal and the end signal, and sends the first time interval value and the second time interval value to the microprocessor so that the microprocessor can calculate the frequency of the frequency waveform to be measured according to the first time interval value and the second time interval value.

Therefore, the time for sending the start signal to the time-to-digital converter can be adjusted through the first data selection output module, the time for sending the end signal to the time-to-digital converter can be adjusted through the second data selection output module, and the situation that the time difference between the start signal and the end signal is large can be further avoided, so that the time-to-digital converter with the short delay chain length can obtain the accurate and stable first time interval value and second time interval value, the more accurate and stable frequency of the frequency waveform to be detected can be obtained, and the hardware resources of the TDC control system can be saved.

The above description is only for the specific embodiment of the present invention, but the scope of the present invention is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present invention are included in the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the appended claims.