Control method for inhibiting field effect transistor switch oscillation and second-order model thereof

文档序号:1508137 发布日期:2020-02-07 浏览:4次 中文

阅读说明:本技术 抑制场效应晶体管开关振荡的控制方法及其二阶模型 (Control method for inhibiting field effect transistor switch oscillation and second-order model thereof ) 是由 喻松涛 李巍巍 于 2019-11-20 设计创作,主要内容包括:本发明实施例涉及一种抑制场效应晶体管开关振荡的控制方法及其二阶模型,包括阶跃电源、与阶跃电源正极连接的主回路电感、与主回路电感连接的主回路电容和与主回路电容连接的主回路电阻,主回路电阻与阶跃电源的负极连接。该抑制场效应晶体管开关振荡的控制方法通过场效应晶体管开关回路的二阶模型使得场效应晶体管开关回路不需要在场效应晶体管开关回路中的主回路接入额外的阻尼设备,也不引入新的振荡模态;采用开通、关断二阶模型,得到能抑制该场效应晶体管开通或关断过程中出现振荡的驱动电阻,对场效应晶体管的开通或关断过程中出现的振荡得到有效抑制,解决了现有碳化硅MOSFET开关暂态过程出现振荡的技术问题。(The embodiment of the invention relates to a control method for inhibiting field effect transistor switch oscillation and a second-order model thereof. According to the control method for inhibiting the switching oscillation of the field effect transistor, the field effect transistor switching loop does not need to be connected with additional damping equipment in a main loop in the field effect transistor switching loop through a second-order model of the field effect transistor switching loop, and a new oscillation mode is not introduced; the driving resistor capable of inhibiting oscillation in the switching-on or switching-off process of the field effect transistor is obtained by adopting a switching-on and switching-off second-order model, the oscillation in the switching-on or switching-off process of the field effect transistor is effectively inhibited, and the technical problem of oscillation in the transient process of the existing silicon carbide MOSFET switch is solved.)

1. A second-order model of a field effect transistor switch loop is based on a double-pulse test circuit and is characterized by comprising a step power supply, a main loop inductor connected with the positive pole of the step power supply, a main loop capacitor connected with the main loop inductor and a main loop resistor connected with the main loop capacitor, wherein the main loop resistor is connected with the negative pole of the step power supply.

2. The second order model of a fet switch circuit of claim 1, wherein the second order model of the fet switch circuit is in the on state, the second order model comprising a first step power supply, a main loop inductance connected to an anode of the first step power supply, a first capacitor connected to the main loop inductance, and a first main loop resistance connected to the first capacitor, the first main loop resistance connected to a cathode of the first step power supply.

3. Second-order model of a fet switch circuit as claimed in claim 2, characterized in that the second-order model of a fet switch circuit requires a time t during the switching-on processr1,tr1The formula of (1) is:

Figure FDA0002281458510000011

Figure FDA0002281458510000012

wherein, ξ1Is a damping coefficient L 'of a second-order model of the field effect transistor switch loop in a turn-on process'loopIs the main loop inductance, CJIs the first capacitor, Req1Is the first main loop resistance.

4. Second order model of a fet switch loop as claimed in claim 2, wherein the first main loop resistance is Req1,Req1The formula of (1) is:

Figure FDA0002281458510000013

wherein R iseq1Is said first main loop resistance, ωONFor the resonant frequency, L, of the second-order model of the field-effect transistor switching circuit during the switching-on processD、LGAnd LSRespectively drain, gate and source inductances, L 'of the field effect transistor'loopIs the main loop inductance, CJIs the first capacitor, RGIRepresenting the gate resistance, R, of a field effect transistorGIs a drive resistor of a field effect transistor, CGD、CGSAnd CDSAre respectively asGate-drain capacitance, gate-source capacitance and drain-source capacitance, R, of a field effect transistorDS(ON)Is the resistance between the drain of the field effect transistor and its source in the turn-on process.

5. The second order model of the fet switch loop of claim 1, wherein the second order model of the fet switch loop is in the process of being turned off, the second order model comprising a second step power supply, the main loop inductance connected to an anode of the second step power supply, an equivalent capacitance connected to the main loop inductance, and a second main loop resistance connected to the equivalent capacitance, the second main loop resistance connected to a cathode of the second step power supply.

6. Second-order model of a fet switch circuit as claimed in claim 5, characterized by the time t required in the turn-off process in the fet switch circuitr2,tr2The formula of (1) is:

Figure FDA0002281458510000021

Figure FDA0002281458510000022

wherein, ξ2Is a damping coefficient L 'in the turn-off process of a second order model of the field effect transistor switch loop'loopIs the main loop inductance, CDIs the equivalent capacitance, Req2Is the second main loop resistance.

7. The second order model of the FET switching loop of claim 5, wherein the second main loop resistance is Req2,Req2The formula of (1) is:

Figure FDA0002281458510000023

Figure FDA0002281458510000024

Figure FDA0002281458510000025

Figure FDA0002281458510000026

wherein, ω isOFFThe second-order model for the switching loop of a field effect transistor is the resonant frequency, L, during the turn-off processGAnd LSRespectively being the gate inductance and the source inductance, L 'of the field effect transistor'loopIs the main loop inductance, CGD、CGSAnd CDSRespectively a gate-drain capacitance, a gate-source capacitance and a drain-source capacitance, R of the field effect transistorGIRepresents the gate resistance, R, of the field effect transistorGIs a drive resistor of a field effect transistor, CSIs the source side equivalent capacitance, C, of the field effect transistorGIs the gate side equivalent capacitance of the field effect transistor.

8. A control method for suppressing switching oscillations of a field effect transistor, comprising the steps of:

obtaining a second order model of a field effect transistor switching loop as claimed in any one of claims 1 to 7;

obtaining a damping coefficient with the least time required by the field effect transistor in the process of switching on and switching off according to the second-order model;

comparing the obtained damping coefficient with a preset value of the damping coefficient, and taking the minimum value to obtain a new damping coefficient ξ in the switching-on process of the field effect transistor switch loopopt1And damping coefficient ξ for shutdown processopt2

According to the obtained damping coefficient ξopt1And ξopt2Calculating a field in the second order modelThe effect transistor suppresses the oscillating drive resistance during switching on or off.

9. The control method for suppressing switching oscillation of a field effect transistor according to claim 8, wherein the preset value of the damping coefficient is 0.6-0.8.

10. The control method for suppressing fet switch oscillations according to claim 9, characterized in that, said preset value of damping coefficient is 0.8.

Technical Field

The invention relates to the technical field of switching device oscillation, in particular to a control method for inhibiting field effect transistor switching oscillation and a second-order model thereof.

Background

Wide bandgap semiconductor (third generation semiconductor) devices represented by silicon carbide (SiC) and gallium nitride (GaN) have the characteristics of high junction temperature, high blocking voltage, high switching frequency and the like, and have incomparable advantages of silicon-based devices in the aspect of high-frequency and high-power density application. The silicon carbide based MOSFET device is a hot spot for research and application in the field of power electronic technology at present.

Compared with the silicon-based IGBT which is mature to be applied, the silicon carbide MOSFET has the advantages of higher switching speed, shorter switching time, high frequency and small switching loss. But due to the high voltage and current rates of change dv/dt and di/dt during switching, as well as parasitic parameters present in the switching loop, the ringing phenomenon during switching transients in silicon carbide MOSFETs is particularly severe, possibly leading to overvoltage, electromagnetic interference and switching loss problems.

In the prior art, for solving the oscillation phenomenon in the transient process of the silicon carbide MOSFET switch, the more common solutions are:

firstly, the parasitic parameters are reduced by optimizing the PCB design and the device packaging process, but the method is limited by the current manufacturing technology level and is difficult to continuously reduce the parasitic parameters;

secondly, the RC damper is additionally arranged to improve the dynamic performance of the switch loop, additional elements need to be added in the method, the complexity of the circuit is increased, and a new oscillation mode can be introduced into inappropriate damping parameters;

thirdly, the driving resistance of the MOSFET is increased to improve the damping of the MOSFET, but at present, the driving resistance is selected mainly through experience, and an effective model basis is lacked, so that the switching response speed of the MOSFET can be reduced if an overlarge driving resistance is selected.

Therefore, in view of the above situation, how to select the driving resistance of the silicon carbide MOSFET to suppress the MOSFET switching oscillation becomes an important technical problem to be solved urgently by those skilled in the art.

Disclosure of Invention

The invention provides a control method for inhibiting field effect transistor switch oscillation and a second-order model thereof, which are used for solving the technical problem that an electronic device is damaged due to overvoltage and electromagnetic interference possibly caused by oscillation in the transient process of the existing silicon carbide MOSFET switch.

In order to achieve the above purpose, the invention provides the following technical scheme:

a second-order model of a field effect transistor switch loop is based on a double-pulse test circuit and comprises a step power supply, a main loop inductor connected with the positive pole of the step power supply, a main loop capacitor connected with the main loop inductor and a main loop resistor connected with the main loop capacitor, wherein the main loop resistor is connected with the negative pole of the step power supply.

Preferably, a second-order model of the fet switch circuit is in the on process, the second-order model includes a first step power supply, a main circuit inductor connected to the positive terminal of the first step power supply, a first capacitor connected to the main circuit inductor, and a first main circuit resistor connected to the first capacitor, and the first main circuit resistor is connected to the negative terminal of the first step power supply.

Preferably, the second-order model of the field effect transistor switch loop requires time t during the turn-on processr1,tr1The formula of (1) is:

Figure BDA0002281458520000021

Figure BDA0002281458520000022

wherein, ξ1Is a damping coefficient L 'of a second-order model of the field effect transistor switch loop in a turn-on process'loopIs the main loop inductance, CJIs the first capacitor, Req1Is the first main loop resistance.

Preferably, the first main loop resistance is Req1,Req1The formula of (1) is:

Figure BDA0002281458520000023

Figure BDA0002281458520000024

wherein R iseq1Is said first main loop resistance, ωONFor the resonant frequency, L, of the second-order model of the field-effect transistor switching circuit during the switching-on processD、LGAnd LSRespectively drain, gate and source inductances, L 'of the field effect transistor'loopIs the main loop inductance, CJIs the first capacitor, RGIRepresenting the gate resistance, R, of a field effect transistorGIs a drive resistor of a field effect transistor, CGD、CGSAnd CDSRespectively a gate-drain capacitance, a gate-source capacitance and a drain-source capacitance, R of the field effect transistorDS(ON)Is the resistance between the drain of the field effect transistor and its source in the turn-on process.

Preferably, a second-order model of the fet switch circuit is in the turn-off process, the second-order model includes a second step-up power supply, the main circuit inductor connected to the positive terminal of the second step-up power supply, an equivalent capacitor connected to the main circuit inductor, and a second main circuit resistor connected to the equivalent capacitor, and the second main circuit resistor is connected to the negative terminal of the second step-up power supply.

Preferably, the time t required during the turn-off process in a field effect transistor switching loopr2,tr2The formula of (1) is:

Figure BDA0002281458520000031

Figure BDA0002281458520000032

wherein, ξ2Is a damping coefficient L 'in the turn-off process of a second order model of the field effect transistor switch loop'loopIs the main loop inductance, CDIs the equivalent capacitance, Req2Is the second main loop resistance.

Preferably, the second main loop resistance is Req2,Req2The formula of (1) is:

Figure BDA0002281458520000034

Figure BDA0002281458520000035

Figure BDA0002281458520000036

wherein, ω isOFFThe second-order model for the switching loop of a field effect transistor is the resonant frequency, L, during the turn-off processGAnd LSRespectively being the gate inductance and the source inductance, L 'of the field effect transistor'loopIs the main loop inductance, CGD、CGSAnd CDSRespectively a gate-drain capacitance, a gate-source capacitance and a drain-source capacitance, R of the field effect transistorGIRepresents the gate resistance, R, of the field effect transistorGIs a drive resistor of a field effect transistor, CSIs the source side equivalent capacitance, C, of the field effect transistorGIs the gate side equivalent capacitance of the field effect transistor.

The invention also provides a control method for inhibiting the switch oscillation of the field effect transistor, which comprises the following steps:

acquiring a second-order model of the field effect transistor switch loop;

obtaining a damping coefficient with the least time required by the field effect transistor in the process of switching on and switching off according to the second-order model;

comparing the obtained damping coefficient with a preset value of the damping coefficient, and taking the minimum value to obtain a new damping coefficient ξ in the switching-on process of the field effect transistor switch loopopt1And damping of the switching-off processCoefficient ξopt2

According to the obtained damping coefficient ξopt1And ξopt2And calculating the driving resistance for inhibiting oscillation of the field effect transistor in the switching-on or switching-off process in the second-order model.

Preferably, the preset value of the damping coefficient is 0.6-0.8.

Preferably, the preset value of the damping coefficient is 0.8.

According to the technical scheme, the embodiment of the invention has the following advantages:

1. according to the control method for inhibiting the switching oscillation of the field effect transistor, the field effect transistor switching loop does not need to be connected with additional damping equipment in a main loop in the field effect transistor switching loop through a second-order model of the field effect transistor switching loop, and a new oscillation mode is not introduced; compared with the problem that the driving resistance of the field effect transistor is selected according to experience to inhibit the switch oscillation, the second-order model of the field effect transistor switch loop obtains the driving resistance capable of inhibiting the oscillation in the switching-on or switching-off process of the field effect transistor through switching on and switching off the second-order model, and the oscillation in the switching-on or switching-off process of the field effect transistor is effectively inhibited; the technical problem that an electronic device is damaged due to overvoltage and electromagnetic interference caused by oscillation in the transient state process of the existing silicon carbide MOSFET switch is solved;

2. according to the control method for inhibiting the switching oscillation of the field effect transistor, a damping coefficient with the least time required in the switching-on and switching-off processes of the field effect transistor is obtained through a second-order model of a switching loop of the field effect transistor, then the damping coefficient is compared with a preset damping coefficient value to obtain a new damping coefficient, and a driving resistor for inhibiting the oscillation of the field effect transistor in the switching-on or switching-off process is obtained in the second-order model according to the new damping coefficient. Compared with the existing method for selecting the driving resistor by depending on experience to inhibit the switching oscillation of the field effect transistor, the control method for inhibiting the switching oscillation of the field effect transistor is more reasonable and has high efficiency; switch oscillation of the field effect transistor in the switching-on and switching-off processes is effectively inhibited according to the selected driving resistor, and the technical problem that an electronic device is damaged due to overvoltage and electromagnetic interference possibly caused by oscillation in the transient state process of the existing silicon carbide MOSFET switch is solved.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to these drawings without inventive exercise.

Fig. 1 is a circuit diagram of a typical double pulse test of a prior art fet switch loop.

Fig. 2 is a circuit block diagram of a second-order model of a fet switch loop according to an embodiment of the present invention.

Fig. 3 is a circuit diagram of a second-order model of a fet switch loop according to an embodiment of the present invention during a turn-on process.

Fig. 4 is a circuit diagram of a second-order model turn-off process of a fet switch loop according to an embodiment of the present invention.

Fig. 5 is a flowchart illustrating steps of a control method for suppressing fet switching oscillation according to an embodiment of the present invention.

Detailed Description

In order to make the objects, features and advantages of the present invention more obvious and understandable, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the embodiments described below are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention. .

The embodiment of the application provides a control method for inhibiting field effect transistor switch oscillation and a second-order model thereof, which are used for solving the technical problem that an electronic device is damaged due to overvoltage and electromagnetic interference possibly caused by oscillation in the transient process of the existing silicon carbide MOSFET switch.

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