阅读说明：本技术 包括神经网络的半导体装置 (Semiconductor device including neural network ) 是由 黑川义元 原田伸太郎 于 2018-06-11 设计创作，主要内容包括：提供一种能够高效地进行利用神经网络的图像识别的半导体装置。半导体装置包括移位寄存器群、D/A转换器以及积和运算电路。积和运算电路包括模拟存储器,并储存滤波器的参数。移位寄存器群提取图像数据,在使图像数据移位的同时将图像数据的一部分输出到D/A转换器。D/A转换器将被输入的图像数据的一部分转换为模拟数据而输出到积和运算电路。(Provided is a semiconductor device capable of efficiently performing image recognition using a neural network. The semiconductor device includes a shift register group, a D/A converter, and a product-sum operation circuit. The product-sum operation circuit includes an analog memory and stores parameters of the filter. The shift register group extracts image data, and outputs a part of the image data to the D/a converter while shifting the image data. The D/a converter converts a part of the input image data into analog data and outputs the analog data to the product-sum operation circuit.)

1. A semiconductor device, comprising:

a shift register group;

a D/A converter; and

a product-sum operation circuit for performing a product-sum operation,

wherein the shift register group extracts image data,

the shift register group performs an operation of shifting the image data and an operation of outputting a part of the image data to the D/A converter,

the D/a converter converts a part of the image data into analog data and outputs the analog data to the product-sum operation circuit.

2. The semiconductor device according to claim 1,

wherein the product-sum operation circuit includes an analog memory,

the analog memory has stored therein a parameter that,

and the product-sum operation circuit outputs a result of product-sum operation on a part of the image data and the parameter.

3. The semiconductor device as set forth in claim 2,

wherein the analog memory comprises a transistor and a memory cell,

and the transistor includes a metal oxide in a channel formation region.

4. A semiconductor device, comprising:

a D/A converter;

a shift register group; and

a product-sum operation circuit for performing a product-sum operation,

wherein the D/A converter is inputted with image data,

the D/A converter outputs first data in which the image data is converted into analog data to the shift register group,

the shift register group performs an operation of shifting the first data and an operation of outputting a part of the first data as second data to the product-sum operation circuit,

the product-sum operation circuit includes an analog memory,

the analog memory has stored therein a parameter that,

the product-sum operation circuit outputs a result of product-sum operation on the second data and the parameter.

5. The semiconductor device according to claim 4, wherein the first and second semiconductor layers are stacked,

wherein the analog memory comprises a first transistor,

and the first transistor includes a metal oxide in a channel formation region.

6. The semiconductor device according to claim 4, wherein the first and second semiconductor layers are stacked,

wherein the shift register group includes a second transistor,

and the second transistor includes a metal oxide in a channel formation region.

7. A semiconductor device, comprising:

a shift register group;

a D/A converter;

a product-sum operation circuit; and

a pooling circuit is arranged in the device and is used for storing the information of the cells,

wherein the shift register group extracts image data,

the shift register group performs an operation of shifting the image data and an operation of outputting a part of the image data to the D/A converter,

the D/a converter performs an operation of outputting first data in which a part of the image data is converted into analog data to the product-sum operation circuit,

the product-sum operation circuit has parameters stored therein,

the product-sum operation circuit outputs second data obtained by performing product-sum operation on the first data and the parameter to the pooling circuit.

8. The semiconductor device according to claim 7,

wherein the product-sum operation circuit includes an analog memory,

and the parameters are stored in the analog memory.

9. The semiconductor device as set forth in claim 8,

wherein the analog memory comprises a transistor and a memory cell,

and the transistor includes a metal oxide in a channel formation region.

Technical Field

One embodiment of the present invention relates to a semiconductor device including a neural network. In particular, the present invention relates to a semiconductor device capable of performing image recognition using a neural network.

Note that in this specification and the like, a semiconductor device refers to all devices which can operate by utilizing semiconductor characteristics. A display device, a light-emitting device, a memory device, an electro-optical device, a power storage device, a semiconductor circuit, and an electronic apparatus may include a semiconductor device.

Note that one embodiment of the present invention is not limited to the above-described technical field. The technical field of the invention disclosed in this specification and the like relates to an object, a method or a method of manufacture. In addition, one embodiment of the present invention relates to a process (process), a machine (machine), a product (manufacture), or a composition (machine).

Background

The neural network is an information processing system using the neural network as a model. It is expected that a computer having higher performance than a conventional noelman-type computer can be realized by using a neural network, and in recent years, various studies for constituting the neural network have been carried out.

The neural network has a circuit structure modeled by a neural circuit network composed of neurons and synapses. Each neuron is inputted with a plurality of data, each data is multiplied by a "weight coefficient" representing the binding strength, and the results are added together. When the result of the product-sum operation obtained by the above-described method exceeds a threshold value, the neuron outputs a high-level signal, and this phenomenon is called "firing".

Neural networks are used, for example, in the field of image recognition.

In the field of image recognition, convolution is performed to detect the characteristics of image data by multiplying the image data by sliding the parameters of a filter. The convolution is performed a plurality of times, and the edge of the image or the like is detected in the first convolution, and the complicated feature such as the shape or pattern of the image is detected in the subsequent convolution.

In the field of image recognition, image data is divided into small areas and subjected to pooling processing for extracting, for example, a maximum value. The pooling process can be regarded as the same object even if the position of the object changes, and can allow positional deviation of the feature or the like detected in the convolution. Pooling is in many cases performed after convolution, for example, by combining convolution with pooling a plurality of times.

When a neural network is used in the image recognition field, image data and filter parameters in the image recognition field correspond to a plurality of data and weight coefficients input to neurons in the neural network, respectively. In other words, the convolution in the image recognition field is a product-sum operation, and the following processing needs to be performed quickly and efficiently: the image processing apparatus performs an operation by a product-sum operation circuit, extracts image data to the product-sum operation circuit, performs pooling after the product-sum operation, and the like.

Patent document 1 discloses the following example: the handwritten character is recognized by performing mechanical learning using a neural network using a processor such as a CPU (Central Processing Unit) or a GPU (Graphics Processing Unit).

In recent years, a transistor including an Oxide Semiconductor or a metal Oxide in a channel formation region (Oxide Semiconductor transistor, hereinafter referred to as an OS transistor) has attracted attention. The off-state current (off-state current) of the OS transistor is extremely small. Applications using OS transistors have been proposed that take advantage of this characteristic. For example, patent document 2 discloses an example in which an OS transistor is used for learning a neural network.

[ Prior Art document ]

[ patent document ]

[ patent document 1] Japanese patent application laid-open No. 2005-182785

[ patent document 2] Japanese patent application laid-open No. 2016-

Disclosure of Invention

Technical problem to be solved by the invention

In the operation using the neural network, the main operation is product-sum operation, and the image recognition using the neural network requires an enormous amount of calculation by repeating the product-sum operation. Therefore, when a neural network is configured using a data circuit such as a CPU or a GPU, a large number of transistors are required, power consumption is high, and efficiency is low.

When a neural network is used for image recognition, even if the speed of product-sum operation is increased, if the speed of inputting image data as input data to a product-sum operation circuit is slow, the overall processing speed is reduced.

An object of one embodiment of the present invention is to provide a semiconductor device capable of efficiently performing image recognition. An object of one embodiment of the present invention is to provide a semiconductor device capable of performing product-sum operation efficiently. An object of one embodiment of the present invention is to provide a novel semiconductor device.

Note that one embodiment of the present invention does not necessarily achieve all the above-described objects as long as at least one of the objects can be achieved. In addition, the above description of the object does not hinder the existence of other objects. The above-described object other than the above may be apparent from the description of the specification, the claims, the drawings, and the like, and may be extracted from the description of the specification, the claims, the drawings, and the like.

Means for solving the problems

One embodiment of the present invention is a semiconductor device including: a shift register group; a D/A converter; and a product-sum operation circuit. The shift register group extracts image data, and performs an operation of shifting the image data and an operation of outputting a part of the image data to the D/a converter. The D/a converter is characterized by converting a part of image data into analog data and outputting the analog data to a product-sum operation circuit.

In the above aspect, the product-sum operation circuit includes an analog memory in which parameters are stored. The product-sum operation circuit is characterized by outputting a result of product-sum operation on a part of the image data and the parameter.

In the above aspect, the transistor constituting the analog memory includes a metal oxide in the channel formation region.

One embodiment of the present invention is a semiconductor device including: a D/A converter; a shift register group; and a product-sum operation circuit. The image data is input to the D/a converter, and the D/a converter outputs first data, which is converted into analog data, to the shift register group. The shift register group performs an operation of shifting the first data and an operation of outputting a part of the first data as second data to the product-sum operation circuit. The product-sum operation circuit comprises an analog memory, and parameters are stored in the analog memory. The product-sum operation circuit is characterized by outputting a result of product-sum operation on the second data and the parameter.

In the above aspect, the transistor constituting the analog memory includes a metal oxide in the channel formation region.

In the above aspect, the transistors included in the shift register group include a metal oxide in the channel formation region.

One embodiment of the present invention is a semiconductor device including: a shift register group; a D/A converter; a product-sum operation circuit; and a pooling circuit. The shift register group extracts image data, and performs an operation of shifting the image data and an operation of outputting a part of the image data to the D/a converter. The D/a converter outputs first data in which a part of the image data is converted into analog data to the operation of the product-sum operation circuit. The product-sum operation circuit stores parameters, and is characterized in that second data obtained by performing product-sum operation on the first data and the parameters are output to the pooling circuit.

In the above aspect, the product-sum operation circuit is characterized by including an analog memory in which the parameters are stored.

In the above aspect, the transistor constituting the analog memory includes a metal oxide in the channel formation region.

Effects of the invention

According to one embodiment of the present invention, a semiconductor device capable of efficiently performing image recognition can be provided. According to one embodiment of the present invention, a semiconductor device capable of efficiently performing product-sum operation can be provided. According to one embodiment of the present invention, a novel semiconductor device can be provided.

Note that the effects of one embodiment of the present invention are not limited to the above-described effects. The effects listed above do not hinder the existence of other effects. The other effects are those described in the following description and not described in this section. A person skilled in the art can derive the effects not described in this section from the description of the specification, the drawings, and the like, and appropriately derive the effects. One embodiment of the present invention has at least one of the above-described effects and other effects. Therefore, one embodiment of the present invention may not have the above-mentioned effects depending on the case.