阅读说明：本技术 固态摄像装置、固态摄像装置的驱动方法、以及电子设备 (Solid-state imaging device, method for driving solid-state imaging device, and electronic apparatus ) 是由 大高俊德 于 2018-05-07 设计创作，主要内容包括：固态摄像装置10在信号保持部212中,包括分别由一个采样晶体管(1T)与采样电容(1C)形成的第一采样部2122及第二采样部2123,并将两个采样部的耦合节点即保持节点ND23作为双向端口利用,由此,构成为利用四个晶体管实现与差动读取大致同等的信号振幅的具备全局快门功能的固态摄像元件。由此,能够抑制晶体管数的增加,并防止采样部中产生信号振幅损失,而且可维持高像素灵敏度并抑制输入换算噪声。(The solid-state imaging device 10 includes the signal holding unit 212 including the first sampling unit 2122 and the second sampling unit 2123 each formed of one sampling transistor (1T) and one sampling capacitor (1C), and is configured as a solid-state imaging element having a global shutter function in which signal amplitude substantially equal to that of differential reading is realized by four transistors by using the holding node ND23, which is a coupling node of two sampling units, as a bidirectional port. This makes it possible to suppress the increase in the number of transistors, prevent the generation of signal amplitude loss in the sampling unit, and suppress input conversion noise while maintaining high pixel sensitivity.)

1. A solid-state image pickup device characterized by comprising:

a pixel unit in which pixels including a photoelectric conversion reading unit and a signal holding unit are arranged;

a reading unit that reads a pixel signal from the pixel unit; and

a signal line for outputting the holding signal of the signal holding section,

the pixel signals read from the pixels are at least:

a pixel signal including a read signal and a read reset signal read from the pixel,

the photoelectric conversion reading section of the pixel includes at least:

an output node;

a photoelectric conversion element that accumulates charges generated by photoelectric conversion during an accumulation period;

a transfer element that can transfer the electric charge accumulated by the photoelectric conversion element during transfer;

a floating diffusion layer that transfers the electric charges accumulated by the photoelectric conversion element through the transfer element;

a first source follower element that converts the charge of the floating diffusion layer into a voltage signal corresponding to an amount of charge, and outputs the converted signal to the output node; and

a reset element that resets the floating diffusion layer to a specific potential in a reset period, the signal holding portion including:

an input node;

a holding node;

a first sampling unit including a first signal holding capacitor capable of holding a read signal output from an output node of the photoelectric conversion reading unit of the pixel and input to the input node, and a first switching element selectively connecting the first signal holding capacitor to the holding node;

a second sampling unit including a second signal holding capacitor capable of holding a read reset signal that is output from an output node of the photoelectric conversion reading unit of the pixel and is input to the input node, and a second switching element that selectively connects the second signal holding capacitor to the holding node; and

and an output unit including a second source follower element for outputting the signal held by the first signal holding capacitor and the signal held by the second signal holding capacitor from a source terminal to the signal line in accordance with the holding voltage of the holding node.

2. The solid-state image pickup device according to claim 1, wherein:

the input node is connected to the holding node,

the first switching element of the first sampling section and the second switching element of the second sampling section are connected in parallel for the holding node.

3. The solid-state image pickup device according to claim 1, wherein:

the first sampling unit is connected between the input node and the holding node,

the second switching element of the second sampling unit is connected to the holding node,

the first signal holding capacitor of the first sampling unit is connected to the input node, and the first switching element is connected between a connection node of the first signal holding capacitor and the input node and the holding node.

4. The solid-state image pickup device according to claim 1, characterized by comprising:

a power supply switching section capable of selectively connecting a drain side of the second source follower element of the signal holding section to a power supply potential or a reference potential; and

and a node potential switching unit which can selectively set the holding node of the signal holding unit to a specific voltage level or a reference potential.

5. The solid-state image pickup device according to claim 4, wherein:

the reading section, when clearing at least one of the first signal holding capacitor of the first sampling section and the second signal holding capacitor of the second sampling section of the signal holding section,

connecting the drain side of the second source follower element to a reference potential by the power supply switching section,

setting the holding node to a reference potential by the node potential switching section,

and a signal holding unit configured to hold at least one of a first switching element of the first sampling unit and a second switching element of the second sampling unit in an on state.

6. The solid-state image pickup device according to claim 4, wherein:

the signal holding section:

is connected to the holding node at the input node, and

in the case where the first switching element of the first sampling section and the second switching element of the second sampling section are connected in parallel with respect to the holding node,

the reading section:

during the sampling of the pixel signal of the pixel being read,

connecting the drain side of the second source follower element to a reference potential by the power supply switching section,

during a first clearing period of the sampling periods,

setting the holding node to a reference potential by the node potential switching section, and

holding a first switching element of the first sampling unit and a second switching element of the second sampling unit of the signal holding unit in an on state, and clearing the first signal holding capacitor of the first sampling unit and the second signal holding capacitor of the second sampling unit of the signal holding unit,

during a reset signal read period in which a read reset signal as a pixel signal is read from the pixel subsequent to the first clear period,

turning on the second switching element of the second sampling section for a specific period to hold the read reset signal in the second signal holding capacitor,

during a second clear period subsequent to the reset signal read period,

setting the holding node to a reference potential by the node potential switching section, and

holding a first switching element of the first sampling section of the signal holding section in an on state while clearing the first signal holding capacitor of the first sampling section of the signal holding section,

during a signal reading period of reading a reading signal as a pixel signal from the pixel subsequent to the second clear period,

the first switching element of the first sampling unit is turned on for a specific period, and the read signal is held in the first signal holding capacitor.

7. The solid-state image pickup device according to claim 4, wherein:

the signal holding section:

the first sampling unit is connected between the input node and the holding node,

the second switching element of the second sampling unit is connected to the holding node, and

in the case where the first signal holding capacitor of the first sampling unit is connected to the input node, and the first switching element is connected between the holding node and a connection node between the first signal holding capacitor and the input node,

the reading section:

during the sampling of the pixel signal of the pixel being read,

connecting the drain side of the second source follower element to a reference potential by the power supply switching section,

during a first clearing period of the sampling periods,

setting the holding node to a reference potential by the node potential switching section, and

holding a first switching element of the first sampling unit and a second switching element of the second sampling unit of the signal holding unit in an on state, and clearing the first signal holding capacitor of the first sampling unit and the second signal holding capacitor of the second sampling unit of the signal holding unit,

during a reset signal read period in which a read reset signal as a pixel signal is read from the pixel subsequent to the first clear period,

in a state where the first switching element of the first sampling section has been held in an on state,

turning on the second switching element of the second sampling section for a specific period to hold the read reset signal in the second signal holding capacitor,

during a second clear period subsequent to the reset signal read period,

in a state where the second switching element of the second sampling section has been held in a non-conductive state,

setting the holding node to a reference potential by the node potential switching section, and

holding a first switching element of the first sampling section of the signal holding section in an on state while clearing the first signal holding capacitor of the first sampling section of the signal holding section,

during a signal reading period of reading a reading signal as a pixel signal from the pixel subsequent to the second clear period,

the first switching element of the first sampling unit is turned on for a specific period, and the read signal is held in the first signal holding capacitor.

8. The solid-state image pickup device according to claim 6, wherein:

a bus reset section is included, and the source terminal side of the second source follower element of the signal holding section is set to a reference potential level during the sampling period.

9. The solid-state image pickup device according to claim 7, wherein:

a bus reset section is included, and the source terminal side of the second source follower element of the signal holding section is set to a reference potential level during the sampling period.

10. The solid-state image pickup device according to claim 6, wherein:

the reading section:

in the case of performing hold signal read processing of reading the read reset signal held by the second signal holding capacitor of the second sampling section and the read signal held by the first signal holding capacitor of the first sampling section to the signal line,

during the period in which the signal is held read,

connecting the drain side of the second source follower element to a power supply potential by the power supply switching section,

during a first initial value reading period among the hold signal reading periods,

setting the holding node to a specific potential corresponding to an initial value for a specific period by the node potential switching section, reading a conversion signal corresponding to the specific potential to the signal line by the second source follower element of the output section,

during a hold reset signal read period subsequent to the first initial value read period,

turning on the second switching element of the second sampling section for a specific period, and reading a conversion signal corresponding to a hold reset signal of the second signal holding capacitor to the signal line by the second source follower element of the output section,

during a second initial value reading period following the hold reset signal reading period,

setting the holding node to a specific potential corresponding to an initial value for a specific period by the node potential switching section, reading a conversion signal corresponding to the specific potential to the signal line by the second source follower element of the output section,

during a hold read signal read period subsequent to the second initial value read period,

the first switching element of the first sampling unit is turned on for a specific period, and a conversion signal corresponding to a hold signal of the first signal holding capacitor is read out to the signal line by the second source follower element of the output unit.

11. The solid-state image pickup device according to claim 7, wherein:

the reading section:

in the case of performing hold signal read processing of reading the read reset signal held by the second signal holding capacitor of the second sampling section and the read signal held by the first signal holding capacitor of the first sampling section to the signal line,

during the period in which the signal is held read,

connecting the drain side of the second source follower element to a power supply potential by the power supply switching section,

during a first initial value reading period among the hold signal reading periods,

setting the holding node to a specific potential corresponding to an initial value for a specific period by the node potential switching section, reading a conversion signal corresponding to the specific potential to the signal line by the second source follower element of the output section,

during a hold reset signal read period subsequent to the first initial value read period,

turning on the second switching element of the second sampling section for a specific period, and reading a conversion signal corresponding to a hold reset signal of the second signal holding capacitor to the signal line by the second source follower element of the output section,

during a second initial value reading period following the hold reset signal reading period,

setting the holding node to a specific potential corresponding to an initial value for a specific period by the node potential switching section, reading a conversion signal corresponding to the specific potential to the signal line by the second source follower element of the output section,

during a hold read signal read period subsequent to the second initial value read period,

the first switching element of the first sampling unit is turned on for a specific period, and a conversion signal corresponding to a hold signal of the first signal holding capacitor is read out to the signal line by the second source follower element of the output unit.

12. The solid-state image pickup device according to claim 4, wherein:

the node potential switching section includes:

a selection unit that can select a specific voltage level or a reference potential; and

a switching transistor selectively connecting an output of the selection part and the holding node of the signal holding part,

the switching transistor has both a function as a switching element and a function as a current source.

13. The solid-state image pickup device according to claim 5, wherein:

the reading section ends at least the sampling period and performs a process of setting the second source follower element of the output section to an off state before performing the hold signal reading process.

14. The solid-state image pickup device according to claim 13, wherein:

the reading section sets the holding node to a reference potential for a certain period by the node potential switching section in a state where the drain side of the second source follower element has been set to a power supply potential before the holding signal reading process is performed at the end of the sampling period, and sets the second source follower element of the output section to an off state.

15. The solid-state image pickup device according to claim 1, characterized by comprising:

a first substrate, and

a second substrate, which is a substrate,

the first substrate and the second substrate have a stacked structure connected by a connection portion,

on the first substrate, a first dielectric layer is formed,

at least a part of the photoelectric conversion reading section in which at least the pixel is formed,

on the second substrate, a first substrate,

at least a part of the signal holding portion, the signal line, and the reading portion is formed.

16. A method of driving a solid-state image pickup device, the solid-state image pickup device comprising

A pixel unit in which pixels including a photoelectric conversion reading unit and a signal holding unit are arranged;

a reading unit that reads a pixel signal from the pixel unit; and

a signal line for outputting the holding signal of the signal holding section,

the pixel signals read from the pixels are at least:

a pixel signal including a read signal and a read reset signal read from the pixel,

the photoelectric conversion reading section of the pixel includes at least:

an output node;

a photoelectric conversion element that accumulates charges generated by photoelectric conversion during an accumulation period;

a transfer element that can transfer the electric charge accumulated by the photoelectric conversion element during transfer;

a floating diffusion layer that transfers the electric charges accumulated by the photoelectric conversion element through the transfer element;

a first source follower element that converts the charge of the floating diffusion layer into a voltage signal corresponding to an amount of charge, and outputs the converted signal to the output node; and

a reset element for resetting the floating diffusion layer to a specific potential during a reset period, the signal holding portion including

An input node;

a holding node;

a first sampling unit including a first signal holding capacitor capable of holding a read signal output from an output node of the photoelectric conversion reading unit of the pixel and input to the input node, and a first switching element selectively connecting the first signal holding capacitor to the holding node;

a second sampling unit including a second signal holding capacitor capable of holding a read reset signal that is output from an output node of the photoelectric conversion reading unit of the pixel and is input to the input node, and a second switching element that selectively connects the second signal holding capacitor to the holding node; and

an output section including a second source follower element for outputting a signal held by the first signal holding capacitor and a signal held by the second signal holding capacitor from a source terminal to the signal line in accordance with a holding voltage of the holding node,

and the solid-state image pickup device includes:

a power supply switching section capable of selectively connecting a drain side of the second source follower element of the signal holding section to a power supply potential or a reference potential; and

a node potential switching section which can selectively set the holding node of the signal holding section to a specific voltage level or a reference potential,

the method of driving the solid-state image pickup device includes the steps of:

the signal holding section:

is connected to the holding node at the input node, and

in the case where the first switching element of the first sampling section and the second switching element of the second sampling section are connected in parallel with respect to the holding node,

during the sampling of the pixel signal of the pixel being read,

connecting the drain side of the second source follower element to a reference potential by the power supply switching section,

during a first clearing period of the sampling periods,

setting the holding node to a reference potential by the node potential switching section, and

holding a first switching element of the first sampling unit and a second switching element of the second sampling unit of the signal holding unit in an on state, and clearing the first signal holding capacitor of the first sampling unit and the second signal holding capacitor of the second sampling unit of the signal holding unit,

during a reset signal read period in which a read reset signal as a pixel signal is read from the pixel subsequent to the first clear period,

turning on the second switching element of the second sampling section for a specific period to hold the read reset signal in the second signal holding capacitor,

during a second clear period subsequent to the reset signal read period,

setting the holding node to a reference potential by the node potential switching section, and

holding a first switching element of the first sampling section of the signal holding section in an on state while clearing the first signal holding capacitor of the first sampling section of the signal holding section,

during a signal reading period of reading a reading signal as a pixel signal from the pixel subsequent to the second clear period,

the first switching element of the first sampling unit is turned on for a specific period, and the read signal is held in the first signal holding capacitor.

17. A method of driving a solid-state image pickup device, the solid-state image pickup device comprising

A pixel unit in which pixels including a photoelectric conversion reading unit and a signal holding unit are arranged;

a reading unit that reads a pixel signal from the pixel unit; and

a signal line for outputting the holding signal of the signal holding section,

the pixel signals read from the pixels are at least:

a pixel signal including a read signal and a read reset signal read from the pixel,

the photoelectric conversion reading section of the pixel includes at least:

an output node;

a photoelectric conversion element that accumulates charges generated by photoelectric conversion during an accumulation period;

a transfer element that can transfer the electric charge accumulated by the photoelectric conversion element during transfer;

a floating diffusion layer that transfers the electric charges accumulated by the photoelectric conversion element through the transfer element;

a first source follower element that converts the charge of the floating diffusion layer into a voltage signal corresponding to an amount of charge, and outputs the converted signal to the output node; and

a reset element that resets the floating diffusion layer to a specific potential in a reset period, the signal holding portion including:

an input node;

a holding node;

a first sampling unit including a first signal holding capacitor capable of holding a read signal output from an output node of the photoelectric conversion reading unit of the pixel and input to the input node, and a first switching element selectively connecting the first signal holding capacitor to the holding node;

a second sampling unit including a second signal holding capacitor capable of holding a read reset signal that is output from an output node of the photoelectric conversion reading unit of the pixel and is input to the input node, and a second switching element that selectively connects the second signal holding capacitor to the holding node; and

an output section including a second source follower element for outputting a signal held by the first signal holding capacitor and a signal held by the second signal holding capacitor from a source terminal to the signal line in accordance with a holding voltage of the holding node,

and the solid-state image pickup device includes:

a power supply switching section capable of selectively connecting a drain side of the second source follower element of the signal holding section to a power supply potential or a reference potential; and

a node potential switching section which can selectively set the holding node of the signal holding section to a specific voltage level or a reference potential,

the method of driving the solid-state image pickup device includes the steps of:

the signal holding section:

the first sampling unit is connected between the input node and the holding node,

the second switching element of the second sampling unit is connected to the holding node, and

in the case where the first signal holding capacitor of the first sampling unit is connected to the input node, and the first switching element is connected between the holding node and a connection node between the first signal holding capacitor and the input node,

during the sampling of the pixel signal of the pixel being read,

the drain side of the second source follower element is connected to a reference potential by the power supply switching section, and in a first erasing period in the sampling period,

setting the holding node to a reference potential by the node potential switching section, and

holding a first switching element of the first sampling unit and a second switching element of the second sampling unit of the signal holding unit in an on state, and clearing the first signal holding capacitor of the first sampling unit and the second signal holding capacitor of the second sampling unit of the signal holding unit,

during a reset signal read period in which a read reset signal as a pixel signal is read from the pixel subsequent to the first clear period,

in a state where the first switching element of the first sampling section has been held in an on state,

turning on the second switching element of the second sampling section for a specific period to hold the read reset signal in the second signal holding capacitor,

during a second clear period subsequent to the reset signal read period,

in a state where the second switching element of the second sampling section has been held in a non-conductive state,

setting the holding node to a reference potential by the node potential switching section, and

holding a first switching element of the first sampling section of the signal holding section in an on state while clearing the first signal holding capacitor of the first sampling section of the signal holding section,

during a signal reading period of reading a reading signal as a pixel signal from the pixel subsequent to the second clear period,

the first switching element of the first sampling unit is turned on for a specific period, and the read signal is held in the first signal holding capacitor.

18. The method of driving the solid-state imaging device according to claim 16, wherein:

in the case of performing hold signal read processing of reading the read reset signal held by the second signal holding capacitor of the second sampling section and the read signal held by the first signal holding capacitor of the first sampling section to the signal line,

during the period in which the signal is held read,

the drain side of the second source follower element is connected to a power supply potential by the power supply switching section, and in a first initial value reading period in the hold signal reading period,

setting the holding node to a specific potential corresponding to an initial value for a specific period by the node potential switching section, reading a conversion signal corresponding to the specific potential to the signal line by the second source follower element of the output section,

during a hold reset signal read period subsequent to the first initial value read period,

turning on the second switching element of the second sampling section for a specific period, and reading a conversion signal corresponding to a hold reset signal of the second signal holding capacitor to the signal line by the second source follower element of the output section,

during a second initial value reading period following the hold reset signal reading period,

setting the holding node to a specific potential corresponding to an initial value for a specific period by the node potential switching section, reading a conversion signal corresponding to the specific potential to the signal line by the second source follower element of the output section,

during a hold read signal read period subsequent to the second initial value read period,

the first switching element of the first sampling unit is turned on for a specific period, and a conversion signal corresponding to a hold signal of the first signal holding capacitor is read out to the signal line by the second source follower element of the output unit.

19. The method of driving the solid-state imaging device according to claim 17, wherein:

in the case of performing hold signal read processing of reading the read reset signal held by the second signal holding capacitor of the second sampling section and the read signal held by the first signal holding capacitor of the first sampling section to the signal line,

during the period in which the signal is held read,

the drain side of the second source follower element is connected to a power supply potential by the power supply switching section, and in a first initial value reading period in the hold signal reading period,

setting the holding node to a specific potential corresponding to an initial value for a specific period by the node potential switching section, reading a conversion signal corresponding to the specific potential to the signal line by the second source follower element of the output section,

during a hold reset signal read period subsequent to the first initial value read period,

turning on the second switching element of the second sampling section for a specific period, and reading a conversion signal corresponding to a hold reset signal of the second signal holding capacitor to the signal line by the second source follower element of the output section,

during a second initial value reading period following the hold reset signal reading period,

setting the holding node to a specific potential corresponding to an initial value for a specific period by the node potential switching section, reading a conversion signal corresponding to the specific potential to the signal line by the second source follower element of the output section,

during a hold read signal read period subsequent to the second initial value read period,

the first switching element of the first sampling unit is turned on for a specific period, and a conversion signal corresponding to a hold signal of the first signal holding capacitor is read out to the signal line by the second source follower element of the output unit.

20. An electronic device, characterized by comprising:

a solid-state image pickup device; and

an optical system for forming an image of a subject on the solid-state image pickup device,

the solid-state image pickup device includes:

a pixel unit in which pixels including a photoelectric conversion reading unit and a signal holding unit are arranged;

a reading unit that reads a pixel signal from the pixel unit; and

a signal line for outputting the holding signal of the signal holding section,

the pixel signals read from the pixels are at least:

a pixel signal including a read signal and a read reset signal read from the pixel, the photoelectric conversion reading section of the pixel including at least:

an output node;

a photoelectric conversion element that accumulates charges generated by photoelectric conversion during an accumulation period;

a transfer element that can transfer the electric charge accumulated by the photoelectric conversion element during transfer;

a floating diffusion layer that transfers the electric charges accumulated by the photoelectric conversion element through the transfer element;

a first source follower element that converts the charge of the floating diffusion layer into a voltage signal corresponding to an amount of charge, and outputs the converted signal to the output node; and

a reset element that resets the floating diffusion layer to a specific potential in a reset period, the signal holding portion including:

an input node;

a holding node;

a first sampling unit including a first signal holding capacitor capable of holding a read signal output from an output node of the photoelectric conversion reading unit of the pixel and input to the input node, and a first switching element selectively connecting the first signal holding capacitor to the holding node;

a second sampling unit including a second signal holding capacitor capable of holding a read reset signal that is output from an output node of the photoelectric conversion reading unit of the pixel and is input to the input node, and a second switching element that selectively connects the second signal holding capacitor to the holding node; and

and an output unit including a second source follower element for outputting the signal held by the first signal holding capacitor and the signal held by the second signal holding capacitor from a source terminal to the signal line in accordance with the holding voltage of the holding node.

Technical Field

The present invention relates to a solid-state imaging device, a method of driving the solid-state imaging device, and an electronic apparatus.

Background

A Complementary Metal Oxide Semiconductor (CMOS) image sensor has been put to practical use as a solid-state image pickup device (image sensor) using a photoelectric conversion element that detects light and generates electric charges.

CMOS image sensors are widely used as a part of various electronic devices such as digital cameras, video cameras, monitoring cameras, medical endoscopes, Personal Computers (PCs), portable terminal devices (mobile devices) such as mobile phones, and the like.

A CMOS image sensor, which has an FD amplifier including a photodiode (photoelectric conversion element) and a Floating Diffusion layer (FD) in each pixel, has a mainstream reading type of column parallel output, that is, a column (column) output direction is read by selecting a certain row in a pixel array.

The CMOS image sensor performs an operation of reading photocharges generated and accumulated by the photodiode by scanning the pixel or row by row.

In the case of this sequential scanning, that is, in the case of using a rolling shutter (rolling shutter) as an electronic shutter, the exposure start time and the exposure end time of accumulated photocharges cannot be made to coincide in all pixels. Therefore, in the case of successive scans, there are problems as follows: when a moving subject is photographed, the photographed image is distorted.

Therefore, in the photographing of a subject moving at a high speed that does not allow image distortion or in the sensing application that requires simultaneity in photographing an image, a global shutter (globalshutter) that performs start exposure and end exposure at the same timing for all pixels in a pixel array section is employed as an electronic shutter.

A CMOS image sensor that employs a global shutter as an electronic shutter is provided with, for example, a signal holding section that holds a signal read from a photoelectric conversion reading section in a signal holding capacitor within a pixel.

In a CMOS image sensor using a global shutter, charges are accumulated from photodiodes as voltage signals in signal holding capacitors of a signal holding section at a time, and then read out sequentially, thereby ensuring simultaneity of the entire image (see, for example, non-patent document 1).

The stacked CMOS image sensor described in non-patent document 1 has a stacked structure in which a first substrate (Pixel die) and a second substrate (ASIC die) are connected to each other by micro bumps (connection portions). A photoelectric conversion reading portion for each pixel is formed over the first substrate, and a signal holding portion, a signal line, a vertical scanning circuit, a horizontal scanning circuit, a column reading circuit, and the like for each pixel are formed over the second substrate.

Disclosure of Invention

Technical problem to be solved by the invention

However, a voltage-mode global shutter in which Correlated Double Sampling (CDS) is performed at a portion adjacent to a photoelectric conversion portion can realize high shutter efficiency (SRR) and Parasitic Sensitivity (PLS) more easily than a conventional charge mode type.

Further, by using a chip stacking technique and providing the sampling section on a die (die) different from the photoelectric conversion section, complete light shielding can be achieved.

As a result, even when very strong light such as sunlight is incident, PLS can be reduced to a level of-160 dB which hardly affects an image to be sampled (see non-patent document 2).

Therefore, it is a promising pixel technology in a machine vision camera that needs to acquire a stable image under extreme illumination fluctuations, such as ITS.

The stacked global shutter CMOS image sensor has a sampling circuit mounted directly below a pixel including a photoelectric conversion portion.

Sampling the voltage requires a large capacitor and a switching transistor. In addition, a transistor to output the sampled voltage is also required.

The noise voltage generated at the time of sampling is inversely proportional to the square root of the sampling capacitance, and therefore, it is indispensable to install the sampling capacitance as large as possible in terms of noise reduction.

The devices for realizing the sampling capacitor include various types of MOS capacitors, MIM capacitors, PIP capacitors, MOM capacitors, and trench capacitors, but in general, it is preferable that the sampling portion and the output portion of the sampling circuit be configured with as few transistors as possible.

On the other hand, as shown in non-patent document 3, the CDS method can be divided into two methods.

One is a method of performing differential processing between a pixel reset voltage and an optical signal voltage by using an AC coupling technique and using a sampling circuit, and storing the differential processing.

In the AC coupling technique used in non-patent document 3, the same configuration of the output section as that of the conventional 4T-APS pixel can be adopted, and therefore, the required number of transistors can be suppressed.

However, as a result of charge sharing, there may be a case where the transfer function gain of the sampling circuit is lower than 0.5, or a case where the transfer function gain becomes about 0.8 due to parasitic capacitance in another structure. As a result, there is a disadvantage that input conversion noise becomes very large.

Another is a method using a double sampling technique.

In the double sampling, a differential process is performed by a column circuit.

As shown in non-patent document 2, since each sampling capacitor requires an output unit, the number of transistors tends to increase.

However, since charge sharing does not occur at all, there is an advantage that no signal amplitude loss occurs in the sampling circuit, and input conversion noise can be suppressed while maintaining high pixel sensitivity as compared with the AC coupling method.

The invention provides a solid-state imaging device, a driving method of the solid-state imaging device, and an electronic apparatus, which can suppress the generation of signal amplitude loss in a sampling unit while suppressing the increase of the number of transistors, and can suppress input conversion noise while maintaining high pixel sensitivity.

Means for solving the problems

A solid-state image pickup device according to a first aspect of the present invention includes: a pixel unit in which pixels including a photoelectric conversion reading unit and a signal holding unit are arranged; a reading unit that reads a pixel signal from the pixel unit; and a signal line that outputs a hold signal of the signal holding section, wherein the pixel signal read from the pixel is a pixel signal including at least a read signal and a read reset signal read from the pixel, and the photoelectric conversion reading section of the pixel includes at least: an output node; a photoelectric conversion element that accumulates charges generated by photoelectric conversion during an accumulation period; a transfer element that can transfer the electric charge accumulated by the photoelectric conversion element during transfer; a floating diffusion layer that transfers the electric charges accumulated by the photoelectric conversion element through the transfer element; a first source follower element that converts the charge of the floating diffusion layer into a voltage signal corresponding to an amount of charge, and outputs the converted signal to the output node; and a reset element that resets the floating diffusion layer to a specific potential in a reset period, the signal holding portion including: an input node; a holding node; a first sampling unit including a first signal holding capacitor capable of holding a read signal output from an output node of the photoelectric conversion reading unit of the pixel and input to the input node, and a first switching element selectively connecting the first signal holding capacitor to the holding node; a second sampling unit including a second signal holding capacitor capable of holding a read reset signal that is output from an output node of the photoelectric conversion reading unit of the pixel and is input to the input node, and a second switching element that selectively connects the second signal holding capacitor to the holding node; and an output unit including a second source follower element for outputting the signal held by the first signal holding capacitor and the signal held by the second signal holding capacitor from a source terminal to the signal line in accordance with the holding voltage of the holding node.

A second aspect of the present invention is a driving method of a solid-state image pickup device including: a pixel unit in which pixels including a photoelectric conversion reading unit and a signal holding unit are arranged; a reading unit that reads a pixel signal from the pixel unit; and a signal line that outputs a hold signal of the signal holding section, wherein the pixel signal read from the pixel is a pixel signal including at least a read signal and a read reset signal read from the pixel, and the photoelectric conversion reading section of the pixel includes at least: an output node; a photoelectric conversion element that accumulates charges generated by photoelectric conversion during an accumulation period; a transfer element that can transfer the electric charge accumulated by the photoelectric conversion element during transfer; a floating diffusion layer that transfers the electric charges accumulated by the photoelectric conversion element through the transfer element; a first source follower element that converts the charge of the floating diffusion layer into a voltage signal corresponding to an amount of charge, and outputs the converted signal to the output node; and a reset element that resets the floating diffusion layer to a specific potential in a reset period, the signal holding portion including: an input node; a holding node; a first sampling unit including a first signal holding capacitor capable of holding a read signal output from an output node of the photoelectric conversion reading unit of the pixel and input to the input node, and a first switching element selectively connecting the first signal holding capacitor to the holding node; a second sampling unit including a second signal holding capacitor capable of holding a read reset signal that is output from an output node of the photoelectric conversion reading unit of the pixel and is input to the input node, and a second switching element that selectively connects the second signal holding capacitor to the holding node; and an output section including a second source follower element that outputs a signal held by the first signal holding capacitor and a signal held by the second signal holding capacitor from a source terminal to the signal line in accordance with a holding voltage of the holding node, the solid-state image pickup device including: a power supply switching section capable of selectively connecting a drain side of the second source follower element of the signal holding section to a power supply potential or a reference potential; and a node potential switching section that can selectively set the holding node of the signal holding section to a specific voltage level or a reference potential.

In the second aspect of the present invention, the signal holding section is configured such that, when the input node is connected to the holding node, and the first switching element of the first sampling section and the second switching element of the second sampling section are connected in parallel to the holding node, the drain side of the second source follower element is connected to a reference potential by the power supply switching section during a sampling period for reading a pixel signal of the pixel, and the holding node is set to the reference potential by the node potential switching section and the first switching element of the first sampling section and the second switching element of the second sampling section of the signal holding section are held in an on state while the first switching element of the first sampling section and the second switching element of the second sampling section of the signal holding section are held in a first clear period in the sampling period, and the first signal holding capacitor of the first sampling section and the second signal holding capacitor of the second sampling section of the signal holding section are cleared, in a reset signal read period in which a read reset signal as a pixel signal is read from the pixel subsequent to the first clear period, the second switching element of the second sampling section is turned on for a specific period to hold the read reset signal in the second signal holding capacitor, in a second clear period subsequent to the reset signal read period, the holding node is set to a reference potential by the node potential switching section, and the first switching element of the first sampling section of the signal holding section is held in an on state to clear the first signal holding capacitor of the first sampling section of the signal holding section, and in a signal read period in which a read signal as a pixel signal is read from the pixel subsequent to the second clear period, the first switching element of the first sampling section is turned on for a specific period, while the read signal is held on the first signal holding capacitor.

In the second aspect of the present invention, the signal holding unit is configured such that the first sampling unit is connected between the input node and the holding node, the second switching element of the second sampling unit is connected to the holding node, the first signal holding capacitor of the first sampling unit is connected to the input node, and the first switching element is connected between a connection node of the first signal holding capacitor and the input node and the holding node, wherein the drain side of the second source follower element is connected to a reference potential by the power supply switching unit during a sampling period in which a pixel signal of the pixel is read, and the holding node is set to the reference potential by the node potential switching unit and the first switching element of the first sampling unit and the second switching element of the second sampling unit of the signal holding unit are held during a first clear period in the sampling period The first signal holding capacitor of the first sampling unit and the second signal holding capacitor of the second sampling unit of the signal holding unit are cleared to be in a conductive state, the second switching element of the second sampling unit is made conductive for a specific period in a reset signal reading period in which a read reset signal as a pixel signal is read from the pixel subsequent to the first clearing period in a state in which the first switching element of the first sampling unit is held in a conductive state, the read reset signal is held in the second signal holding capacitor, and the holding node is set to a reference potential by the node potential switching unit in a state in which the second switching element of the second sampling unit is held in a non-conductive state in a second clearing period subsequent to the reset signal reading period, and a first switching element of the first sampling unit of the signal holding unit is held in an on state, the first signal holding capacitor of the first sampling unit of the signal holding unit is cleared, and the first switching element of the first sampling unit is turned on for a specific period in a signal reading period in which a read signal as a pixel signal is read from the pixel subsequent to the second clearing period, and the read signal is held in the first signal holding capacitor.

An electronic device according to a third aspect of the present invention includes: a solid-state image pickup device; and an optical system that forms an image of a subject on the solid-state image pickup device, the solid-state image pickup device including: a pixel unit in which pixels including a photoelectric conversion reading unit and a signal holding unit are arranged; a reading unit that reads a pixel signal from the pixel unit; and a signal line that outputs a hold signal of the signal holding section, wherein the pixel signal read from the pixel is a pixel signal including at least a read signal and a read reset signal read from the pixel, and the photoelectric conversion reading section of the pixel includes at least: an output node; a photoelectric conversion element that accumulates charges generated by photoelectric conversion during an accumulation period; a transfer element that can transfer the electric charge accumulated by the photoelectric conversion element during transfer; a floating diffusion layer that transfers the electric charges accumulated by the photoelectric conversion element through the transfer element; a first source follower element that converts the charge of the floating diffusion layer into a voltage signal corresponding to an amount of charge, and outputs the converted signal to the output node; and a reset element that resets the floating diffusion layer to a specific potential in a reset period, the signal holding portion including: an input node; a holding node; a first sampling unit including a first signal holding capacitor capable of holding a read signal output from an output node of the photoelectric conversion reading unit of the pixel and input to the input node, and a first switching element selectively connecting the first signal holding capacitor to the holding node; a second sampling unit including a second signal holding capacitor capable of holding a read reset signal that is output from an output node of the photoelectric conversion reading unit of the pixel and is input to the input node, and a second switching element that selectively connects the second signal holding capacitor to the holding node; and an output unit including a second source follower element for outputting the signal held by the first signal holding capacitor and the signal held by the second signal holding capacitor from a source terminal to the signal line in accordance with the holding voltage of the holding node.

Effects of the invention

According to the present invention, it is possible to suppress the increase in the number of transistors, prevent the generation of signal amplitude loss in the sampling unit, and suppress input conversion noise while maintaining high pixel sensitivity.

Drawings

Fig. 1 is a block diagram showing a configuration example of a solid-state image pickup device according to a first embodiment of the present invention.

Fig. 2 is a circuit diagram showing a configuration example of a pixel of the solid-state imaging device according to the first embodiment of the present invention.

Fig. 3 is a diagram for explaining a pixel array in a pixel portion of a solid-state image pickup device according to a first embodiment of the present invention.

Fig. 4 is a diagram illustrating a configuration example of a reading system for column output of a pixel portion of a solid-state imaging device according to an embodiment of the present invention.

Fig. 5 is a diagram for explaining a first layered structure of the solid-state image pickup device 10 according to the first embodiment.

Fig. 6 is a diagram for explaining a second stacked structure of the solid-state image pickup device 10 according to the first embodiment.

Fig. 7(a) to (I) are timing charts mainly explaining the operation of the clear period and the sampling period of the pixel portion in the specific shutter mode of the solid-state imaging device according to the first embodiment.

Fig. 8(a) to (F) are timing charts mainly explaining the reading operation in the hold signal reading period of the pixel section in the specific shutter mode of the solid-state imaging device according to the first embodiment.

Fig. 9 is a circuit diagram showing a configuration example of a pixel of a solid-state imaging device according to a second embodiment of the present invention.

Fig. 10 is a circuit diagram showing a configuration example of a pixel of a solid-state imaging device according to a third embodiment of the present invention.

Fig. 11(a) to (I) are timing charts mainly explaining the operation of the clear period and the sampling period of the pixel portion in the specific shutter mode of the solid-state imaging device according to the third embodiment.

Fig. 12 is a diagram showing an example of a configuration of an electronic apparatus to which a solid-state imaging device according to an embodiment of the present invention is applied.

Description of the main elements

10. 10A, 10B: solid-state image pickup device

20. 20A, 20B: pixel section

PD 21: photodiode

TG 1-Tr: transmission transistor

RST 1-Tr: reset transistor

SF 1-Tr: source follower transistor

FD 21: floating diffusion layer

21: pixel

211: photoelectric conversion reading unit

212. 212A, 212B: signal holding part

ND 21: output node

ND 22: input node

2121: input unit

2122: a first sampling part

2123: a second sampling part

2124: output unit

ND 23: holding node

CS 21: first signal holding capacitor

CR 21: second signal holding capacitor

SHS 1-Tr: first sampling transistor

SHR 1-Tr: second sampling transistor and vertical scanning circuit

40: read circuit (column read circuit)

50: horizontal scanning circuit

60: sequential control circuit

70: reading unit

300: electronic device

310: CMOS image sensor

320: optical system

330: signal processing circuit (PRC)

Detailed Description

Hereinafter, embodiments of the present invention will be described in connection with the drawings.

(first embodiment)

Fig. 1 is a block diagram showing a configuration example of a solid-state image pickup device according to a first embodiment of the present invention.

In the present embodiment, the solid-state image pickup device 10 is constituted by, for example, a CMOS image sensor.

As shown in fig. 1, the solid-state image pickup device 10 includes, as main structural elements, a pixel portion 20 as an image pickup portion, a vertical scanning circuit (row scanning circuit) 30, a reading circuit (column reading circuit) 40, a horizontal scanning circuit (column scanning circuit) 50, and a timing control circuit 60.

Among these components, the vertical scanning circuit 30, the reading circuit 40, the horizontal scanning circuit 50, and the timing control circuit 60 constitute a reading unit 70 for pixel signals.

In the first embodiment, the solid-state imaging device 10 includes a photoelectric conversion reading section and a signal holding section as pixels in the pixel section 20, and is configured as a stacked CMOS image sensor having an operation function of a global shutter, for example.

In the solid-state imaging device 10 according to the first embodiment, as described in detail below, in the stacked CMOS image sensor including the first substrate and the second substrate, the first sampling portion and the second sampling portion each formed of one sampling transistor (1T) and one sampling capacitor (1C) are mounted in the signal holding portion formed in the second substrate, and the holding node, which is the coupling node of the two sampling portions, is used as a bidirectional port, whereby a solid-state imaging element having a global shutter function is configured to realize a signal amplitude substantially equal to that of differential reading using four transistors.

Hereinafter, the outline of the structure and function of each part of the solid-state imaging device 10, in particular, the structure and function of the pixel unit 20, the reading process related thereto, the stacked structure of the pixel unit 20 and the reading unit 70, and the like will be described in detail.

(Structure of Pixel and Pixel section 20)

Fig. 2 is a circuit diagram showing a configuration example of a pixel of the solid-state imaging device 10 according to the first embodiment of the present invention.

The pixel 21 disposed in the pixel portion 20 includes a photoelectric conversion reading portion 211 and a signal holding portion 212.

In the pixel unit 20 according to the first embodiment, a power supply switching unit 22, a node potential switching unit 23, and a bus line resetting unit 24 are arranged corresponding to the pixel 21 or corresponding to the plurality of pixels 21.

The photoelectric conversion reading section 211 of the pixel 21 includes a photodiode (photoelectric conversion element) and an in-pixel amplifier.

Specifically, the photoelectric conversion reading section 211 includes, for example, a photodiode PD21 as a photoelectric conversion element.

The photodiode PD21 includes a transfer transistor TG1-Tr as a transfer element, a reset transistor RST1-Tr as a reset element, a source follower transistor SF1-Tr as a first source follower element, a selection transistor SEL1-Tr as a selection element, and an output node ND 21.

In this way, the photoelectric conversion reading section 211 of the pixel 21 of the first embodiment has a 4-transistor (4Tr) including the transfer transistor TG1-Tr, the reset transistor RST1-Tr, the first source follower transistor SF1-Tr, and the selection transistor SEL 1-Tr.

In the photoelectric conversion reading section 211 of the first embodiment, the output node ND21 is connected to the input section of the signal holding section 212 of the pixel 21.

In the global shutter mode, the photoelectric conversion reading unit 211 outputs a read signal (signal Voltage) (VSIG), which is a pixel signal, and a read reset signal (signal Voltage) (VRST) to the signal holding unit 212.

In the first embodiment, the vertical signal line LSGN11 is driven by the constant current source Ibias in the global shutter mode.

The photodiode PD21 generates and accumulates signal charges (electrons here) of an amount corresponding to the amount of incident light.

Hereinafter, a case where the signal charges are electrons and the transistors are n-type transistors will be described, but the signal charges may be holes (holes) and the transistors may be p-type transistors.

This embodiment is also effective in the case where each transistor is shared between a plurality of photodiodes and transfer transistors, or in the case where a three-transistor (3Tr) pixel including no selection transistor is used.

The transfer transistor TG1-Tr of the photoelectric conversion reading section 211 is connected between the photodiode PD21 and the floating diffusion layer FD21, and is controlled by a control signal TG applied to the gate through a control line.

The transfer transistor TG1-Tr is selected to be in an on state during a transfer period in which the control signal TG is at a high (H) level, and transfers charges (electrons) photoelectrically converted and accumulated by the photodiode PD21 to the floating diffusion FD 21.

The reset transistor RST1-Tr is connected between a power supply line VDD of a power supply voltage VDD and the floating diffusion layer FD21, and is controlled by a control signal RST applied to the gate through a control line.

The reset transistor RST1-Tr is selected to be in an on state in a reset period in which the control signal RST is at the H level, and resets the floating diffusion FD21 to the potential of the power supply line VDD of the power supply voltage VDD.

The source follower transistor SF1-Tr as a first source follower element and the selection transistor SEL1-Tr are connected in series between the power supply line Vdd and the output node ND 21.

The signal line LSGN12 between the output node ND21 and the input section of the signal holding section 212 is driven by, for example, a capacitor or a constant current source disposed in the signal holding section 212.

The gate of the source follower transistor SF1-Tr is connected to the floating diffusion layer FD21, and the select transistor SEL1-Tr is controlled by a control signal SEL applied to the gate through a control line.

The selection transistors SEL1-Tr are selected to be in an on state during a selection period in which the control signal SEL is at the H level. Thus, the source follower transistor SF1-Tr outputs a read signal (VSIG) and a read reset signal (VRST) output from a column, which is obtained by converting the charges of the floating diffusion layer FD21 into a voltage signal corresponding to the amount of charges (potential), to the signal line LSGN12 via the output node ND 21.

The signal holding section 212 of the pixel 21 basically has a configuration including an input section 2121 including an input node ND22, a first sampling section 2122, a second sampling section 2123, an output section 2124, and a holding node ND 23.

The input node ND22 of the signal holding section 212 according to the first embodiment is directly connected to the holding node ND23, and the first switching element of the first sampling section 2122 and the second switching element of the second sampling section 2123 are connected in parallel to the holding node ND 23.

The input unit 2121 has an input node ND22 connected to the output node ND21 of the photoelectric conversion reading unit 211 via a signal line LSGN12, and inputs a read signal (VSIG) and a read reset signal (VRST) output from the output node ND21 to the first sampling unit 2122 and the second sampling unit 2123 via the holding node ND 23.

The first sampling unit 2122 includes: a first signal holding capacitor CS21 capable of holding a read signal VSIG which is output from the output node ND21 of the photoelectric conversion reading section 211 and input to the input node ND 22; and a first sampling transistor SHS1-Tr as a first switching element selectively connecting the first signal holding capacitor CS21 to the holding node ND 23.

The first signal holding capacitor CS21 is connected between the node ND24 and the reference potential VSS.

The first sampling transistor SHS1-Tr is connected between the holding node ND23 and the node ND 24.

The first sampling transistor SHS1-Tr is turned on, for example, during a period in which the control signal SHS is at a high level.

The first sampling transistor SHS1-Tr selectively connects the first signal holding capacitor CS21 of the first sample-and-hold section 2122 to the holding node ND23 during a global shutter period or a clear (clear) period of the signal holding capacitor.

The second sampling unit 2123 includes: a second signal holding capacitor CR21 that can hold the read reset signal VRST that is output from the output node ND21 of the photoelectric conversion reading section 211 and input to the input node ND 22; and a second sampling transistor SHR1-Tr as a second switching element selectively connecting the second signal holding capacitor CR21 to the holding node ND 23.

The second signal holding capacitor CR21 is connected between the node ND25 and the reference potential VSS.

The second sampling transistor SHR1-Tr is connected between the holding node ND23 and the node ND 25.

The second sampling transistor SHR1-Tr is turned on, for example, during a period in which the control signal SHR is at a high level.

The second sampling transistor SHR1-Tr selectively connects the second signal holding capacitor CR21 of the second sample hold section 2123 to the holding node ND23 during the global shutter period or the clear period of the signal holding capacitor.

Further, the first signal holding capacitor CS21 and the second signal holding capacitor CR21, which are sampling capacitances cleared to 0V, are connected to the holding node ND23, whereby reading from the photoelectric conversion reading section 211 to the signal holding section 212 is performed.

In this way, the signal holding unit 212 according to the first embodiment can perform charge transfer bidirectionally to the holding node ND23 by using a configuration of the 1 transistor (1T) and the 1 capacitor (1C) as in a DRAM for the first sampling unit 2122 and the second sampling unit 2123.

That is, the signal holding section 212 of the first embodiment realizes writing (sampling operation) and reading (charge sharing operation) for one point, thereby reducing the number of transistors required.

Further, the first and second sampling transistors SHS1-Tr and SHR1-Tr are formed of MOS transistors such as n-channel MOS (NMOS) transistors.

The first signal holding capacitor CS21 and the second signal holding capacitor CR21 are formed of any one of or a combination of a MOS capacitor, an MIM capacitor, a PIP capacitor, and an MOM capacitor.

The output section 2124 includes a source follower transistor SF2-Tr as a second source follower element, and the source follower transistor SF2-Tr outputs the read signal VSIG held by the first signal holding capacitor CS21 of the first sampling section 2122 and the read reset signal VRST held by the second signal holding capacitor CR21 of the second sampling section 2123 from the source terminal gn to the vertical signal line ls 11 in accordance with the holding voltage of the holding node ND 23.

The source follower transistor SF2-Tr as the second source follower element has a source terminal connected to the vertical signal line LSGN11, a drain terminal side connected to the power supply switching section 22 via the power supply line Vddpix, and a gate terminal connected to the holding node ND 23.

The source follower transistor SF2-Tr has its drain connected to the power supply line Vddpix of the power supply potential VDD via the power supply switching unit 22 during the read period PHRD of the read signal VSIG held by the first signal holding capacitor CS21 and the second signal holding capacitor CR21 and the read reset signal VRST.

In this case, the source follower transistor SF2-Tr outputs the read signal (VSIG) and the read reset signal (VRST) converted to the column output of the voltage signal corresponding to the holding voltage of the holding node ND23 to the vertical signal line LSGN 11.

The source follower transistor SF2-Tr has a drain connected to a reference potential VSS (for example, 0V at the ground level) via the power supply switching section 22 in the erasing period PCL of the first signal holding capacitor CS21 and the second signal holding capacitor CR21 of the erasing signal holding section 212 and the sampling period PSML in which the read signal and the read reset signal read from the photoelectric conversion section 211 are written (held) in the first signal holding capacitor CS21 and the second signal holding capacitor CR 21.

The power supply switching section 22 has an output of the selection section 221 connected to a power supply line Vddpix connected to the drain of the source follower transistor SF2-Tr of the output section 2124 of the signal holding section 212, and the selection section 221 connects the power supply line Vddpix to a power supply line VDD of a power supply potential VDD (for example, 3V) or a reference potential VSS in accordance with a control signal CTL 1.

For example, in the erasing period PCL or the sampling period PSML, the control signal CTL1 is set to the L level, and the selection unit 221 of the power supply switching unit 22 connects the power supply line Vddpix to the reference potential VSS.

On the other hand, in the hold signal read period PHRD, the control signal CTL1 is set to the H level, and the selection unit 221 of the power supply switching unit 22 connects the power supply line Vddpix to the power supply line VDD of the power supply potential VDD.

The source terminal side of the source follower transistor SF2-Tr is connected to the vertical signal line LSGN11 as described above, but the bus reset section 24 is connected to the vertical signal line LSGN 11.

The bus reset unit 24 includes a switching element 241 connected between the vertical signal line LSGN11 and the reference potential VSS.

The switching element 241 is turned ON (ON) and OFF (OFF) in response to a bus reset signal BRST.

The source terminal side of the source follower transistor SF2-Tr functions as an impedance by being driven by a constant current in the hold signal read period PHRD, but in the sampling period PSML, the switching element 241 is turned on by the bus reset signal BRST for the switching element 241 of the bus reset unit 24 and fixed to the reference potential VSS (for example, 0V).

As a result, the source follower transistors SF2-Tr become strong inversion operation regions, and are equivalent to MOS capacitors. As a result, band limitation is imposed on the former transistor of the MOS capacitor, and noise can be reduced.

In the signal holding unit 212, the node potential switching unit 23 functioning as a clamp circuit is connected to the holding node ND 23.

The node potential switching section 23 is provided to selectively set the holding node ND23 of the signal holding section 212 to a specific voltage level VCLP or a reference potential VSS (e.g., 0V), enabling CDS reading by the output section 2124 of the signal holding section 212.

The configuration of the node potential switching unit 23 functioning as a clamp circuit includes: a selection unit 231 that selects a specific voltage VCLP (for example, 2.6V) level or a reference potential VSS as a clamp voltage in accordance with a control signal CTL 2; and a switching transistor CLP1-Tr selectively connecting the output line side of the selection section 231 with the holding node ND 23.

The node potential switching section 23 has the selection section 231 connected to the power supply line Vclppix connected to the source terminal of the switching transistor CLP1-Tr, and the selection section 231 connects the power supply line Vclppix to the power supply line VCLP of the specific voltage VCLP (for example, 2.6V) or the reference potential VSS in response to the control signal CTL 2.

For example, in the erasing period PCL or the sampling period PSML, the control signal CTL2 is set to the L level, and the selection unit 231 of the node potential switching unit 23 connects the power supply line Vclppix to the reference potential VSS.

On the other hand, in the hold signal read period PHRD, the control signal CTL2 is set to the H level, and the selection section 231 of the node potential switching section 23 connects the power supply line Vclppix to the power supply line VCLP of the specific voltage VCLP.

The switching transistor CLP1-Tr of the node potential switching section 23 is turned on/off in response to the control signal CLP, is turned on while the control signal CLP is at the H level, connects the holding node to the power supply line Vclppix connected to the source terminal, and sets the holding node ND23 to the specific voltage VCLP (for example, 2.6V) or the reference potential VSS.

That is, the switching transistor CLP1-Tr of the node potential switching unit 23 according to the first embodiment functions as a switching element.

The node potential switching unit 23 sets the holding node ND23 to the specific voltage VCLP in the holding signal read period PHRD, thereby serving as an initial voltage for CDS reading by the output unit 2124 of the signal holding unit 212.

In addition, the node potential switching section 23 fixes the holding node ND23 to the reference potential VSS (e.g., 0V) when reading another row, thereby causing the source follower transistors SF2-Tr of the output section 2124 to operate as off switches.

In this way, in the solid-state imaging device 10 according to the first embodiment, in the signal holding section 212 which stores the pixel signal, the pixel signal is sampled simultaneously in all the pixels in the voltage mode, and the converted signal corresponding to the read signal held by the first signal holding capacitor CS21 and the second signal holding capacitor CR21 is read to the vertical signal line LSGN11 and supplied to the column reading circuit 40.

In the solid-state imaging device 10 according to the first embodiment, the constant current source for driving the signal line LSGN12 between the output node ND21 of the photoelectric conversion reading section 211 and the input section of the signal holding section 212 is not disposed in the input section 2121 of the signal holding section 212, for example, and the signal line LSGN12 is driven by a dynamic current source provided by the first signal holding capacitor CS21 and the second signal holding capacitor CR 21.

The two capacitors, i.e., the first signal holding capacitor CS21 and the second signal holding capacitor CR21, are cleared to 0V during the clearing period, and electrons are supplied from the first signal holding capacitor CS21 and the second signal holding capacitor CR21 when the two capacitors are connected to the source follower transistors SF1-Tr of the photoelectric conversion reading section 211.

Therefore, the first signal holding capacitor CS21 and the second signal holding capacitor CR21 function as dynamic current sources.

The pixel unit 20 of the first embodiment is configured such that, for example, as shown in fig. 3, the pixels 21 having the above-described configuration are arranged as a pixel array, and a plurality of pixel arrays are combined.

Fig. 3 is a diagram for explaining a pixel array in the pixel section 20 of the solid-state imaging device 10 according to the first embodiment of the present invention.

The pixel section 20 of the solid-state imaging device 10 according to the first embodiment includes a pixel array 230 and a holding section array 240.

In the pixel array 230, the photoelectric conversion reading portions 211 of the plurality of pixels 21 are arranged in a two-dimensional row-column shape (matrix shape) of N rows × M columns.

The pixel array 230 may output, for example, an aspect ratio of 16: in the image system of fig. 9, the photoelectric conversion reading units 211 of the plurality of pixels 21 are arranged in a two-dimensional row-column shape (matrix shape) of N rows × M columns.

In the holding portion array 240, the signal holding portions 212 of the plurality of pixels 21 are arranged in a two-dimensional row-column shape (matrix shape) of N rows × M columns corresponding to the pixel array 230.

The holding portion array 240 can output, for example, an image having an aspect ratio of 16: in the image system of fig. 9, the signal holding sections 212 of the plurality of pixels 21 are arranged in a two-dimensional row-column shape (matrix shape) of N rows × M columns.

In the solid-state imaging device 10, as described below, when a stacked structure of a first substrate (upper substrate) and a second substrate (lower substrate) is provided, the pixel array 230 is formed on the first substrate, and the holding portion array 240 is formed on the second substrate so as to face the pixel array 230.

In this case, the holding section array 240 may also be completely shielded from light by the metal wiring layer.

The pixel unit 20, under the control of the reading unit 70, activates (active) the pixel array 230 and the holding unit array 240 in the global shutter mode to read the pixel signal.

In the pixel section 20, all pixels reset the photodiodes at the same time using the reset transistors RST1-Tr and the transfer transistors TG1-Tr, whereby all pixels start exposure simultaneously in parallel. After the end of a specific exposure period, the signal holding section 212 samples the output signal output from the photoelectric conversion reading section using the transfer transistors TG1-Tr, whereby all pixels end exposure in parallel at the same time. Thereby, a complete shutter action is electronically achieved.

Since N rows × M columns of pixels are arranged in the pixel unit 20, there are N control lines for the control signals SEL, RST and TG, and M vertical signal lines LSGN 11.

In fig. 1, each row control line is denoted as one row scanning control line. Similarly, each vertical signal line LSGN11 is represented as one vertical signal line.

Further, the second signal line LSGN12 is arranged between the photoelectric conversion reading section 211 and the signal holding section 212 in each pixel.

The vertical scanning circuit 30 drives the photoelectric conversion reading section 211 and the signal holding section 212 of the pixel 21 by a row scanning control line in the shutter row and the reading row under the control of the timing control circuit 60.

The vertical scanning circuit 30 outputs a row selection signal of a read row for reading a signal and a row address of a shutter row for resetting the electric charge accumulated in the photodiode PD21, based on an address signal.

The column reading circuit 40 may include a plurality of column signal processing circuits (not shown) arranged corresponding to the column outputs of the pixel units 20, and may be configured to perform column-parallel processing using the plurality of column signal processing circuits.

In the global shutter mode, the column read circuit 40 performs amplification processing and AD conversion processing on the differential pixel signal pixout (vsl) read from the signal holding section 212 of the pixel 21 on the vertical signal line LSGN 11.

Here, the pixel signal pixout (vsl) refers to a pixel read signal including a read signal VSIG and a read reset signal VRST which are sequentially read from a pixel (in this example, the photoelectric conversion read portion 211 of the pixel 21 and the signal holding portion 212) in the global shutter mode.

In the solid-state imaging device 10 according to the first embodiment, the column readout circuit 40 is formed so as to be shared by one circuit configuration regardless of the operation mode or the signal form of the readout signal (signal such as single-ended or differential signal).

The column read circuit 40 includes, for example, amplifiers (AMP, amplifier)41 and ADCs (analog-to-digital converters, AD converters) 42 as shown in fig. 4.

The horizontal scanning circuit 50 scans signals processed by a plurality of column signal processing circuits such as ADCs of the column reading circuit 40, transmits the signals in the horizontal direction, and outputs the signals to a signal processing circuit not shown.

The timing control circuit 60 generates timing signals necessary for signal processing of the pixel portion 20, the vertical scanning circuit 30, the reading circuit 40, the horizontal scanning circuit 50, and the like.

In the first embodiment, the reading unit 70 enables the pixel array 230 and the holding unit array 240 to read the differential pixel signal pixout, for example, in the global shutter mode.

(laminated structure of solid-state image pickup device 10)

Next, a laminated structure of the solid-state imaging device 10 according to the first embodiment will be described.

Fig. 5 is a diagram for explaining a first layered structure of the solid-state image pickup device 10 according to the first embodiment.

Fig. 6 is a diagram for explaining a second stacked structure of the solid-state image pickup device 10 according to the first embodiment.

The solid-state image pickup device 10 according to the first embodiment has a stacked structure of a first substrate (upper substrate) 110 and a second substrate (lower substrate) 120.

The solid-state imaging device 10 is formed as an imaging device having a laminated structure that is cut out by dicing (dicing) after being bonded at a wafer (wafer) level, for example.

In this example, the first substrate 110 is stacked over the second substrate 120.

As shown in fig. 5 and 6, a pixel array 230 (region 111) in which the photoelectric conversion reading portions 211 of the respective pixels 21 of the pixel portion 20 are arranged is formed on the first substrate 110 centering on the central portion thereof.

In the example of fig. 6, the regions 112 and 113 for a part of the column read circuit 40 are formed around the pixel array 230 on the upper and lower sides in the figure. Furthermore, a part of the column readout circuit 40 may be disposed on either the upper side or the lower side of the region 111 of the pixel array 230.

In this way, in the first embodiment, the photoelectric conversion reading portion 211 of the pixel 21 is basically formed in a matrix on the first substrate 110.

On the second substrate 120, a holding section array 240 (region 121) and vertical signal lines LSGN11 are formed around the central portion thereof, and the signal holding sections 212 of the pixels 21 connected to the output nodes ND21 of the photoelectric conversion reading sections 211 of the pixel array 230 are arranged in a matrix in the holding section array 240 (region 121).

The array of holding sections 240 may also be completely shielded from light by the metal wiring layer.

In the example of fig. 5 and 6, the areas 122 and 123 for the column read circuit 40 are formed on the upper and lower sides in the figure around the holding portion array 240. The column read circuit 40 may be disposed on either the upper side or the lower side of the region 121 of the holding portion array 240.

Further, a region for the vertical scanning circuit 30, or a region for a digital system or an output system may be formed on the side portion of the holding portion array 240.

In addition, the vertical scanning circuit 30, the horizontal scanning circuit 50, and the timing control circuit 60 may be formed over the second substrate 120.

In such a stacked structure, the output node ND21 of each photoelectric conversion reading section 211 of the pixel array 230 of the first substrate 110 and the input node ND22 of the signal holding section 212 of each pixel 21 of the second substrate 120 are electrically connected to each other by using a through-hole (Die-to-Die Via) or a micro bump, for example, as shown in fig. 2.

(reading operation of solid-state imaging device 10)

The characteristic structure and function of each part of the solid-state imaging device 10 have been described above.

Next, the operation of reading differential pixel signals of the solid-state imaging device 10 according to the first embodiment will be described in detail.

Fig. 7(a) to (I) are timing charts for mainly explaining the operation of the clear period and the sampling period of the pixel section in the specific shutter mode of the solid-state imaging device according to the first embodiment.

Fig. 8(a) to (F) are timing charts mainly explaining the reading operation in the hold signal reading period of the pixel section in the specific shutter mode of the solid-state imaging device according to the first embodiment.

Fig. 7(a) shows a control signal RST of the reset transistor RST1-Tr of the photoelectric conversion reading section 211 of the pixel 21. Fig. 7(B) shows a control signal TG of the transfer transistor TG1-Tr of the photoelectric conversion reading section 211 of the pixel 21. Fig. 7(C) shows the control signal SEL of the selection transistor SEL1-Tr of the photoelectric conversion reading section 211 of the pixel 21.

Fig. 7(D) shows a control signal SHR of the second sampling transistor SHR1-Tr of the signal holding section 212 of the pixel 21. Fig. 7(E) shows a control signal SHS of the first sampling transistor SHS1-Tr of the signal holding section 212 of the pixel 21.

Fig. 7(F) shows a control signal CLP of the switching transistor CLP1-Tr of the node potential switching section 23.

Fig. 7(G) shows the level of the power supply line Vclppix of the node potential switching section 23. Fig. 7(H) shows the level of the power supply line Vddpix of the power supply switching unit 22.

Fig. 7(I) shows a bus reset signal BRST of the bus reset unit 24.

Further, < ＊ > in FIG. 7 indicates that it is the same on all rows.

Fig. 8(a) shows a control signal SHR of the second sampling transistor SHR1-Tr of the signal holding section 212 of the pixel 21. Fig. 8(B) shows a control signal SHS of the first sampling transistor SHS1-Tr of the signal holding section 212 of the pixel 21.

Fig. 8(C) shows a control signal CLP of the switching transistor CLP1-Tr of the node potential switching section 23.

Fig. 8(D) shows the level of the power supply line Vclppix of the node potential switching section 23. Fig. 8(E) shows the level of the power supply line Vddpix of the power supply switching unit 22.

Fig. 8(F) shows a bus reset signal BRST of the bus reset unit 24.

Further, < n > in FIG. 8 represents a row read by the column read circuit.

(sampling action)

First, the sampling operation of the sampling period PSML including the zero clear operation of the zero clear (zero clear) period PCL will be mainly described in connection with fig. 7(a) to (I).

In the sampling period PSML, as shown in fig. 7(H), the power supply line Vddpix connected to the drain terminal of the source follower transistor of the output section 2124 is held at the reference potential VSS (for example, 0V) by the power supply switching section 22.

As shown in fig. 7G, the power supply line vclppex is held at the reference potential VSS (e.g., 0V) by the node potential switching section 23.

As shown in fig. 7I, the switching element 241 of the bus reset unit 24 is turned on by a bus reset signal BRST to the switching element 241 and fixed to the reference potential VSS (e.g., 0V).

As a result, the source follower transistors SF2-Tr become strong inversion operation regions, and are equivalent to MOS capacitors. As a result, band limitation is imposed on the former transistor of the MOS capacitor, and noise can be reduced.

In addition, in the sampling period PSML, as shown in fig. 7(C), the selection transistor SEL1-Tr of the photoelectric conversion reading section 211 is kept in an on state in accordance with the control signal SEL at the H level.

In this state, first, the first clear division period PCL1 is performed in which the first signal holding capacitor CS21 and the second signal holding capacitor CR21 of the signal holding unit 212 are cleared.

In the first clear division period PCL1, as shown in fig. 7(F), the control signal CLP is set to the H level for the specific period, and the switching transistor CLP1-Tr of the node potential switching section 23 is thereby kept in the on state for the specific period. Accordingly, the holding node ND23 of the signal holding portion 212 is held at the reference potential VSS (e.g., 0V).

In parallel with this, as shown in fig. 7(D) and (E), the control signal SHR of the second sampling transistor SHR1-Tr and the control signal SHS of the first sampling transistor SHS1-Tr of the signal holding section 212 are set to the H level, and the first sampling transistor SHS1-Tr and the second sampling transistor SHR1-Tr are in the on state.

Thereby, the first signal holding capacitor CS21 and the second signal holding capacitor CR21 of the signal holding section 212 are cleared to 0V.

Then, when the two capacitors of the first signal holding capacitor CS21 and the second signal holding capacitor CR21 are cleared to 0V during the clearing period and are in a state of being connected to the source follower transistors SF1-Tr of the photoelectric conversion reading section 211, electrons are supplied from the first signal holding capacitor CS21 and the second signal holding capacitor CR 21.

Therefore, the first signal holding capacitor CS21 and the second signal holding capacitor CR21 function as dynamic current sources.

Next, following the first clear division period PCL1, a reset signal read period PRDR during which the read reset signal VRST, which is a pixel signal, is read from the photoelectric conversion reading section 211 arrives.

In the reset signal read period PRDR, the reset transistors RST1-Tr are selected to be kept in an on state while the control signal RST is at the H level.

Next, while the control signal RST is at the H level, the floating diffusion FD21 is reset to the potential of the power supply line Vdd.

In the photoelectric conversion reading section 211, the charge of the floating diffusion layer FD21 is converted into a voltage signal corresponding to the amount of charge (potential) by the source follower transistor SF1-Tr, and a read reset signal VRST output as a column is output from the output node ND21 via the selection transistor SEL 1-Tr.

Then, the control signal RST of the reset transistor RST1-Tr is switched to the L level, and the reset transistor RST1-Tr is turned off.

In the signal holding section 212, for example, the control signal SHR is continuously held at the H level from the first clear division period PCL1, and the second sampling transistors SHR1-Tr are held in the on state.

Thereby, the read reset signal VRST output from the output node ND21 of the photoelectric conversion reading section 211 is transmitted to the corresponding signal holding section 212 through the second signal line LSGN12, and is held in the second signal holding capacitor CR21 by the second sampling transistor SHR 1-Tr.

After the read reset signal VRST is held in the second signal holding capacitor CR21, the control signal SHR is switched to the L level, and the second sampling transistors SHR1-Tr are turned into a non-conductive state.

Second, the second clear divide period PCL2 is reached.

In the second clear division period PCL2, as shown in fig. 7(F), the control signal CLP is set to the H level for the specific period, and the switching transistor CLP1-Tr of the node potential switching section 23 is thereby kept in the on state for the specific period. Accordingly, the holding node ND23 of the signal holding portion 212 is held at the reference potential VSS (e.g., 0V).

In parallel with this, as shown in fig. 7(D) and (E), the control signal SHR of the second sampling transistor SHR1-Tr of the signal holding section 212 is held at the L level, the control signal SHS of the first sampling transistor SHS1-Tr is set to the H level, the first sampling transistor SHS1-Tr is held in the conductive state, and the second sampling transistor SHR1-Tr is held in the non-conductive state.

Thereby, the first signal holding capacitor CS21 of the signal holding section 212 is cleared to 0V.

Next, when the first signal holding capacitor CS21 is cleared to 0V during the clearing period and is in a state of being connected to the source follower transistor SF1-Tr of the photoelectric conversion reading section 211, electrons are supplied from the first signal holding capacitor CS 21.

Therefore, the first signal holding capacitor CS21 functions as a dynamic current source.

Next, the second clear division period PCL2 is followed by the signal read period PRDS during which the read signal VSIG, which is a pixel signal, is read from the photoelectric conversion reading section 211.

A specific period of the signal read period PRDS is a transfer period.

In the transfer period, in each photoelectric conversion reading section 211, the transfer transistor TG1-Tr is selected to be in an on state while the control signal TG is at the H level, and the charge (electrons) photoelectrically converted and accumulated by the photodiode PD21 is transferred to the floating diffusion FD 21.

When the transmission period ends, the control signal TG of the transmission transistors TG1-Tr is switched to the L level, and the transmission transistors TG1-Tr are in a non-conduction state.

In the photoelectric conversion reading section 211, the charges of the floating diffusion layer FD21 are converted into a voltage signal corresponding to the amount of charges (potential) by the source follower transistor SF1-Tr, and a read signal VSIG output as a column is output from the output node ND21 via the selection transistor SEL 1-Tr.

In addition, the following control is performed in all the signal holding sections 212 of the holding section array 240.

The signal holding unit 212 is controlled so that the control signal SHS is continuously held at the H level and the first sampling transistors SHS1-Tr are held in the on state.

Thus, the read signal VSIG output from the output node ND21 of the photoelectric conversion reading section 211 is transmitted to the corresponding signal holding section 212 through the second signal line LSGN12 and is held by the first signal holding capacitor CS21 through the first sampling transistor SHS 1-Tr.

After the read signal VSIG is held in the first signal holding capacitor CS21, the control signal SHS is switched to the L level, and the first sampling transistors SHS1-Tr are turned into a non-conductive state.

Thus, the sampling period PSML ends. Subsequently, as shown in fig. 7(C), the control signal SEL is switched to the L level, and the selection transistors SEL1-Tr are turned off.

Then, the bus reset signal BRST switches to the L level, and the source terminal of the source follower transistor SF2-Tr of the output section 2124 comes out of the state fixed to 0V, and becomes drivable with a constant current.

Next, as shown in fig. 7(H), the power supply line Vddpix connected to the drain terminal of the source follower transistor SF2-Tr of the output section 2124 is held at the power supply potential Vdd of the power supply line Vdd by the power supply switching section 22.

Next, the off-state setting period POS during which the source follower transistors SF2-Tr are set to the off-state is reached.

In the off-state setting period POS, as shown in fig. 7(F), the control signal CLP is set to the H level for a certain period, and thereby the switching transistors CLP1-Tr of the node potential switching section 23 are kept in the on state for the certain period. With this, the holding node ND23 of the signal holding section 212 is held at the reference potential VSS (e.g., 0V), and the source follower transistors SF2-Tr are set to an off state.

After the off-state setting period POS is completed, as shown in fig. 7(G), the power supply line Vclppix is switched to the level of the specific voltage VCLP by the node potential switching section 23.

Next, in the photoelectric conversion reading section 211, the reset transistor RST1-Tr and the transfer transistor TG1-Tr are kept in an on state for a certain period, and the floating diffusion FD21 and the photodiode PD21 are reset (pixel reset).

In this state, a hold signal reading process is performed in which the read reset signal VRST held by the second signal holding capacitor CR21 of the second sampling unit 2123 and the read signal VSIG held by the first signal holding capacitor CS21 of the first sampling unit 2122 are read to the vertical signal line LSGN 11.

In the hold signal read period PHRD in which the hold signal read process is performed, the power supply line vddpi connected to the drain terminal of the source follower transistor SF2-Tr of the output section 2124 is held at the power supply potential Vdd of the power supply line Vdd by the power supply switching section 22.

Further, the power supply line Vclppix is switched to the level of the specific voltage VCLP by the node potential switching section 23.

In the first initial value reading period PIVR1 in the hold signal reading period PHRD, as shown in fig. 8(C), the control signal CLP is set to the H level for a certain period, and thereby the switching transistors CLP1-Tr of the node potential switching section 23 are held in the on state for the certain period. Accordingly, the holding node ND23 of the signal holding section 212 is held at the level of the specific voltage VCLP corresponding to the initial value.

At this time, in each signal holding section 212, the first initial value read signal VIVR, which is a conversion signal output as a column, is output to the vertical signal line LSGN11 in accordance with the holding voltage (initial value) of the node ND23 by the source follower transistor SF2-Tr having a gate connected to the node ND23, and is supplied to the read circuit 40.

Next, the hold reset signal read period PHRR following the first initial value read period PIVR1 is reached.

In the hold reset signal read period PHRR, as shown in fig. 8(a), the control signal SHR of the second sampling transistor SHR1-Tr of the signal holding section 212 is set to the H level, and the second sampling transistor SHR1-Tr is held in the on state.

Thereby, the read reset signal VRST held by the second signal holding capacitor CR21 is transferred to the holding node ND 23.

In each signal holding section 212, a read reset signal VRST, which is a conversion signal output as a column, is output to the vertical signal line LSGN11 by the source follower transistor SF2-Tr having a gate connected to the node ND23, based on the holding voltage of the second signal holding capacitor CR21 connected to the node ND23, and is supplied to the read circuit 40.

The second initial value reading period PIVR2 in the hold signal reading period PHRD is reached.

In the second initial value reading period PIVR2, as shown in fig. 8(C), the control signal CLP is set to the H level for a certain period, and thereby the switching transistors CLP1-Tr of the node potential switching section 23 are kept in the on state for the certain period. Accordingly, the holding node ND23 of the signal holding section 212 is held at the level of the specific voltage VCLP corresponding to the initial value.

At this time, in each signal holding section 212, the second initial value read signal VIVS, which is a conversion signal output as a column, is output to the vertical signal line LSGN11 in accordance with the holding voltage (initial value) of the node ND23 by the source follower transistor SF2-Tr having a gate connected to the node ND23, and is supplied to the read circuit 40.

Next, the hold read signal read period PHSR is reached which is subsequent to the second initial value read period PIVR 2.

In the hold read signal read period PHRR, as shown in fig. 8(B), the control signal SHS of the first sampling transistor SHS1-Tr of the signal holding section 212 is set to the H level, and the first sampling transistor SHS1-Tr is held in the on state.

Thereby, the read signal VSIG held by the first signal holding capacitor CS21 is transferred to the holding node ND 23.

In each signal holding section 212, a read signal VSIG, which is a conversion signal output as a column, is output to the vertical signal line LSGN11 by the source follower transistor SF2-Tr having a gate connected to the node ND23, based on the holding voltage of the first signal holding capacitor CS21 connected to the node ND23, and is supplied to the read circuit 40.

Next, for example, in the column reading circuit 40 constituting a part of the reading unit 70, amplification processing and AD conversion processing of the read reset signal VRST and the read signal VSIG of the pixel signal pixout are performed, and CDS processing is performed by acquiring a difference { VRST-VSIG } between the two signals.

After the hold signal read period PHRD, the off-state setting period POS during which the source follower transistors SF2-Tr are set to the off state is reached in the same manner as after the sampling period ends.

As described above, according to the first embodiment, the pixel section 20 is configured as, for example, a stacked CMOS image sensor including the pixel array 230 of the photoelectric conversion reading section 211 in which a plurality of pixels 21 are arranged in rows and columns and the holding section array 240 of the signal holding section 212 in which a plurality of pixels 21 are arranged in rows and columns.

In a laminated CMOS image sensor including a first substrate 110 and a second substrate 120, a first sampling unit 2122 and a second sampling unit 2123 each including a sampling transistor (1T) and a sampling capacitor (1C) are mounted on a signal holding unit 212 formed on the second substrate 120, and a holding node ND23, which is a coupling node of the two sampling units, is used as a bidirectional port, whereby a solid-state image sensor having a global shutter function is configured to realize a signal amplitude substantially equal to that of differential readout using four transistors.

Further, according to the first embodiment, the node potential switching unit 23 functioning as a clamp circuit and the source follower transistors SF2-Tr are connected to the junction of the two first and second sampling units 2122 and 2123, and the clamp voltage at the holding node ND23 is set to the reference potential VSS (e.g., 0V) or the specific voltage VCLP, whereby the voltage at the junction is dynamically changed, and the drain voltages of the source follower transistors SF2-Tr are dynamically changed to the reference VSS potential (e.g., 0V) or the power supply potential VDD.

In addition, according to the first embodiment, the source follower transistors SF2-Tr of the output section 2124 are sampled in the strong inversion mode state, whereby the gate capacitance can be increased and the band limiting capacitance can be increased.

Therefore, according to the solid-state image pickup device 10 of the first embodiment, it is possible to suppress the input conversion noise while maintaining high pixel sensitivity while preventing the signal amplitude loss in the sampling unit while suppressing the increase in the number of transistors.

More specifically, the number of transistors that conventionally require eight transistors can be reduced to four, and miniaturization can be achieved.

The silicon area used as a transistor up to now can be replaced with a MOS capacitor, so that noise can be reduced.

The sampling capacitor can be cleared without adding a transistor, and thus miniaturization can be achieved.

One of the sampling capacitors can be used as a band limiting element, and the parasitic capacitor can be used as a band limiting element, thereby reducing noise.

In addition, there is an advantage that the general 4-Tr APS structure can be used for pixels with high versatility.

In addition, according to the solid-state imaging device 10 of the first embodiment, it is possible to prevent the structure from being complicated and to prevent the area efficiency in the layout from being lowered.

The solid-state image pickup device 10 according to the first embodiment has a stacked structure of a first substrate (upper substrate) 110 and a second substrate (lower substrate) 120.

Therefore, in the first embodiment, the first substrate 110 side is formed by using substantially only NMOS-based elements, and the effective pixel region is enlarged to the maximum by using the pixel array, whereby cost performance can be improved to the maximum.

(second embodiment)

Fig. 9 is a diagram showing a configuration example of a pixel of a solid-state imaging device according to a second embodiment of the present invention.

The solid-state imaging device 10A according to the second embodiment differs from the solid-state imaging device 10 according to the first embodiment in the following point.

In the solid-state imaging device 10A according to the second embodiment, the voltage CLP < n > of the driving switching transistor CLP1-Tr of the node potential switching unit 23A can be switched to a constant current bias (bias) Voltage (VLNPIX) in addition to the pulse driving required in the first embodiment.

The switching is performed by the selection unit 232 in accordance with the control signal CTL 3.

According to the second embodiment, it is needless to say that the same effects as those of the first embodiment can be obtained, and a constant current can be read without increasing the number of transistors. At this time, the voltage VCLP is set to 0V to supply the GND potential.

(third embodiment)

Fig. 10 is a diagram showing a configuration example of a pixel of a solid-state imaging device according to a third embodiment of the present invention.

Fig. 11 is a timing chart mainly explaining the operation of the clear period and the sampling period of the pixel portion in the specific shutter mode of the solid-state imaging device according to the third embodiment.

The solid-state imaging device 10B according to the third embodiment differs from the solid- state imaging devices 10 and 10A according to the first and second embodiments in the following point.

In the solid-state image pickup device 10B according to the third embodiment, in the signal holding section 212B, the first sampling section 2122 is connected between the input node ND22 and the holding node ND 23.

In the signal holding section 212B, the second sampling transistor SHR1-Tr of the second sampling section 2123 is connected to the holding node ND23, the first signal holding capacitor CS21 of the first sampling section 2122 is connected to the input node ND22, and the first sampling transistor SHS1-Tr is connected between the holding node ND23 and a connection node ND26 between the first signal holding capacitor CS21 and the input node NS 22.

As for the reading operation, the details of the reset signal reading period PRDR of the sampling period PSML are omitted here, since they are the same as those of the first embodiment except that the first sampling transistor SHS1-Tr of the first sampling unit 2122 is kept in the on state as shown in fig. 11 (E).

According to the third embodiment, the same effects as those of the first embodiment can be obtained, and the following effects can be obtained.

By arranging the first sampling unit 2122 for reading the signal VSIG on the read path from the photoelectric conversion reading unit 211, the parasitic capacitance generated at the holding node ND23 can be minimized. This minimizes a gain drop due to charge sharing with the sampling capacitor during reading, thereby reducing input conversion noise.

Further, the source follower transistor SF1-Tr and the selection transistor SEL1 of the photoelectric conversion reading section 211 located at a position before the sampling capacitance arranged on the path impose band limitation by the sampling capacitance, and therefore noise is reduced, and thus the entire sampling noise can be reduced.

In addition, since the parasitic capacitance of the Die-to-Die VIA is also included in the sampling capacitance, the effective sampling capacitance can be increased.

In addition, the same modification as the second embodiment can be added to drive with a constant current.

The solid- state imaging devices 10, 10A, and 10B described above can be applied as imaging devices to electronic apparatuses such as digital cameras, video cameras, mobile terminals, monitoring cameras, and medical endoscope cameras.

Fig. 12 is a diagram showing an example of a configuration of an electronic apparatus on which a camera system to which a solid-state imaging device according to an embodiment of the present invention is mounted.

As shown in fig. 12, the present electronic apparatus 300 includes a CMOS image sensor 310 to which the solid-state image pickup device 10 of the present embodiment is applicable.

The electronic device 300 includes an optical system (lens or the like) 320 that guides incident light to the pixel region of the CMOS image sensor 310 (images a subject image).

The electronic device 300 includes a signal processing circuit (PRC)330 that processes an output signal of the CMOS image sensor 310.

The signal processing circuit 330 performs specific signal processing on the output signal of the CMOS image sensor 310.

The image signal processed by the signal processing circuit 330 may be displayed as a moving image on a monitor including a liquid crystal display or the like, or may be output to a printer, or may be directly recorded on a storage medium such as a memory card or the like, and may take various forms.

As described above, by mounting the solid-state image pickup devices 10, 10A, and 10B as the CMOS image sensor 310, a high-performance, small-sized, and low-cost camera system can be provided.

Further, it is possible to realize an electronic device such as a monitoring camera and a medical endoscope camera which is used for applications in which there are restrictions on installation conditions of the camera, such as an installation size, the number of connectable cables, a cable length, and an installation height.