阅读说明：本技术 图像处理系统和图像处理方法 (Image processing system and image processing method ) 是由 麻军平 孙辉 陈战雷 于 2018-09-26 设计创作，主要内容包括：本申请公开一种图像处理系统和图像处理方法。图像处理系统包括图像传感器、接口扩展装置和至少两个图像处理器。图像传感器用于感应光信号,并将光信号转换成相应的原始图像信号。图像传感器包括用于输出原始图像信号的图像输出接口。接口扩展装置包括扩展输入接口和至少两组扩展输出接口。扩展输入接口与图像输出接口电连接,用于接收图像输出接口输出的原始图像信号,至少两组扩展输出接口分别用于输出与原始图像信号对应的待处理图像信号。至少两个图像处理器与至少两组扩展输出接口对应电连接,用于接收待处理图像信号,并对待处理图像信号进行处理。(The application discloses an image processing system and an image processing method. The image processing system includes an image sensor, an interface expansion device, and at least two image processors. The image sensor is used for sensing the optical signal and converting the optical signal into a corresponding original image signal. The image sensor includes an image output interface for outputting a raw image signal. The interface expansion device comprises an expansion input interface and at least two groups of expansion output interfaces. The expansion input interface is electrically connected with the image output interface and used for receiving the original image signals output by the image output interface, and at least two groups of expansion output interfaces are respectively used for outputting the image signals to be processed corresponding to the original image signals. The at least two image processors are correspondingly and electrically connected with the at least two groups of expansion output interfaces and are used for receiving the image signals to be processed and processing the image signals to be processed.)

1. An image processing system, characterized in that it comprises:

the image sensor is used for sensing an optical signal and converting the optical signal into a corresponding original image signal, and comprises an image output interface used for outputting the original image signal;

the interface expansion device comprises an expansion input interface and at least two groups of expansion output interfaces, wherein the expansion input interface is electrically connected with the image output interface and is used for receiving the original image signals output by the image output interface, and the at least two groups of expansion output interfaces are respectively used for outputting image signals to be processed corresponding to the original image signals; and

and the at least two image processors are correspondingly and electrically connected with the at least two groups of the expansion output interfaces and are used for receiving the image signals to be processed and processing the image signals to be processed.

2. The image processing system according to claim 1, wherein said interface expanding means is configured to output the same image signal to be processed as the original image signal through at least two sets of said expanded output interfaces.

3. The image processing system according to claim 1, wherein the image signal to be processed comprises a first image signal to be processed, the interface expansion means is configured to process the original image signal to obtain the first image signal to be processed, and the interface expansion means is configured to output the first image signal to be processed through at least one set of the expansion output interfaces.

4. The image processing system of claim 3, wherein the interface expansion means for processing the raw image signal comprises:

and processing the original image signal by the pixel number and/or the pixel bit width.

5. The image processing system according to claim 3, wherein the image signal to be processed comprises a second image signal to be processed, the second image signal to be processed being different from the first image signal to be processed, the interface expansion means being configured to output the second image signal to be processed through at least another set of the expansion output interfaces.

6. The image processing system of claim 1, wherein the image output interface comprises a multi-channel data interface.

7. The image processing system of claim 6, wherein a single channel of the data interface has a bandwidth of no less than 200 Mbps.

8. The image processing system of claim 6, wherein the data interface comprises a serial data interface.

9. The image processing system of claim 8, wherein the serial data interface comprises an LVDS interface or an MIPI interface.

10. The image processing system of claim 1, wherein the interface expansion means comprises a programmable logic device.

11. The image processing system of claim 10, wherein the programmable logic device comprises an FPGA or a CPLD.

12. The image processing system of claim 1, wherein the interface expansion means comprises an ASIC chip.

13. The image processing system of claim 1, wherein at least two of the image processors comprise a first image processor and a second image processor, the second image processor processing the image signals to be processed at least partially differently than the first image processor processing the image signals to be processed.

14. The image processing system of claim 13, wherein the first image processor and the second image processor comprise different chips.

15. The image processing system of claim 13, wherein the first image processor and the second image processor comprise the same chip.

16. The image processing system of claim 13, wherein at least two of the image processors are configured to perform at least one of image signal processing, image display, image compression, image storage, and image transmission on the image signal to be processed.

17. The image processing system of claim 16, wherein the first image processor is configured to perform first image signal processing on the image signal to be processed.

18. The image processing system of claim 17, wherein the second image processor is configured to perform a first image compression on the image signal to be processed.

19. The image processing system of claim 18, wherein the first image processor is configured to perform a first image signal processing on the image signal to be processed, and further configured to perform a second image compression on the image signal to be processed, wherein the second image compression is different from the first image compression.

20. The image processing system according to claim 19, wherein the image quality of the image obtained by the second image compression is higher than the image quality of the image obtained by the first image compression.

21. The image processing system of claim 17, wherein the second image processor is configured to perform a first image storage of the image signal to be processed.

22. The image processing system of claim 21, wherein the first image processor is configured to perform a first image signal processing on the image signal to be processed, and further configured to perform a second image storage on the image signal to be processed, wherein the first image storage is different from the second image storage.

23. The image processing system of claim 22, wherein the storage capacity of the second image processor is greater than the storage capacity of the first image processor.

24. The image processing system of claim 17, wherein the second image processor is for second image signal processing, the second image signal processing performed by the second image processor being different from the first image signal processing performed by the first image processor.

25. The image processing system of claim 1, wherein at least two of the image processors are communicatively coupled.

26. The image processing system of claim 25, wherein at least two of the image processors are wired.

27. The image processing system of claim 26, wherein at least two of the image processors are communicatively coupled via a UART interface or an I2C interface or an SPI interface.

28. The image processing system of claim 25, wherein at least two of the image processors are wirelessly connected.

29. The image processing system of claim 1, wherein the interface expansion means is configured to receive a clock signal from the image sensor, and to adjust a phase relationship between the original image signal and the clock signal when receiving the original image signal.

30. The image processing system according to claim 1, wherein the interface extension means is configured to adjust a phase relationship between the image signal to be processed and a clock signal when outputting the image signal to be processed.

31. The image processing system of claim 1, wherein the image sensor comprises a CMOS image sensor or a CCD image sensor.

32. An image processing method, characterized in that it comprises:

sensing an optical signal through an image sensor, and converting the optical signal into a corresponding original image signal to an interface expansion device;

sending the image signals to be processed corresponding to the original image signals to at least two image processors through at least two groups of expansion output interfaces of the interface expansion device; and

and processing the image signal to be processed by at least two image processors.

33. The image processing method according to claim 32, wherein the image signal to be processed is the same as the original image signal.

34. The image processing method according to claim 32, wherein the image signal to be processed includes a first image signal to be processed;

the method comprises the following steps: processing the original image signal through the interface expansion device to obtain the first image signal to be processed; and the first image signal to be processed is sent to at least one image processor through at least one group of the extended output interfaces.

35. The image processing method according to claim 34, wherein said processing the original image signal through the interface expansion apparatus to obtain the first image signal to be processed comprises:

and processing the original image signal by changing the pixel number and/or the pixel bit width.

36. The image processing method according to claim 34, wherein the image signal to be processed comprises a second image signal to be processed;

the sending the image signal to be processed corresponding to the original image signal to at least two image processors through at least two groups of expansion output interfaces of the interface expansion device comprises:

and sending the second image signal to be processed to at least one other image processor through at least one other group of the extended output interfaces.

37. The image processing method of claim 32, wherein the sensing the optical signal by the image sensor and converting the optical signal into a corresponding original image signal to the interface expansion device comprises:

and outputting the original image signal to the interface expansion device through a multi-channel data interface of the image sensor.

38. The image processing method of claim 37, wherein a bandwidth of a single channel of the data interface is not lower than 200 Mbps.

39. The image processing method of claim 37, wherein the data interface comprises a serial data interface.

40. The image processing method of claim 39, wherein the serial data interface comprises an LVDS interface or an MIPI interface.

41. The image processing method of claim 32, wherein the interface expansion means comprises a programmable logic device.

42. The image processing method of claim 41, wherein the programmable logic device comprises an FPGA or a CPLD.

43. The image processing method of claim 32, wherein the interface expansion means comprises an ASIC chip.

44. The image processing method of claim 32, wherein the at least two image processors comprise a first image processor and a second image processor;

the processing the image signal to be processed by at least two image processors comprises:

processing the image signal to be processed by the first image processor and the second image processor respectively; wherein the processing of the image to be processed by the first image processor is at least partially different from the processing of the image signal to be processed by the second image processor.

45. The image processing method of claim 44, wherein the first image processor and the second image processor comprise different chips.

46. The image processing method of claim 44, wherein the first image processor and the second image processor comprise the same chip.

47. The image processing method according to claim 44, wherein said processing the image signal to be processed by at least two of the image processors comprises:

and performing at least one of image signal processing, image display, image compression, storage and image transmission on the image signal.

48. The image processing method according to claim 47, wherein said processing the image signal to be processed by at least two of the image processors comprises: and carrying out first image signal processing on the image signal to be processed by the first image processor.

49. The image processing method of claim 48, wherein said processing the image signal to be processed by at least two of the image processors comprises: and performing first image compression on the image signal to be processed by the second image processor.

50. The image processing method according to claim 49, wherein said processing the image signal to be processed by at least two of the image processors comprises:

after the first image signal processing is carried out on the image signal to be processed, the first image processor further carries out second image compression on the image to be processed, wherein the second image compression is different from the first image compression.

51. The image processing method according to claim 50, wherein an image quality of the image obtained by said second image compression is higher than an image quality of the image obtained by said first image compression.

52. The image processing method of claim 48, wherein said processing the image signal to be processed by at least two of the image processors comprises:

and performing first image storage on the image signal to be processed through the second image processor.

53. The image processing method of claim 52, wherein said processing the image signal to be processed by at least two of the image processors comprises:

after the first image signal processing is carried out on the image signal to be processed, the first image processor further carries out second image storage on the image to be processed, and the first image storage is different from the second image storage.

54. The image processing method of claim 53, wherein a storage capacity of the second image processor is greater than a storage capacity of the first image processor.

55. The image processing method of claim 48, wherein said processing the image signal to be processed by at least two of the image processors comprises:

performing second image signal processing by the second image processor, the second image signal processing being different from the first image signal processing.

56. The method of image processing according to claim 32, comprising: communication is performed between at least two of the image processors.

57. The image processing method of claim 56, wherein said communicating between at least two of said image processors comprises: and communicating between at least two of the image processors by wire.

58. The image processing method of claim 57, wherein said communicating between at least two of said image processors comprises: communication is performed between at least two of the image processors through a UART interface or an I2C interface or an SPI interface.

59. The image processing method of claim 56, wherein said communicating between at least two of said image processors comprises: and communicating between at least two of the image processors in a wireless manner.

60. The method of image processing according to claim 32, comprising: receiving a clock signal from the image sensor through the interface expansion device, and adjusting a phase relationship between the original image signal and the clock signal when receiving the original image signal.

61. The image processing method according to claim 32, wherein said sending the image signal to be processed corresponding to the original image signal to at least two image processors through at least two sets of extended output interfaces of the interface extension apparatus comprises:

and adjusting the phase relation between the image signal to be processed and the clock signal when the image signal to be processed is output through the interface expansion device.

62. The method of claim 32, wherein the image sensor comprises a CMOS image sensor or a CCD image sensor.

Technical Field

The present application relates to the field of image processing, and in particular, to an image processing system and an image processing method.

Background

Image processing systems play an important role in devices such as photographing devices. An image processing system generally includes an image sensor and an image processor. The image sensor is responsible for converting the optical signal into an electrical signal to the image processor. And after receiving the electric signal output by the image sensor, the image processor processes the electric signal, namely, the image signal is processed. According to different application scenes, the image processing system needs to process different image signals to meet different requirements.

Existing image processing systems perform all image processing tasks by a single image processor. Different image processors are good at different functions, and the functions of each image processor design are often limited. Therefore, the processing of the image signal by the single image processor is limited, and a higher level of function cannot be supported, so that the function of the entire system is limited.

Disclosure of Invention

The present application provides an image processing system and an image processing method that can support higher-level functions.

According to an aspect of an embodiment of the present application, there is provided an image processing system including: the image sensor is used for sensing an optical signal and converting the optical signal into a corresponding original image signal, and comprises an image output interface used for outputting the original image signal; the interface expansion device comprises an expansion input interface and at least two groups of expansion output interfaces, wherein the expansion input interface is electrically connected with the image output interface and is used for receiving the original image signals output by the image output interface, and the at least two groups of expansion output interfaces are respectively used for outputting image signals to be processed corresponding to the original image signals; and the at least two image processors are correspondingly and electrically connected with the at least two groups of the extended output interfaces and are used for receiving the image signals to be processed and processing the image signals to be processed.

According to another aspect of embodiments of the present application, there is provided an image processing method including: sensing an optical signal through an image sensor, and converting the optical signal into a corresponding original image signal to an interface expansion device; sending the image signals to be processed corresponding to the original image signals to at least two image processors through at least two groups of expansion output interfaces of the interface expansion device; and processing the image signal to be processed by at least two image processors.

The image processing system is characterized in that at least two image processors are connected to the image sensor through the interface expansion device, the at least two image processors respectively perform image processing, the image processors can be selected more flexibly when the quality of image signals is guaranteed during design, the function of one image processor is not limited, more advanced functions can be realized by using the advantages of different image processors, and the image processing system is more abundant in function and stronger in performance.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without inventive labor.

FIG. 1 is a schematic block diagram of one embodiment of an image processing system of the present application.

Fig. 2 is a flowchart illustrating an embodiment of an image processing method according to the present application.

Detailed Description

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

Reference will now be made in detail to the exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, like numbers in different drawings represent the same or similar elements unless otherwise indicated. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present application. Rather, they are merely examples of apparatus and methods consistent with certain aspects of the present application, as detailed in the appended claims.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used in this application and the appended claims, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should also be understood that the term "and/or" as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items. Unless otherwise indicated, "front", "rear", "lower" and/or "upper" and the like are for convenience of description and are not limited to one position or one spatial orientation. The terms "connected" or "coupled" and the like are not restricted to physical or mechanical connections, but may include electrical connections, whether direct or indirect.

"plurality" means at least two.

The image processing system of the embodiment of the application comprises an image sensor, an interface expansion device and at least two image processors. The image sensor is used for sensing the optical signal and converting the optical signal into a corresponding original image signal. The image sensor includes an image output interface for outputting a raw image signal. The interface expansion device comprises an expansion input interface and at least two groups of expansion output interfaces. The expansion input interface is electrically connected with the image output interface and used for receiving the original image signals output by the image output interface, and at least two groups of expansion output interfaces are respectively used for outputting the image signals to be processed corresponding to the original image signals. The at least two image processors are correspondingly and electrically connected with the at least two groups of expansion output interfaces and are used for receiving the image signals to be processed and processing the image signals to be processed.

The image processing system connects at least two image processors to the image sensor through the interface expansion device, and the at least two image processors respectively perform image processing.

The image processing method of the embodiment of the application comprises the following steps: sensing the optical signal through an image sensor, and converting the optical signal into a corresponding original image signal to an interface expansion device; sending the image signals to be processed corresponding to the original image signals to at least two image processors through at least two groups of expansion output interfaces of the interface expansion device; and processing the image signal to be processed by at least two image processors.

The image processing system and the image processing method according to the present application will be described in detail below with reference to the accompanying drawings. The features of the following examples and embodiments may be combined with each other without conflict.

FIG. 1 is a schematic block diagram illustrating one embodiment of an image processing system 100. The image processing system 100 may be used in a camera device, such as a digital camera, but may also be used in other devices. Image processing system 100 may comprise a digital image processing system. The image processing system 100 of the embodiment of the present application includes an image sensor 101, an interface expansion apparatus 102, and at least two image processors, i.e., a first image processor 103 and a second image processor 104.

The image sensor 101 is used for sensing an optical signal and converting the optical signal into a corresponding original image signal. The image sensor 101 includes an image output interface 105 for outputting a raw image signal. The image sensor 101 may convert the optical signal into an analog electrical signal and convert the analog electrical signal into a digital signal, and the original image signal may be a digital signal. In some embodiments, the image sensor 101 includes a CMOS (Complementary Metal Oxide Semiconductor) image sensor or a CCD (Charge-coupled Device) image sensor. The image sensor 101 may include a CMOS image sensor or a CCD image sensor, which may support multi-channel output, each channel having a bandwidth of not less than 200Mbps, and has features of high resolution and high frame rate, and a large amount of transmission data. For example, the image sensor 101 may be an 4/3-inch CMOS image sensor or a 1-inch CMOS image sensor.

The image output interface 105 includes a data interface of multiple channels. For example, the data interface of 9 lanes, one lane of which outputs the clock signal clk0 and the other 8 lanes of which output the image data lane00-lane0n, n is a natural number. In this example, n is 7, but is not limited thereto, and in other examples, the image output interface 105 may include other number of channels of data interfaces. In some embodiments, the bandwidth of a single channel of the data interface is no less than 200 Mbps. In some embodiments, the bandwidth of a single channel of the data interface may reach over 300 Gbps. In some embodiments, the bandwidth of a single channel of the data interface may be up to 1Gbps or more. The data interface is a high-speed data interface and can transmit the original image signal of the high-end image sensor at high speed. In one embodiment, the data interface comprises a serial data interface. In one embodiment, the serial data Interface includes an LVDS (Low Voltage Differential Signaling) Interface or an MIPI (Mobile industry processor Interface) Interface. In other embodiments, the serial data interface may include other high-speed serial data interfaces.

The interface expansion apparatus 102 includes an expansion input interface 106 and at least two sets of expansion output interfaces, in this embodiment, the two sets of expansion output interfaces are a first expansion output interface 107 and a second expansion output interface 108. The extended input interface 106 is electrically connected to the image output interface 105, and is configured to receive an original image signal output by the image output interface, and the first extended output interface 107 and the second extended output interface 108 are respectively configured to output an image signal to be processed corresponding to the original image signal.

The expansion input interface 106 may be matched with the image output interface 105, the image sensor 101 outputs the original image signal through the image output interface 105, and the interface expansion device 102 receives the original image signal through the expansion input interface 106. In one embodiment, the expansion input interface 106 comprises a multi-channel data interface. The single channel bandwidth of the extended input interface 106 is comparable to, or higher than, the single channel bandwidth of the image output interface 105. The extended input interface 106 is a high-speed data interface, which satisfies data transmission of the high-end image sensor 101. The extended input interface 106 may be a serial data interface.

The interface extension apparatus 102 is configured to receive a clock signal from the image sensor 101, and when receiving an original image signal, adjust a phase relationship between the original image signal and the clock signal so that a phase difference between each path of data of the received original image signal and the clock signal is substantially the same, thereby ensuring stability of the received data. One lane of the spread input interface 106 receives the clock signal clk0, and the other lanes may receive the multiple lanes of data lane00-lane0n of the original image signal.

In the illustrated embodiment, the interface expansion apparatus 102 includes two sets of expansion output interfaces, i.e., a first expansion output interface 107 and a second expansion output interface 108, which respectively output the to-be-processed image signals corresponding to the original image signals. In other embodiments, the interface expansion device 102 may include three or more sets of expansion output interfaces. Further, the first extended output interface 107 and the second extended output interface 108 may include multiple channels, and the number of the channels is the same as the number of the channels of the image output interface 105 and the number of the channels of the extended input interface 106.

In some embodiments, the interface extension apparatus 102 is configured to adjust a phase relationship between the image signal to be processed and the clock signal when outputting the image signal to be processed, so that a phase difference between each path of data of the output image signal to be processed and the clock signal is substantially the same, thereby ensuring stability of the output data. One lane of the first extended output interface 107 in fig. 1 outputs the clock signal clk1, and the other lanes may output the multiple lanes of data lane10-lane1n of the image signal to be processed. One lane of the second expansion output interface 108 outputs the clock signal clk2, and the other lanes may output the multiplexed data lane20-lane2n of the image signal to be processed.

In one embodiment, the interface expanding means 102 is configured to output the same image signal to be processed as the original image signal through at least two sets of expanded output interfaces. The interface expansion means 102 divides the original image signal into at least two groups of outputs. For example, the to-be-processed image signal lane10-lane1n output by the first extended output interface 107 and the to-be-processed image signal lane20-lane2n output by the second extended output interface 108 in the figure may both be the same as the original image signal lane00-lane0n output by the image sensor 101.

In another embodiment, the image signal to be processed includes a first image signal to be processed, the interface expanding means 102 is configured to process the original image signal to obtain the first image signal to be processed, and the interface expanding means 102 is configured to output the first image signal to be processed through at least one set of the expanded output interfaces, for example, the first expanded output interface 107 and/or the second expanded output interface 108 in the embodiment. The interface expansion apparatus 102 may process the original image signal and output the processed image signal. In some embodiments, the interface expansion apparatus 102 for processing the original image signal may include: the original image signal is processed by the number of pixels and/or the bit width of the pixels. In one embodiment, the processing for the number of pixels may be an adjustment of the pixel resolution, for example, adjusting the 4K resolution (4096 × 2160) to the 1080p resolution (1920 × 1080). In some other embodiments, the interface expansion device 102 may perform other processing on the original image signal.

In one embodiment, the multiple sets of extended output interfaces of the interface extension apparatus 102 each output the first image signal to be processed. In another embodiment, part of the expansion output interfaces of the interface expansion apparatus 102 outputs the first image signal to be processed, and the other part of the expansion output interfaces may output an image signal different from the first image signal to be processed. The image signal to be processed may include a second image signal to be processed, the second image signal to be processed being different from the first image signal to be processed, and the interface expanding means 102 is configured to output the second image signal to be processed through at least another set of the expanded output interfaces. For example, the first extended output interface 107 may output the first to-be-processed image signal lane10-lane1n, and the second extended output interface 108 may output the second to-be-processed image signal lane20-lane2 n. In another example, two or more sets of the extended output interfaces output first to-be-processed image signals, and/or another two or more sets of the extended output interfaces output second to-be-processed image signals. The interface expansion device 102 may output different image signals to be processed to corresponding image processors, such as the first image processor 103 and the second image processor 104 shown in fig. 1, through different expansion output interfaces, so as to meet the requirements of image data required by different image processors.

In one embodiment, the second image signal to be processed is the same as the original image signal. In another embodiment, the second image signal to be processed is different from the original image signal, and the interface expansion apparatus 102 processes the original image signal to obtain the second image signal to be processed. The interface expansion apparatus 102 may perform different processing on the original image signal to obtain different first to-be-processed image signals and second to-be-processed image signals. In some other embodiments, the interface expansion apparatus 102 may output other image signals to be processed different from the first image signal to be processed and the second image signal to be processed.

In some embodiments, the interface extension apparatus 102 includes a programmable logic device, which can be programmed according to different applications and requirements, and is convenient for designers to design and flexible. In some embodiments, the Programmable logic device may include an FPGA (Field-Programmable Gate Array). The bandwidth of the high-speed serial ports of some FPGAs can reach more than 1Gbps, and some can even reach 1.5Gbps, so that the high-speed image data transmission requirements can be met, the high-speed image data transmission device can be matched with a plurality of high-end image sensors, and a plurality of image processors can be supported, and therefore the device can be selected more flexibly. In other embodiments, the Programmable Logic Device may include a CPLD (Complex Programmable Logic Device), may be matched to many high-end image sensors, and supports many image processors.

An appropriate programmable logic device may be selected according to the number of channels of the image output interface 105 of the image sensor 101 and the number of image processors, and the number of interface channels of the programmable logic device is equal to the sum of the number of channels of the image output interface 105 and the number of channels divided into multiple sets of extended output interfaces. For example, the image sensor 101 outputs one channel of LVDS clock data and 8 channels of LVDS image data, and 9 channels of LVDS data in total, and if 1 group of interfaces of the programmable logic device receives the data of the image sensor 101 and is divided into 2 groups of interfaces to output the image data to be processed, 3 groups of interfaces are required, and 27 channels of LVDS are in total. From which a programmable logic device capable of supporting 27-way LVDS can be selected. The above is only an example, and the practical application is not limited to the above example.

In another embodiment, interface expansion device 102 comprises an ASIC (Application specific integrated Circuit) chip. The ASIC chip can be customized according to the actual application.

The at least two image processors are correspondingly and electrically connected with the at least two groups of expansion output interfaces and are used for receiving the image signals to be processed and processing the image signals to be processed. In the illustrated embodiment, the image processing system 100 includes two image processors, namely a first image processor 103 and a second image processor 104, the first image processor 103 being connected to the first extended output interface 107, and the second image processor 104 being connected to the second extended output interface 108. In other embodiments, the image processing system 100 may include three or more image processors connected to corresponding extended output interfaces.

In this way, the image processing system 100 connects at least two image processors to the image sensor 101 through the interface extension device 102, and particularly for high-end image sensors, efficient transmission of image data can be achieved. Further, the image processing system can respectively process images through at least two image processors, the image processors can be selected more flexibly during design, the function of one image processor is not limited, the advantages of different image processors can be utilized, higher performance indexes can be achieved in the respective dedicated functions, more higher functions are achieved, and the image processing system can be richer in function and stronger in performance.

In one embodiment, the at least two image processors include a first image processor 103 and a second image processor 104, the second image processor 104 at least partially processing the image signals to be processed differently than the first image processor 103. The first image processor 103 and the second image processor 104 may perform completely different or partially different processing on the image signal to be processed to obtain different processed images. The image signals to be processed received by the first image processor 103 and the second image processor 104 may be the same or different.

In one embodiment, the first image processor 103 and the second image processor 104 comprise different chips. Different chips can be dedicated to different processes, and different functions can be realized through different chips. In another embodiment, the first image processor 103 and the second image processor 104 comprise the same chip, and data can be processed differently by the same chip, so as to realize different functions, reduce the workload of a single chip, and improve the operation speed.

In one embodiment, the at least two image processors are configured to perform at least one of image signal processing, image display, image compression, image storage, and image transmission on the image signal to be processed. For example, in the present embodiment, the performing different processes on the image signal to be processed by the first image processor 103 and the second image processor 104 may include: the image signal to be processed is subjected to different kinds of processing, such as two different kinds of processing of image signal processing and image display, and/or the image signal to be processed is subjected to the same kind of processing but different ways, such as image compression processing of different standards.

In one embodiment, the image signal processing includes a first image signal processing, and the first image processor 103 is configured to perform the first image signal processing on the image signal to be processed. For example, the image signal to be processed may be subjected to processing of the number of pixels, processing of the pixel bit width, image transformation, image enhancement and restoration, image segmentation, image description, and/or image recognition, and the like.

In one embodiment, the second image processor 104 is configured to perform a first image compression on the image signal to be processed. As such, the first image processor 103 may be dedicated to image signal processing and the second image processor 104 may be dedicated to image compression.

In one embodiment, the first image processor 103 is configured to perform a second image compression on the image signal to be processed after performing the first image signal processing on the image signal to be processed, where the second image compression is different from the first image compression. The first image processor 103 may also compress the image, and the first image processor 103 and the second image processor 104 may perform image compression of different standards to obtain different compressed images. In one embodiment, the image quality of the image obtained by the second image compression is higher than the image quality of the image obtained by the first image compression. For example, the first image processor 103 performs image compression of the h.264 standard, the second image processor 104 performs image compression of the JPEG2000 standard with higher image quality, or image compression of the H265 standard, and realizes a higher-level image compression function.

In another embodiment, the second image processor 104 is configured to perform a first image storage of the image signal to be processed. As such, the first image processor 103 may be dedicated to image signal processing and the second image processor 104 may be dedicated to image storage.

In one embodiment, the first image processor 103 is configured to perform a first image signal processing on the image signal to be processed, and further configured to perform a second image storage on the image signal to be processed, where the first image storage is different from the second image storage. The first image processor 103 may also store images, and the first image processor 103 and the second image processor 104 may store images with different storage capacities. In one embodiment, the memory capacity of the second image processor 104 is larger than the memory capacity of the first image processor 103. The second image processor 104 can perform professional image storage, can support higher storage bandwidth, and can store images with higher image quality. For example, the first image processor 103 stores images by using an SD card, and the second image processor 104 stores images by using a storage device having a larger storage bandwidth and/or storage capacity than the SD card, such as a Solid-state drive (SSD) or a Universal Flash Storage (UFS) or other suitable storage devices.

In another embodiment, the second image processor 104 is used for second image signal processing, which second image signal processing performed by the second image processor 104 is different from the first image signal processing performed by the first image processor 103. The algorithm of the first image signal processing is different from the algorithm of the second image signal processing, and different images are obtained. The second image processor 104 may perform simple image signal processing with respect to the first image processor 103. For example, the first image signal processing includes processing such as image transformation, image enhancement and restoration, image segmentation, image description, and image recognition on an image signal to be processed, and the second image signal processing includes processing such as the number of pixels and the bit width of the pixels on the image signal to be processed. For example, the first image processor 103 may perform image recognition such as portrait recognition to complete subsequent image signal processing, and the second image processor 104 performs image display and/or image storage of a typical digital camera. The above are merely examples and are not limited to the above examples. The first image processor 103 and the second image processor 104 may perform different image signal processing according to actual requirements.

In some embodiments, the second image processor 104 may perform at least two functions of image compression, image storage, and second image signal processing. In one embodiment, the second image processor 104 includes a chip dedicated to image compression, performs second image signal processing on the image signal to be processed, and compresses the processed image. In another embodiment, the second image processor 104 comprises a chip dedicated to image storage, and performs the second image signal processing on the image signal to be processed, and stores the processed image. In still another embodiment, the second image processor 104 performs second image signal processing on the image signal to be processed, compresses and stores the processed image.

In some embodiments, the first image processor 103 may also be used for processing of image display, processing of image signals into data suitable for display, such as processing of HDMI (High Definition Multimedia Interface) image display. In some embodiments, the first image processor 103 may also be used for the processing of image transmissions. The image transmission includes wireless image transmission, and the first image processor 103 may be configured to wirelessly transmit the processed image to other devices. In other embodiments, the first image processor 103 and/or the second image processor 104 may also perform other image processing, for example, the second image processor 104 may be used for image display and/or image transmission.

In one embodiment, at least two image processors are communicatively coupled. For example, in the present embodiment, the first image processor 103 and the second image processor 104 may communicate with each other to work cooperatively. For example, the image signal processed by the first image processor 103 may be sent to the second image processor 104, and the second image processor 104 may compress, store, etc. the image signal. Therefore, more higher-level functions are realized, different requirements can be met, and the design is more flexible. In one embodiment, the at least two image processors may be wired. In one embodiment, the first image processor 103 and the second image processor 104 may be communicatively connected through a UART interface or an I2C interface or an SPI interface. In another embodiment, at least two image processors are wirelessly connected.

FIG. 2 is a flow diagram illustrating one embodiment of an image processing method 200. The image processing method 200 may be performed by the image processing system shown in fig. 1. The image processing method 200 comprises step 201-203. In step 201, the optical signal is sensed by the image sensor and converted into a corresponding original image signal to the interface expansion device. The image sensor may be the image sensor 101 shown in fig. 1 and the interface expansion means may be the interface expansion means 102 shown in fig. 1. In one embodiment, the image sensor comprises a CMOS image sensor or a CCD image sensor.

In step 202, the image signal to be processed corresponding to the original image signal is sent to at least two image processors through at least two sets of extended output interfaces of the interface extension device. The image processors may be the first image processor 103 and the second image processor 104 shown in fig. 1. In step 203, the image signal to be processed is processed by at least two image processors.

The image processing method sends the image signal to be processed corresponding to the original image signal output by the image sensor to at least two image processors for processing through the interface expansion device, and different processing can be carried out on the image signal to be processed through the plurality of image processors.

In one embodiment, step 201 comprises: the original image signal is output to the interface expansion device through a multi-channel data interface of the image sensor. In one embodiment, the bandwidth of a single channel of the data interface is no less than 200 Mbps. In one embodiment, the data interface comprises a serial data interface. In one embodiment, the serial data interface comprises an LVDS interface or an MIPI interface.

In one embodiment, the image signal to be processed is the same as the original image signal. In another embodiment, the image signal to be processed includes a first image signal to be processed; step 202 comprises: processing the original image signal through an interface expansion device to obtain a first image signal to be processed; and the first image signal to be processed is sent to at least one image processor through at least one group of extended output interfaces. In one embodiment, the original image signal is processed by the interface expansion device to change the pixel number and/or the pixel bit width. In one embodiment, the image signal to be processed comprises a second image signal to be processed; step 202 comprises: and sending the second image signal to be processed to at least one other image processor through at least one other set of extended output interfaces.

In one embodiment, the interface expansion device comprises a programmable logic device. In one embodiment, the programmable logic device comprises an FPGA or a CPLD. In another embodiment, the interface expansion device comprises an ASIC chip.

In one embodiment, an image processing method includes: the clock signal is received from the image sensor through the interface expansion device, and the phase relationship between the original image signal and the clock signal is adjusted when the original image signal is received. In one embodiment, the phase relationship between the image signal to be processed and the clock signal is adjusted by the interface expansion means when the image signal to be processed is output.

In one embodiment, the at least two image processors include a first image processor and a second image processor. Step 203 comprises: processing the image signals to be processed by a first image processor and a second image processor respectively; wherein the processing of the image to be processed by the first image processor is at least partially different from the processing of the image signal to be processed by the second image processor. In one embodiment, the first image processor and the second image processor comprise different chips. In another embodiment, the first image processor and said second image processor comprise the same chip.

In one embodiment, step 203 comprises: the image signal is subjected to at least one of image signal processing, image display, image compression, storage, and image transmission. In one embodiment, step 203 comprises: and carrying out first image signal processing on the image signal to be processed by a first image processor. In one embodiment, step 203 comprises: and performing first image compression on the image signal to be processed through a second image processor.

In one embodiment, step 203 comprises: and after the image signal to be processed is subjected to first image signal processing, further performing second image compression on the image to be processed through the first image processor, wherein the second image compression is different from the first image compression. In one embodiment, the image quality of the image obtained by the second image compression is higher than the image quality of the image obtained by the first image compression.

In one embodiment, step 203 comprises: and performing first image storage on the image signal to be processed through a second image processor. In one embodiment, step 203 comprises: and after the image signal to be processed is subjected to first image signal processing, further performing second image storage on the image to be processed through the first image processor, wherein the first image storage is different from the second image storage. In one embodiment, the storage capacity of the second image processor is greater than the storage capacity of the first image processor.

In one embodiment, step 203 comprises: second image signal processing is performed by a second image processor, the second image signal processing being different from the first image signal processing.

In one embodiment, the image processing method 200 includes: communication is performed between at least two image processors. In one embodiment, the communication between the at least two image processors is by wired means. In one embodiment, communication is made between at least two image processors through a UART interface or an I2C interface or an SPI interface. In another embodiment, the communication between the at least two image processors is performed wirelessly.

For the method embodiments, since they substantially correspond to the apparatus embodiments, reference may be made to the apparatus embodiments for relevant portions of the description. The method embodiment and the device embodiment are complementary.

It is noted that, in this document, relational terms such as "first" and "second," and the like, may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. The terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.

The method and apparatus provided by the embodiments of the present invention are described in detail above, and the principle and the embodiments of the present invention are explained in detail herein by using specific examples, and the description of the embodiments is only used to help understanding the method and the core idea of the present invention; meanwhile, for a person skilled in the art, according to the idea of the present invention, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present invention.

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