阅读说明：本技术 半导体器件
(Semiconductor device with a plurality of transistors
) 是由 尾添英利 于 2019-07-05 设计创作，主要内容包括：提供一种能够稳定内部电压的半导体器件。根据一个实施例,半导体器件包括：用于产生第一电压的稳定电源电路；用于使用第一电压产生与第一电压不同的第二电压的电荷泵电路,包括用于将第二电压与参考电压比较的比较电路；以及响应于从比较电路输出的比较结果信号COUT2而被控制为接通或断开的虚拟负载电路,并且虚拟负载电路接收比较结果信号COUT2并在预定时间段内接通,由此基于第一电压的电流IDD的至少一部分流入虚拟负载电路。(Provided is a semiconductor device capable of stabilizing an internal voltage. According to one embodiment, a semiconductor device includes: a regulated power supply circuit for generating a first voltage; a charge pump circuit for generating a second voltage different from the first voltage using the first voltage, including a comparison circuit for comparing the second voltage with a reference voltage; and a dummy load circuit controlled to be turned on or off in response to the comparison result signal COUT2 output from the comparison circuit, and the dummy load circuit receives the comparison result signal COUT2 and is turned on for a predetermined period of time, whereby at least a part of the current IDD based on the first voltage flows into the dummy load circuit.)
1. A semiconductor device, comprising:
a stabilized power supply circuit generating a first voltage;
a charge pump circuit generating a second voltage using the first voltage, comparing the second voltage with a reference voltage, and outputting a comparison result signal; and
a dummy load circuit controlled to be in an on state or an off state in response to the comparison result signal;
wherein the stabilizing power supply circuit supplies at least a part of the current based on the first voltage to the dummy load circuit in the semiconductor device in the on state.
2. The semiconductor device of claim 1, further comprising:
a memory circuit operating at the second voltage.
3. The semiconductor device as set forth in claim 1,
wherein the charge pump circuit includes a voltage divider that outputs a divided voltage signal in response to a change in the second voltage, an
Wherein the charge pump circuit compares the second voltage to a reference voltage via a divided level signal.
4. The semiconductor device as set forth in claim 1,
wherein the charge pump circuit further comprises an oscillator that oscillates the clock signal, an
Wherein the dummy load circuit is controlled to be in the on state or the off state upon receiving the clock signal in addition to the comparison result signal.
5. The semiconductor device as set forth in claim 4,
wherein the charge pump circuit further comprises:
a driver controlled to output a driver output signal in response to the clock signal and the comparison result signal, an
A booster stage that generates the second voltage using the first voltage in response to receiving the driver output signal.
6. The semiconductor device as set forth in claim 4,
wherein the dummy load circuit includes:
a counter receiving the comparison result signal and the clock signal, and counting and outputting a dummy control signal to be turned on; and
an inflow transistor receiving the dummy control signal and flowing in a part of the dummy control signal.
7. The semiconductor device as set forth in claim 6,
wherein the counter comprises a plurality of flip-flops and a logic gate circuit.
8. The semiconductor device as set forth in claim 6,
wherein the size of the portion is a substantially constant value in the on-state.
9. The semiconductor device as set forth in claim 8,
wherein the dummy load circuit includes a current source that makes the portion flowing into the inflow transistor substantially constant.
10. The semiconductor device as set forth in claim 8,
wherein the dummy load circuit includes a level shifter applying a constant voltage to a gate of the inflow transistor.
11. The semiconductor device as set forth in claim 4,
wherein the dummy load circuit includes:
a counter receiving the comparison result signal and the clock signal and counting and outputting a plurality of dummy control signals turned on in mutually different periods, an
A plurality of inflow transistors connected in parallel to the counter,
wherein the dummy load circuit is controlled to receive the dummy control signal and to cause the portion to flow in every different time period.
12. The semiconductor device as set forth in claim 11,
wherein the counter comprises a plurality of flip-flops and a plurality of logic circuits connected to each of the flip-flops.
13. The semiconductor device as set forth in claim 11,
wherein the size of the portion is changed stepwise in the on state.
14. The semiconductor device as set forth in claim 1,
wherein the stabilized power supply circuit includes:
a power supply transistor in which an external power supply is connected to one of a source and a drain,
a voltage dividing circuit for a power supply having a variable resistor, one end of which is connected to the other end of the power supply transistor and the other end of which is grounded,
an amplifier circuit, comprising:
a non-inverting input terminal to which a reference voltage for a power supply is input,
an inverting input terminal connected to a terminal for changing the voltage dividing circuit for power supply, an
An output terminal connected to a gate of the power supply transistor;
wherein the predetermined period of time is set based on a response time of the regulated power supply circuit according to a transconductance of the power supply transistor.
15. The semiconductor device as set forth in claim 1,
wherein the dummy load comprises:
a one-shot pulse generating circuit for receiving the comparison result signal and outputting a one-shot pulse signal,
a first transistor receiving the one-shot pulse signal and outputting the dummy control signal to turn on the one-shot pulse signal,
an inflow transistor receiving the dummy control signal and making the portion flow in, an
A second transistor connected to the capacitive element via a resistive element, for changing the dummy control signal to have a time constant.
16. The semiconductor device as set forth in claim 15,
wherein the size of the portion varies to have the time constant in the on state.
17. A semiconductor device, comprising:
a stabilized power supply circuit generating a first voltage;
a charge pump circuit generating a second voltage using the first voltage, comparing the second voltage with a reference voltage, and outputting a comparison result signal; and
a dummy load circuit controlled to be in an on state or an off state in response to the comparison result signal;
wherein the stabilized power supply circuit includes:
a power supply transistor in which an external power supply is connected to one of a source and a drain,
a voltage dividing circuit for a power supply having a variable resistor of which one end is connected to the other end of the power supply transistor and the other end is grounded, an
An amplifier circuit, comprising:
a non-inverting input terminal to which a reference voltage for a power supply is input,
an inverting input terminal connected to a first terminal for changing the voltage dividing circuit for power supply, an
An output terminal connected to a gate of the power supply transistor,
wherein the regulated power supply circuit supplies at least a portion of the current based on the first voltage to the dummy load circuit in the on state.
18. The semiconductor device as set forth in claim 17,
wherein the voltage dividing circuit for a power supply further has a second terminal for changing,
wherein the dummy load circuit includes:
a virtual compare circuit having a non-inverting input terminal to which a virtual reference voltage is input and an inverting input terminal connected to the second terminal for changing the power divider,
a logic circuit that outputs the dummy control signal to be turned on when a dummy comparison result signal output from the dummy comparison circuit and the comparison result signal are received; and
and a flow-in transistor receiving the dummy control signal and flowing the dummy control signal into a portion of the dummy control signal.
19. The semiconductor device as set forth in claim 18,
wherein the virtual reference voltage is set such that the first voltage is within a predetermined detection level.
20. The semiconductor device according to claim 1, further comprising a predetermined circuit,
wherein the first voltage is an internal voltage at which the predetermined circuit operates.
Technical Field
The present invention relates to a semiconductor device, and more particularly, to a semiconductor device including a charge pump.
Background
In recent years, miniaturization of processes has progressed, and the core power supply voltage has also decreased in proportion to the decrease in the breakdown voltage of the device. However, the voltage used at the time of data rewriting in a semiconductor memory device, particularly a flash memory, is still high. Therefore, as the power supply voltage decreases, the step-up ratio (voltage-up ratio) of the charge pump circuit increases, and the operating current tends to increase. In a stabilized power supply circuit that supplies a power supply voltage to a charge pump circuit, an increase in operating current causes an increase in load variation of an output voltage due to the effect of a response rate. The voltage drop in the output voltage causes performance degradation. Furthermore, the voltage rise in the output voltage reduces the breakdown voltage lifetime of the device. Therefore, a technique for suppressing the influence of load fluctuation of the power supply voltage is required.
Disclosure of Invention
The stabilized power supply circuit shown in fig. 14 includes a differential amplifier circuit AMP, a P-channel output MOSFET Q1, and a voltage dividing circuit and a dummy load circuit for forming a feedback signal NFB. A normal load circuit including active circuits such as a CPU and a memory is equivalently represented as a resistive element. The flash memory, the EEPROM memory, and the like included in the normal load circuit require a boosted voltage VPP obtained by boosting an internal voltage VDD in order to write data or erase data. Specifically, the charge pump circuit shown in fig. 14 receives the internal voltage VDD and forms the boosted voltage VPP of the opposite polarity to the internal voltage VDD.
In order to reduce the power consumed by the system LSI, the charge pump circuit is controlled to operate only when the flash memory or the like is in an operation mode in which the boosted voltage VPP of the opposite polarity is required for the write operation or the erase operation to reduce the power consumed by the system LSI. Therefore, when the operation mode of the flash memory or the like is ended, the charge pump circuit is controlled to stop operating even when the system LSI is activated.
As shown in the graph of fig. 15, when the charge pump circuit stops operating, for example, the boosted voltage VPP changes from-12V to 0V. The voltage variation of the boosted voltage VPP acts to change the internal voltage VDD by the parasitic capacitance CST of fig. 14. In particular, in the stabilized power supply circuit as shown in fig. 14, since the internal voltage VDD itself consumes low power, the internal voltage VDD has substantially no current sinking capability, and therefore, there is a possibility that a large jump of the internal voltage VDD occurs.
The dummy load circuit of fig. 14 is also used to prevent the internal voltage VDD from jumping due to a voltage variation of the boosted voltage VPP. That is, at the timing when the boosted voltage VPP is changed, the dummy load current IDD is caused to flow before the boosted voltage VPP is changed, as indicated by a thick line in fig. 15. Even when the load changes in the active state, the internal voltage VDD can be stabilized by using the virtual load circuit voltage VDD.
When the boosted voltage VPP as an output reaches a desired value, the charge pump circuit stops boosting the boosted voltage VPP. When the charge of the boosted voltage VPP is consumed and the boosted voltage VPP drops below a desired value, the charge pump circuit starts boosting again. That is, even when the charge pump circuit is activated, the voltage repeatedly rises and stops. Therefore, even when the charge pump circuit is activated, there is a problem that a load change occurs.
Other objects and novel features will become apparent from the description of the specification and drawings.
According to one embodiment, a semiconductor device includes: a stabilized power supply circuit generating a first voltage; a charge pump circuit generating a second voltage using the first voltage, comparing the second voltage with a reference voltage, and outputting a comparison result signal; and a dummy load circuit controlled to be in an on state or an off state in response to the comparison result signal; wherein the regulated power supply circuit provides at least a portion of the current based on the first voltage to the dummy load circuit in the on-state semiconductor device.
Drawings
Fig. 1 is a configuration diagram showing a semiconductor device according to a first embodiment;
fig. 2 is a configuration diagram showing a stabilized power supply circuit, a charge pump circuit, and a dummy load circuit of the semiconductor device according to the first embodiment;
fig. 3 is a configuration diagram showing a counter of the semiconductor device according to the first embodiment;
fig. 4 is a graph showing an operation waveform of the semiconductor device according to the first embodiment, in which the horizontal axis represents time and the vertical axis represents the intensity of voltage or current;
fig. 5 is a configuration diagram showing a dummy load circuit of the semiconductor device according to the second embodiment;
fig. 6 is a configuration diagram showing a dummy load circuit of the semiconductor device according to the third embodiment;
fig. 7 is a configuration diagram showing a dummy load circuit of the semiconductor device according to the fourth embodiment;
fig. 8 is a configuration diagram showing a counter of a semiconductor device according to a fourth embodiment;
fig. 9 is a graph showing an operation waveform of the semiconductor device according to the fourth embodiment, in which the horizontal axis represents time and the vertical axis represents the intensity of voltage or current;
fig. 10 is a circuit diagram showing a dummy load circuit of the semiconductor device according to the fifth embodiment;
fig. 11 is a graph showing an operation waveform of the semiconductor device according to the fifth embodiment, in which the horizontal axis represents time and the vertical axis represents the intensity of voltage or current;
fig. 12 is a configuration diagram showing a stabilized power supply circuit, a charge pump circuit, and a dummy load circuit of the semiconductor device according to the sixth embodiment;
fig. 13 is a graph showing an operation waveform of the semiconductor device according to the sixth embodiment, in which the horizontal axis represents time and the vertical axis represents the intensity of voltage or current;
fig. 14 is a configuration diagram showing a stabilized power supply circuit; and
fig. 15 is a graph showing an operation waveform of the system LSI in which the horizontal axis represents time and the vertical axis represents the intensity of voltage or current.
Detailed Description
The following description and drawings are omitted or simplified as appropriate for clear explanation. In the drawings, the same elements are denoted by the same reference numerals, and repeated description thereof is omitted as necessary.
A semiconductor device according to a first embodiment will be described. First, the configuration of the semiconductor device according to the first embodiment will be described. Fig. 1 is a configuration diagram showing a semiconductor device 1 according to a first embodiment. As shown in fig. 1, the semiconductor device 1 includes a stabilization power supply circuit 10, a charge pump circuit 20, a dummy load circuit 30, and a memory circuit 40.
The stabilized power supply circuit 10 generates an internal voltage VDD, and supplies the generated internal voltage VDD to a predetermined circuit provided inside the semiconductor device 1. The internal voltage VDD is an operating voltage of a predetermined circuit. The predetermined circuit is, for example, a CPU and a charge pump circuit 20. The stabilized power supply circuit 10 is connected to the charge pump circuit 20 via a conductor L10. The stabilized power supply circuit 10 supplies the internal voltage VDD to the charge pump circuit 20 via the interconnect L10.
The charge pump circuit 20 generates the boosted voltage VPP using the internal voltage VDD. The boosted voltage VPP is a voltage different from the internal voltage VDD. That is, if the boosted voltage VPP is different from the internal voltage VDD, the boosted voltage VPP may be greater than or less than the internal voltage VDD when positive and negative of the boosted voltage VPP are the same as the internal voltage VDD. When the internal voltage VDD is different in positive and negative, the absolute value may be greater or less than the internal voltage VDD. In this specification, the internal voltage VDD is also referred to as a first voltage, and the boosted voltage VPP is also referred to as a second voltage.
The charge pump circuit 20 supplies the generated boosted voltage VPP to the memory circuit 40. Charge pump circuit 20 is connected to memory circuit 40 via conductor L20. Charge pump circuit 20 supplies boosted voltage VPP to memory circuit 40 via conductor L20.
The memory circuit 40 includes a memory cell array 41, a word line driver 42, a source line driver circuit 43, and a readout circuit 44. The word line driver circuit 42 and the source line driver circuit 43 are connected to the wiring L20, respectively. As a result, the word line driver 42 and the source line driver circuit 43 are supplied with the boosted voltage VPP from the charge pump circuit 20. The memory cell array 41 includes a plurality of memory cells arranged in a matrix. When a read operation is performed on the memory cells, a predetermined memory cell is selected by driving the word line driver circuit 42 and the source line driver circuit 43. Then, the sense circuit 44 reads the data of the selected memory cell. The same applies to the case where a write operation is performed on a memory cell. In this manner, the memory circuit 40 operates at the boosted voltage VPP.
The charge pump circuit 20 is connected to the dummy load circuit 30 via a signal line S20. The charge pump circuit 20 outputs the comparison result signal COUT2 to the dummy load circuit 30 via the signal line S20. The dummy load circuit 30 is connected to the wiring L10 via the wiring L11.
Fig. 2 is a configuration diagram showing the stabilized power supply circuit 10, the charge pump circuit 20, and the dummy load circuit 30 of the semiconductor device 1 according to the first embodiment. As shown in fig. 1 and 2, the stabilized power supply circuit 10 includes, for example, an amplifier circuit 11, a voltage divider circuit 12, and a transistor Q10. In order to distinguish it from other voltage dividing circuits and transistors, the voltage dividing circuit 12 is referred to as a power supply voltage dividing circuit 12, and the transistor Q10 is referred to as a power supply transistor Q10.
The amplifier circuit 11 has a non-inverting input terminal, an inverting input terminal, and an output terminal. The voltage dividing circuit 12 includes a variable resistor R10 having one terminal R11 and the other terminal R13. The variable terminal of the variable resistor R10 is represented by R12. The transistor Q10 is, for example, an N-channel transistor, and has a source, a drain, and a gate.
The reference voltage VR1 is input to the non-inverting input terminal of the amplifier circuit 11. The inverting input terminal of the amplifier circuit 11 is connected to the variable terminal R12 of the variable resistor R10 of the voltage divider circuit 12. The output terminal of the amplifier circuit 11 is connected to the gate of the transistor Q10. The amplification circuit 11 receives the divided voltage signal DIV1 from the terminal R12, and outputs an amplified signal AOUT1 to the gate of the transistor Q10. Reference voltage VR1 is also referred to as power supply reference voltage VR 1.
A terminal R11, which is one end of the variable resistor R10 in the voltage dividing circuit 12, is grounded. The variable terminal R12 of the voltage divider circuit 12 is connected to the inverting input terminal of the amplifier circuit 11. A terminal R13 of the variable resistor R10 is connected to the source of the transistor Q10.
The drain of the transistor Q10 is connected to the external power supply VCC. A source of the transistor Q10 is connected to the terminal R13 of the variable resistor R10. A gate of the transistor Q10 is connected to the output terminal of the amplifier circuit 11. Note that the polarity of the transistor Q10 may be reversed, and in this case, the source and drain are reversed.
The stabilized power supply circuit 10 generates and outputs the internal voltage VDD from the external power supply VCC input from the drain of the transistor Q10 and the reference voltage VR1 input to the non-inverting input terminal of the amplifier 11. A line L10 extends from between the source of the transistor Q10 and the terminal R13 of the variable resistor R10 to the charge pump circuit 20. The stabilized power supply circuit 10 outputs the internal voltage VDD to the charge pump circuit 20 via the interconnect L10.
The charge pump circuit 20 includes an oscillator 21, a driver 22, a booster stage 23, a voltage divider circuit 24, and a comparator circuit 25. The voltage dividing circuit 24 includes a variable resistor R20 having one terminal R21 and the other terminal R23. The variable terminal of the variable resistor R20 is represented by R22. The comparator circuit 25 has an output terminal, a non-inverting input terminal, and an inverting input terminal. The oscillator 21, driver 22 and booster stage 23 are connected to the lead L10. The oscillator 21, driver 22 and booster stage 23 are supplied with the internal voltage VDD via an interconnect L10.
The oscillator 21 oscillates the clock signal CK. The oscillator 21 is connected to the driver 22 via a signal line S21. The oscillator 21 outputs the clock signal CK to the driver 22 via the signal line S21. The oscillator 21 is connected to the dummy load circuit 30 via a signal line S25. The oscillator 21 outputs the clock signal CK to the dummy load circuit 30 via the signal line S25.
The driver 22 is connected to the booster stage 23 via a signal line S22. The driver 22 receives the clock signal CK supplied from the oscillator 21, and outputs a driver output signal CKD to the booster stage 23 via the signal line S22.
The booster stage 23 receives the driver output signal CKD and generates the boosted voltage VPP using the internal voltage VDD. The booster stage 23 is connected to the wire L20. A conductor L20 extends from booster stage 23 to memory circuit 40. The booster stage 23 outputs the boosted voltage VPP to the memory circuit 40 via the wire L20.
The terminal R21 of the variable resistor R20 in the voltage divider circuit 24 is grounded. The terminal R23 of the variable resistor R20 is connected to the wiring L20. The variable terminal R22 of the variable resistor R20 is connected to the inverting input terminal of the comparison circuit 25. The voltage divider 24 outputs a divided voltage level signal DIV2 from a terminal R22 in accordance with a change in the boosted voltage VPP output from the terminal R23.
The reference voltage VR2 is input to the non-inverting input terminal of the comparator 25. The inverting input terminal of the comparison circuit 25 is connected to the variable terminal R22 of the variable resistor R20. The output terminal of the comparator 25 is connected to the dummy load circuit 30 via a signal line S23. The output terminal of the comparison circuit 25 is connected to the driver 22 via a signal line S24. The comparator 25 compares the boosted voltage VPP with a reference voltage VR 2. Specifically, the comparator 25 compares the value of the boosted voltage VPP input via the divided level signal DIV2 with the value of the reference voltage VR 2. The comparator 25 outputs the comparison result signal COUT2 to the dummy load circuit 30 via the signal line S23. The signal line S23 corresponds to the signal line S20 in fig. 1.
The comparator 25 outputs the comparison result signal COUT2 to the driver 22 via the signal line S24. The driver 22 receives the clock signal CK and the comparison result signal COUT2 and is controlled to output a driver output signal CKD.
With this configuration, the charge pump circuit 20 generates the boosted voltage VPP using the reference voltage VR2 input to the non-inverting input terminal of the comparator 25 in addition to the internal voltage VDD supplied from the stabilized power supply circuit 10. Charge pump circuit 20 supplies the generated boosted voltage VPP to memory circuit 40 via conductor L20. The charge pump circuit 20 also outputs the comparison result signal COUT2 and the clock signal CK to the dummy load circuit 30. Accordingly, the charge pump circuit 20 controls the dummy load circuit 30.
The dummy load circuit 30 includes a counter 31 and a transistor Q30. The transistor Q30 is, for example, an N-channel transistor, and has a source, a drain, and a gate. To distinguish the transistor Q30 from other transistors, it is also referred to as an inflow transistor Q30.
The counter 31 is connected to the oscillator 21 via a signal line S25. The counter 31 is connected to an output terminal of the comparison circuit 25 via a signal line S23. The counter 31 is connected to the gate of the transistor Q30. The counter 31 receives the comparison result signal COUT2 input via the signal line S23 and the clock signal CK input via the signal line S25, and outputs the dummy control signal DCTL3 to the transistor Q30. The counter 31 counts a predetermined period of time, for example, and outputs an H level or an L level to the dummy control signal DCTL 3. The H level is a signal to be turned on, and the L level is a signal to be turned off, for example. As described above, the dummy control signal DCTL3 is a signal for turning on or off the transistor Q30. Accordingly, the counter 31 controls the gate of the transistor Q30 to turn on or off the transistor Q30.
The source of transistor Q30 is connected to ground. The drain of the transistor Q30 is connected to a wiring L10 via a wiring L11, and a wiring L10 connects the stable power supply circuit 10 and the charge pump circuit 20. The transistor Q30 receives the dummy control signal DCTL3 output from the counter 31 and is controlled by the dummy control signal DCTL3 so that at least a part of the current IDD based on the internal voltage VDD flows. For example, when the gate of the transistor Q30 is turned on, conduction is established between the drain and the source, and at least a part of the current IDD based on the internal voltage VDD flows from the wiring L11.
With this configuration, the dummy load circuit 30 receives the comparison result signal COUT2 output from the comparison circuit 25, and is controlled to be in an on state or an off state. Then, in response to the comparison result signal COUT2, the dummy load circuit 30 is turned on for a predetermined period of time. As a result, at least a part of the current IDD based on the internal voltage VDD flows into the dummy load circuit 30. Specifically, the dummy load circuit 30 is controlled to be turned on or off in response to the clock signal CK in addition to the comparison result signal COUT2, and a part of the current IDD flows into the transistor Q30.
Fig. 3 is a configuration diagram showing the counter 31 of the semiconductor device 1 according to the first embodiment. As shown in fig. 3, the counter 31 includes a plurality of (n) flip-flops (F/F)311 to 31n and a logic gate circuit G30. The clock terminal of each F/F is connected to the signal line S25. As a result, the clock signal CK is input to the clock terminal of each F/F via the signal line S25. The R terminal of each F/F is connected to the signal line S23. The D terminal of F/F311 is connected to the signal line S23. The Q terminal of F/F311 is connected to the D terminal of F/F312. The Q terminal of F/F312 is connected to the D terminal of F/F313 (not shown). Hereinafter, the Q terminal of each (n-1) th F/F is connected to the D terminal of the nth F/F. The Q terminal of the nth F/F is connected to one input terminal of the logic gate circuit G30. The other input terminal of the logic gate circuit G30 is connected to the signal line S23. The output terminal of the logic gate circuit G30 is connected to the gate of the transistor Q30. With this configuration, the counter 31 has a function of counting a predetermined period of time. Accordingly, the counter 31 receives the comparison result signal COUT2 and the clock signal CK, counts the comparison result signal DCTL3 and the clock signal CK for a predetermined period of time with respect to the gate of the transistor Q30, and outputs the H level or the L level to the dummy control signal DCTL 3.
Next, the operation of the semiconductor device 1 will be described. Fig. 4 is a graph showing an operation waveform of the semiconductor device 1 according to the first embodiment, in which the horizontal axis represents time and the vertical axis represents the intensity of voltage or current. For example, the oscillator 21 outputs the clock signal CK at regular intervals. The driver 22 outputs a driver output signal CKD at a predetermined timing based on the clock signal CK.
The booster stage 23 receives a driver output signal CKD from the driver 22. The booster stage 23 receives the driver output signal CKD and outputs the boosted voltage VPP using the internal voltage VDD. Here, during the operation of boosting the booster stage 23, the load current IDD is generated in the wire L10. As a result, the internal voltage VDD decreases. Therefore, the voltage divider 12 decreases the divided voltage level signal DIV1 according to the decrease of the internal voltage VDD.
Therefore, the amplifier circuit 11 senses that the divided voltage level signal DIV1 is lower than the reference voltage VR1 and increases the amplified signal AOUT 1. In the transistor Q10, gm rises as the amplified signal AOUT1 connected to the gate rises. The transistor Q10 compensates for the load current IDD connected to the source and suppresses the decrease in the internal voltage VDD.
Next, when the boosted voltage VPP continues to rise, the voltage divider 24 raises the divided voltage level signal DIV2 according to the rise of the boosted voltage VPP. The comparator 25 detects that the divided voltage level signal DIV2 becomes higher than the reference voltage VR2, and outputs the H level to the comparison result signal COUT 2. The driver 22 stops the oscillation of the driver output signal CKD in response to the comparison result signal COUT 2.
The booster stage 23 stops boosting in response to the stop of the oscillation of the driver output signal CKD. Here, the load current IDD is abruptly reduced in response to the stop of the boosting of the booster stage 23. Since the stabilized power supply circuit 10 cannot respond to a sudden change in load and gm of the transistor Q10 remains high, the internal voltage VDD rises as indicated by the broken line VDD in fig. 4.
However, when the counter 31 receives the enable signal of the comparison result signal COUT2, the clock signal CK counts the response rate time of the stable power supply circuit 10. Then, the counter 31 outputs the H level to the dummy control signal DCTL3 for a predetermined period. That is, the counter 31 counts and outputs the dummy control signal DCTL3 to be turned on for a predetermined period of time. The transistor Q30 allows at least a part of the current IDD based on the internal voltage VDD to flow in the H level period of the dummy control signal DCTL3 input to the gate. For example, in the on state, the magnitude of the current IDD flowing in is substantially constant. A substantially constant value is a value that can be considered constant within the scope of the measurement technique. As a result, fluctuations in the internal voltage VDD can be suppressed. The predetermined period of time is set according to the transconductance gm of the transistor Q10 in the stabilized power supply circuit 10 based on the response time of the stabilized power supply circuit 10. That is, the rate of change of the amplification signal AOUT1 is set based on the rate of change of the transconductance gm of the transistor Q10.
Next, the effects of the present embodiment will be described. The semiconductor device 1 of the present embodiment is controlled so that at least a part of the load current IDD flows into the dummy load circuit 30 even if the load current IDD fluctuates due to repetition of the operation and stop of the booster stage of the charge pump circuit 20 in the activated state. As a result, fluctuations in the internal voltage VDD can be suppressed.
The dummy load circuit 30 receives the comparison result signal COUT2 output from the comparator 25. Therefore, it is possible to quickly respond to the change in the boosted voltage VPP. Therefore, the fluctuation of the internal voltage VDD can be quickly suppressed.
The charge pump circuit 20 has a configuration capable of coping with the boosting of the positive electrode or the negative electrode. As a result, the versatility of the semiconductor device 1 can be improved. When applied to a semiconductor memory device including the memory circuit 40, since the boosted voltage VPP generated from the internal voltage VDD is also stably generated, operations such as reading and writing can be stabilized.
Next, a semiconductor device according to embodiment 2 will be described. The semiconductor device of the second embodiment differs from the semiconductor device 1 of the first embodiment in the configuration of the dummy load circuit 30 a. Fig. 5 is a configuration diagram showing a dummy load circuit 30a of the semiconductor device according to the second embodiment.
As shown in fig. 5, the dummy load circuit 30a includes a counter 31, a transistor Q30, and a current source I30. One terminal of the current source I30 is connected to ground, and the other terminal is connected to the source of the transistor Q30. That is, the current source I30 is disposed between the source of the transistor Q30 and ground. The current source I30 sets the current IDD flowing into the transistor Q30 to a constant value. The other configurations are the same as those of the first embodiment.
The counter 31 receives the enable signal of the comparison result signal COUT2 and counts the clock signal CK for the response time of the stable power supply circuit 10. Then, the counter 31 outputs the H level to the dummy control signal DCTL3 for a predetermined period of time. The transistor Q30 is turned on during the H level period of the dummy control signal DCTL 3. Accordingly, the transistor Q30 controls the gate so that at least a part of the current IDD based on the internal voltage VDD flows in. By supplying the stabilization current from the current source I30, the variation of the internal voltage VDD can be suppressed.
In the semiconductor device of the second embodiment, since the dummy load circuit 30a uses the current source I30, the current IDD flowing into the transistor Q30 can be kept constant. This makes it possible to suppress fluctuations in the internal voltage VDD with high accuracy. Other effects are included in the description of the first embodiment.
Next, a semiconductor device according to a third embodiment will be described. The semiconductor device of the third embodiment is different from those of the first and second embodiments in the configuration of the dummy load circuit 30 b. Fig. 6 is a configuration diagram showing a dummy load circuit of the semiconductor device according to the third embodiment.
As shown in fig. 6, the dummy load circuit 30b includes a counter 31, a level shifter 32, and a transistor Q30. The level shifter 32 is disposed between the counter 31 and the gate of the transistor Q30. That is, the input terminal of the level shifter 32 is connected to the counter 31, and the output terminal of the level shifter 32 is connected to the gate of the transistor Q30.
The counter 31 receives the enable signal of the comparison result signal COUT2, counts the clock signal CK for the response time of the stable power supply circuit 10, and outputs the clock signal CK to the counter output signal DCTLC for a predetermined period of time. The counter 31 outputs a counter output signal DCTLC to the level shifter 32. The level shifter 32 converts the level of the counter output signal DCTLC of the H level by using the constant voltage VR 3. The level shifter 32 outputs the dummy control signal DCTL3 to the transistor Q30. As a result, the level shifter 32 applies a constant voltage to the gate of the transistor Q30. The transistor Q30 is turned on during the H level of the dummy control signal DCTL3 connected to the gate. As a result, the current IDD flowing into the transistor Q30 becomes constant. Therefore, the internal voltage VDD can be stabilized.
In the semiconductor device according to the third embodiment, since the level shifter 32 using the constant voltage power supply VR3 as a power supply is used, the current IDD based on the internal voltage VDD can be kept constant, and variations in the internal voltage VDD can be suppressed with high accuracy. Other effects are described in the first embodiment and the second embodiment.
Next, a semiconductor device according to a fourth embodiment will be described. The semiconductor device of the fourth embodiment is different from those of the first to third embodiments in the configuration of the dummy load circuit 30 c. Fig. 7 is a configuration diagram showing a dummy load circuit of the semiconductor device according to the fourth embodiment.
As shown in fig. 7, the dummy load circuit 30c includes a counter 31c and a plurality of (n) transistors Q31 to Q3 n. The gate of each transistor is connected to the counter 31 c. The drain of each transistor is connected to a wiring L10 via a wiring L11. The source of each transistor is connected to ground. As described above, the plurality of transistors Q31 to Q3n are connected in parallel to the counter 31 c.
Fig. 8 is a configuration diagram showing a counter 31c of a semiconductor device according to a fourth embodiment. As shown in fig. 8, the counter 31c includes a plurality of (n) F/fs 311 to 31n and n logic gate circuits G31 to G3 n. The clock terminal of each F/F is connected to the signal line S25. As a result, the clock signal CK is input to the clock terminal of each F/F via the signal line S25. The R terminal of each F/F is connected to the signal line S23.
The D terminal of F/F311 is connected to the signal line S23. The Q terminal of F/F311 is connected to the D terminal of F/F312 and one terminal of logic gate circuit G31. The Q terminal of F/F312 is connected to the D terminal (not shown) of F/F313 and to one terminal of logic gate G32. Hereinafter, the Q terminal of each (n-1) th F/F is connected to the D terminal of the nth F/F, and also to one terminal of a logic gate circuit Q3 n. The Q terminal of the nth F/F is connected to one terminal of logic gate circuit G3 n. In this way, the logic gate circuits G31 to G3n are connected to the logic gate circuits F/F311 to 31 n. The other terminals of the logic gate circuits G31 to G3n are connected to the signal line S23.
The counter 31c receives the comparison result signal COUT2 and the clock signal CK, counts the comparison result signals DCTL31 through 3n and the clock signal CK by different times for the plurality of dummy control signals DCTL31 through 3n, and outputs the counted comparison result signals DCTL31 through 3n and the clock signal CK to the plurality of dummy control signals COUT 2. For example, the counter 31c counts and outputs the H-level dummy control signal DCTL32 output to the transistor Q32 for a period longer than the H-level dummy control signal DCTL31 output to the transistor Q31. As a result, the dummy load circuit 30c receives the dummy control signals DCTL31 through 3n and controls the current IDD to flow in the dummy control signals DCTL31 through 3n in different periods.
Fig. 9 is a graph showing an operation waveform of the semiconductor device according to the fourth embodiment, in which the horizontal axis shows time and the vertical axis shows the intensity of voltage or current. As shown in fig. 9, the charge pump circuit 20 outputs the boosted voltage VPP by the operations of the driver 22 and the booster stage 23 in the charge pump circuit 20, and therefore, the stabilizing power supply circuit 10 compensates the load current IDD to suppress the decrease of the internal voltage VDD similarly to the first embodiment.
When the boosted voltage VPP rises above the predetermined voltage, the comparator 25 in the charge pump circuit 20 stops boosting the booster stage 23, whereby the load current IDD suddenly decreases and the internal voltage VDD rises as indicated by VDD of a dotted line in fig. 9, similar to the first embodiment.
In the present embodiment, the plurality of dummy control signals DCTL31 to 3n are output at the H level for a predetermined period of time by using the outputs of the plurality of F/fs 311 to 31 n. The H level periods of the dummy control signals DCTL31 to 3n are different. For example, the counter 31c counts and outputs the H period of the dummy control signal DCTL32 output to the transistor Q32 for a period longer than the H period of the dummy control signal DCTL31 output to the transistor Q31. Accordingly, the H level of each of the dummy control signals DCTL31 through 3n is transited to the L level in a stepwise manner. Each of the transistors Q31 to Q3n feeds a current IDD based on the internal voltage VDD corresponding to the H level period of each dummy control signal DCTL31 to 3 n. Therefore, the current IDD flowing into the dummy load circuit 30c varies in a stepwise manner. That is, in the on state of the dummy load circuit 30c, the magnitude of the current IDD flowing into the dummy load circuit 30c is changed stepwise.
In the semiconductor device of the fourth embodiment, since the transistors Q31 to 3n are turned off in stages, the current IDD can be changed in stages. As a result, the rate of change of gm of the transistor Q10 can be made to follow the rate of change of the amplification signal AOUT 1. Therefore, the fluctuation of the internal voltage VDD can be suppressed with high accuracy. Other effects are included in the description of the first to third embodiments.
Next, a semiconductor device according to a fifth embodiment will be described. The semiconductor device of the fifth embodiment is different from those of the first to fourth embodiments in the configuration of the dummy load circuit 30 d. Fig. 10 is a circuit diagram illustrating a dummy load circuit 30d of the semiconductor device according to the fifth embodiment.
As shown in fig. 10, the virtual load circuit 30d includes a one-shot (one-shot) pulse generator 33, transistors Q30, Q33, and Q34, a resistance element R30, and a capacitance element C30. The one-shot pulse generating circuit 33 is a circuit for generating one pulse. The one-shot pulse generating circuit 33 includes, for example, a delay circuit and a NAND logic circuit. The one-shot pulse generator 33 receives the comparison result signal COUT2 and outputs a one-shot pulse signal DCTLD. More specifically, the comparison result signal COUT2 is input to the input terminal of the one-shot pulse generation circuit 33, and the one-shot pulse signal DCTLD is output from the output terminal of the one-shot pulse generation circuit 33.
The transistor Q30 is, for example, an N-channel transistor. The source of transistor Q30 is connected to ground. The drain of the transistor Q30 is connected to a wiring L10 that connects the stable power supply circuit 10 and the charge pump circuit 20 via a wiring L11. A gate of the transistor Q30 is connected to one end of the capacitor C30 and one end of the resistor R30. The transistor Q30 receives the dummy control signal DCTL3 and causes a current IDD to flow in the dummy control signal DCTL 3.
The transistor Q33 is, for example, a P-channel transistor. A source of the transistor Q33 is connected to the wiring L11. The drain of the transistor Q33 is connected to one end of the resistance element R30. The gate of the transistor Q33 is connected to the output terminal of the one-shot pulse generating circuit 33. The transistor Q33 receives the one-shot pulse signal DCTLD and outputs an H-level signal for turning on the dummy load circuit 30d to the dummy control signal DCTL 3.
The transistor Q34 is, for example, an N-channel transistor. The drain of the transistor Q34 is connected to the other end of the resistance element R30. The source of transistor Q34 is connected to ground. The gate of the transistor Q34 is also connected to the output terminal of the one-shot pulse generating circuit 33.
One end of the resistance element R30 is connected to the drain of the transistor Q33, and the other end of the resistance element R30 is connected to the drain of the transistor Q34. One end of the capacitor C30 is connected to the gate of the transistor Q30, one end of the resistor R30, and the drain of the transistor Q33. The other end of the capacitor C30 is grounded. The transistor Q34 is connected to the capacitive element C30 via the resistive element R30, and the dummy control signal DCTL3 is reduced to have a time constant.
Fig. 11 is a graph showing an operation waveform of the semiconductor device according to the fifth embodiment, in which the horizontal axis represents time and the vertical axis represents the intensity of voltage or current. As shown in fig. 11, the charge pump circuit 20 outputs the boosted voltage VPP by the operations of the driver 22 and the booster stage 23 in the charge pump circuit 20, and therefore, the stabilizing power supply circuit 10 compensates the load current IDD to suppress the decrease of the internal voltage VDD similarly to the first embodiment.
When the boosted voltage VPP rises above the predetermined voltage, the comparator 25 in the charge pump circuit 20 stops boosting the booster stage 23, whereby the load current IDD rapidly decreases and the internal voltage VDD rises as it is, similarly to the first embodiment.
The one-shot pulse generator 33 receives the comparison result signal COUT2 and outputs an L-level signal to the one-shot pulse signal DCTLD for a short time corresponding to a single shot. The transistor Q33 outputs the dummy control signal DCTL3 at the H level during the L level period of the one-shot pulse signal DCTLD connected to the gate. Then, for example, the capacitor C30 is charged at the H level. During the H level period of the dummy control signal DCTL3, the transistor Q30 is turned on, and a current IDD based on the internal voltage VDD flows in. As a result, fluctuations in the internal voltage VDD can be suppressed.
When the one-shot pulse signal DCTLD transitions to the H level, the transistor Q34 turns on and starts to pull out the charged dummy control signal DCTL 3. The resistance element R30 and the capacitance element C30 change the dummy control signal DCTL3 to the L level by a set time constant to correspond to the response time of the stable power supply circuit 10.
In the fifth embodiment, the gate potential of the transistor Q30 decreases with a time constant. Therefore, the current IDD based on the internal voltage VDD changes in an analog manner. That is, in the on state of the dummy load circuit 30d, the magnitude of the current IDD fluctuates to have a time constant. This makes it possible to follow the rate of change of gm of the transistor Q10 with respect to the rate of change of the amplified signal AOUT1, and to suppress variation of the internal voltage VDD with high accuracy.
Next, a semiconductor device according to a sixth embodiment will be described. The semiconductor device of the sixth embodiment is different from those of the first to fifth embodiments in the configuration of the steady power supply circuit 10e and the dummy load circuit 30 e. Fig. 12 is a circuit diagram showing the stabilization power supply circuit 10e, the charge pump circuit 20, and the dummy load circuit 30e of the semiconductor device 6 according to the sixth embodiment.
As shown in fig. 12, the stabilized power supply circuit 10e of the sixth embodiment includes an amplifier circuit 11, a transistor Q10, and a voltage divider circuit 12 e. The structures of the amplifier 11 and the transistor Q10 in the stabilized power supply circuit 10e are the same as those in the first embodiment. The configuration of the terminal R11, the terminal R12, and the terminal R13 of the voltage divider circuit 12e is the same as that of the first embodiment. However, the voltage dividing circuit 12e also has a variable terminal R14. The voltage dividing circuit 12e is also referred to as a power supply voltage dividing circuit 12 e.
The charge pump circuit 20 includes an oscillator 21, a driver 22, a booster stage 23, a voltage divider circuit 24, and a comparison circuit 25, which are the same as those in the first embodiment. The clock signal CK is different from that of the first embodiment in that the signal line S25 connected from the oscillator 21 to the virtual load circuit 30e is not provided, and the clock signal CK is not output to the virtual load circuit 30 e.
The dummy load circuit 30e includes a comparator 51, an AND logic circuit AG30, AND a transistor Q30.
The comparator circuit 51 has a non-inverting input terminal, an inverting input terminal, and an output terminal. The reference voltage VR5 is input to the non-inverting input terminal of the comparator 51. An inverting input terminal of the comparison circuit 51 is connected to the variable terminal R14 of the variable resistor R10 of the voltage dividing circuit 12 e. As a result, the divided voltage level signal DIV5 is input to the inverting input terminal of the comparator 51. An output terminal of the comparator 51 is connected to one input terminal of an AND logic circuit AG 30. The comparator 51 compares the reference voltage VR5 with the divided voltage level signal DIV 5. The comparator 51 outputs a comparison result signal COUT5 to one input terminal of the AND logic circuit AG 30. The comparison circuit 51 is also referred to as a dummy comparison circuit 51.
The other input terminal of the AND logic circuit AG30 is connected to the output terminal of the comparator 25 via a signal line S23. The comparison result signal COUT2 is input to the other input terminal of the AND logic circuit AG30 via the signal line S23. An output terminal of the AND logic circuit AG30 is connected to the gate of the transistor Q30. The AND logic circuit AG30 receives the comparison result signal COUT2 AND the comparison result signal COUT5, AND outputs a dummy control signal DCTL3 to the gate of the transistor Q30. The comparison result signal COUT5 is based on the divided voltage level signal DIV 5.
The transistor Q30 receives the dummy control signal DCTL3 and causes a current IDD based on the internal voltage VDD to flow in the dummy control signal DCTL 3.
Fig. 13 is a graph showing an operation waveform of the semiconductor device according to the sixth embodiment, in which the horizontal axis represents time and the vertical axis represents the intensity of voltage or current. As shown in fig. 13, the charge pump circuit 20 outputs the boosted voltage VPP by the operations of the driver 22 and the booster stage 23 in the charge pump circuit 20, and therefore, the stabilizing power supply circuit 10 compensates the load current IDD to suppress the decrease of the internal voltage VDD similarly to the first embodiment.
When the boosted voltage VPP rises above the predetermined voltage, the comparator 25 in the charge pump circuit 20 stops boosting the booster stage 23, similarly to the first embodiment, whereby the load current IDD rapidly decreases and the internal voltage VDD rises as it is.
In the present embodiment, when the boosted voltage VPP continues to rise, the voltage divider 24 raises the divided voltage level signal DIV2 according to the rise of the boosted voltage VPP. The comparator 25 detects that the divided voltage stop signal DIV2 becomes higher than the reference voltage VR2, and outputs the H level to the comparison result signal COUT 2.
The voltage divider 12 raises the divided level signal DIV5 according to the rise of the internal voltage VDD. The comparator 51 detects that the divided voltage level signal DIV5 becomes higher than the reference voltage VR5, and outputs the H level to the comparison result signal COUT 5. The transition of the comparison result signal COUT5 to the H level is different from the transition of the comparison result signal COUT2 to the H level.
The AND logic circuit AG30 outputs the H level to the dummy control signal DCTL3 according to the H level of the comparison result signal COUT2 AND the H level of the comparison result signal COUT 5. The transistor Q30 is turned on during the H level of the dummy control signal DCTL3 connected to the gate, and a current IDD based on the internal voltage VDD flows.
When the internal voltage VDD becomes the detection level, the reference voltage VR5 is set such that the comparison result signal COUT5 becomes the H level. As a result, the internal voltage VDD can be set within a predetermined detection level range. The detection level is then set to less than the absolute maximum rating. In this way, variations in the internal voltage VDD larger than the absolute maximum rated value can be suppressed.
In the present embodiment, by setting the detection level of the internal voltage VDD lower than the absolute maximum rated value, an increase in the internal voltage VDD can be suppressed with high accuracy.
