Circuit switching device of domestic chip
阅读说明：本技术 一种国产化芯片的电路转接装置 (Circuit switching device of domestic chip ) 是由 孔学成 杜广湘 杜玉甫 江泽鑫 钟柯佳 苏文川 侯东 杨东鑫 邓伟豪 于 2019-11-25 设计创作，主要内容包括：本发明公开了一种国产化芯片的电路转接装置,包括电路板,核心板对接端,所述核心板对接端设置于电路板上层,可用于连接核心板处理器,CN1座子和CN2座子,所述CN1座子和CN1座子设置于电路板下层,位于核心板对接端两侧,用于将核心板对接端引脚转化为针座引脚,针座引脚,所述针座引脚设置于电路板下层,可用于连接外部底板,核心板对接端分别与CN1座子和CN2座子连接,针座引脚分别与CN1座子和CN2座子连接。本发明通过设置CN1座子和CN2座子将核心板对接端转化为针座引脚,使得本装置将国产芯片与原有底板的连接替换了原有的核心板,使得产品资料重复利用率提高,减少了成本,也使得开发周期缩短,无需开发相同尺寸的芯片。(The invention discloses a circuit switching device of a domestic chip, which comprises a circuit board and a core board butt joint end, wherein the core board butt joint end is arranged on the upper layer of the circuit board and can be used for connecting a core board processor, a CN1 seat and a CN2 seat, the CN1 seat and the CN1 seat are arranged on the lower layer of the circuit board and are positioned at two sides of the butt joint end of the core board and used for converting pins of the core board butt joint end into pins of a pin seat, the pins of the pin seat are arranged on the lower layer of the circuit board and can be used for connecting an external bottom plate, the butt joint end of the core board is respectively connected with the CN1 seat and the CN2 seat, and the pins of the pin seat are respectively connected with the CN1 seat and the. According to the invention, the CN1 seat and the CN2 seat are arranged to convert the butt joint end of the core board into the pin of the pin seat, so that the device replaces the original core board with the connection of a domestic chip and the original bottom board, the repeated utilization rate of product data is improved, the cost is reduced, the development period is shortened, and chips with the same size do not need to be developed.)
1. A circuit switching device of a home-made chip is characterized by comprising: a circuit board is provided with a plurality of circuit boards,
the core board butt joint end is arranged on the upper layer of the circuit board and can be used for connecting a core board processor;
the CN1 seat and the CN2 seat, the CN1 seat and the CN1 seat are arranged on the lower layer of the circuit board and positioned on two sides of the butt joint end of the core board, and are used for converting the pins of the butt joint end of the core board into pins of a pin seat;
the pin of the needle seat is arranged on the lower layer of the circuit board and can be used for connecting an external bottom plate;
the butt joint end of the core plate is respectively connected with the CN1 seat and the CN2 seat, and the pin of the needle seat is respectively connected with the CN1 seat and the CN2 seat.
2. The circuit switching device of a localization chip according to claim 1, wherein said CN1 socket has pins No. 1 to No. 60;
the CN2 seat is provided with a pin from I to sixty.
3. The circuit switching device of a homemade chip as claimed in claim 2, wherein said core board docking terminal comprises: USB function pin end, UART function pin end, IIC function pin end, SPI function pin end, RGMII function pin end, MMC function pin end, GPIO function pin end.
4. The circuit switching device of a homemade chip as claimed in claim 3, wherein said core board docking end comprises: USB functional pin terminals: HOST2_ DM pin terminal, HOST2_ DP pin terminal, OTG _ DR pin terminal, OTG _ ID pin terminal, VDD _ SV _ SYS pin terminal, OTG _ DM pin terminal, OTG _ DP pin terminal, HOST1_ DM pin terminal, HOST1_ DP pin terminal;
UART function pin terminal: a UART2_ RXD pin terminal, a UART2_ TXD pin terminal, a UART1_ RXD pin terminal, a UART1_ TXD pin terminal, a UART3_ RXD/GPIO7_ A7 pin terminal, a UART3_ TXD/GPIO7_ B0 pin terminal, a UART4_ TXD/SPI0_ TXD pin terminal, a UART4_ RXD/SPIO _ RXD pin terminal, a UARTO _ RXD pin terminal, a UARTD _ TXD pin terminal;
IIC function pin terminal: I2C1_ SCL _ Sensor pin terminal, I2C1_ SDA _ Sensor pin terminal;
SPI functional pin terminals: an SPI1_ TXD/GPIO7_ B7 pin terminal, an SPI1_ TXD/GPIO7_ B6 pin terminal, an SPI1_ CSNO/GPIO7_ B5 pin terminal, an SPI1_ CLK/GPIO7_ B4 pin terminal, and an SPIO _ CSN 0pin terminal;
RGMII functional pin end: a UARTO _ CTS pin terminal, a UARTO _ RTS pin terminal, a MAC _ MDC pin terminal, a MAC _ MDIO pin terminal, a MAC _ TXD1 pin terminal, a MAC _ TXD 0pin terminal, a MAC _ TXEN pin terminal, a MAC _ RXDV pin terminal, a MAC _ RXD 0pin terminal, a MAC _ RXD1 pin terminal and a MAC _ CLK pin terminal;
MMC function pin end: an SDMMC _ CMD pin end, an SDMMC _ D2 pin end, an SDMMC _ D3 pin end, an SDMMC _ DET pin end, an SDMMC _ CLK pin end, an SDMMC _ D1 pin end, an SDMMC _ D0 pin end and a VDD _3V3_ RTC pin end;
GPIO function pin terminal: a GPIO7_ C5 pin terminal, a UART3_ CTS/GPIO7_ B1 pin terminal, a GPIO5_ C1 pin terminal, a GPIO4_ D7 pin terminal, a GPIO4_ D6 pin terminal, a SDICO _ D3/GPIO4_ C7 pin terminal, a SDICO _ BKPPR/GPIO 4_ D5 pin terminal, a SDICO _ CLK/GPIO4_ D1 pin terminal, a SDICO _ WRPRT/GPIO4_ D3 pin terminal, a SDICO _ DET/GPIO4_ D2 pin terminal, a SDICO _ PWR/GPIO4_ D4 pin terminal, a SDIC _ D1/GPIO4_ C5 pin terminal, a SDIC _ D2/4 _ C6 pin terminal, a SDIC _ CMD 6/6 pin terminal, and a SDIO _ D6/6 pin terminal.
5. The apparatus of claim 4, wherein the pin # 1 is connected to HOST2_ DM pin terminal, the pin # 3 is connected to HOST2_ DP pin terminal, the pin # 5 is connected to OTG _ DR pin terminal, the pin # 7 is connected to UART2_ RXD pin terminal, the pin # 9 is connected to UART2_ TXD pin terminal, the pin # 13 is connected to SPI1_ TXD/GPIO7_ B7 pin terminal, the pin # 15 is connected to SPI1_ TXD/GPIO7_ B6 pin terminal, the pin # 19 is connected to I2C1_ SCL _ Sensor terminal, the pin # 21 is connected to I2C1_ SDA _ Sensor pin terminal, the pin # 25 is connected to GPIO5 pin terminal, the pin # 27 is connected to OTG _ ID pin 68692, the pin # 11 _ CTS _ NO _ 3631 is connected to SPI 6319 pin # 11 _ CTS _ NO _ 6319, the pin No. 33 is connected with a pin terminal of GPIO5_ C1, the pin No. 37 is connected with a pin terminal of VDD _3V3_ RTC, the pin No. 39 is connected with a pin terminal of SPI1_ CLK/GPIO7_ B4, the pin No. 43 is connected with a pin terminal of UART3_ RXD/GPIO7_ A7, the pin No. 45 is connected with a pin terminal of UART3_ TXD/GPIO7_ B0, the pin No. 53, pin No. 55, pin No. 57, pin No. 59 are connected with a pin terminal of VDD _ SV _ SYS, the pin No. 6 is connected with a pin terminal of OTG _ DM, the pin No. 8 is connected with a pin terminal of OTG _ DP, the pin No. 12 is connected with a pin terminal of HOST1_ DM, the pin No. 14 is connected with a pin terminal of HOST 38 _ DP, the pin No. 30 is connected with a pin terminal of UARTO _ RTO _ 4, the pin No. 32 is connected with a pin terminal of UAO _ CTS 4, and the pin 4 is connected with a pin terminal of RTO _ CTS 3_ CTS, pin number 40 is connected to the MAC _ MDC pin terminal, pin number 42 is connected to the MAC _ MDIO pin terminal, pin number 44 is connected to the MAC _ TXD1 pin terminal, pin number 46 is connected to the MAC _ TXD 0pin terminal, pin number 48 is connected to the MAC _ TXEN pin terminal, pin number 50 is connected to the MAC _ RXDV pin terminal, pin number 52 is connected to the MAC _ RXD 0pin terminal, pin number 54 is connected to the MAC _ RXD1 pin terminal, pin number 58 is connected to the MAC _ CLK pin terminal,
the No. 11 pin, the No. 17 pin, the No. 23 pin, the No. 35 pin, the No. 41 pin, the No. 47 pin, the No. 49 pin, the No. 51 pin, the No. 2 pin, the No. 4 pin, the No. 10 pin, the No. 16 pin, the No. 28 pin, the No. 38 pin, the No. 56 pin and the No. 60 pin are grounded,
no. 18 pin, No. 20 pin, No. 22 pin, No. 24 pin and No. 26 pin are not connected.
6. A circuit switching device of a domestic chip according to claim 4, wherein said sixty-numbered pin is connected to SDMMC _ CMD pin terminal, said fifty-eight-numbered pin is connected to SDMMC _ D2 pin terminal, said fifty-six-numbered pin is connected to SDMMC _ D3 pin terminal, said fifty-four-numbered pin is connected to SDMMC _ DET pin terminal, said fifty-numbered pin is connected to SDMMC _ CLK pin terminal, said forty-six-numbered pin is connected to SDMMC _ D1 pin terminal, said forty-numbered pin is connected to SDMMC _ D0 pin terminal, said forty-numbered pin is connected to SDICO _ D3/GPIO4_ C7 pin terminal, said thirty-eight-numbered pin is connected to SDICO _ BKPPWR25 _ D5 pin terminal, said thirty-four-numbered pin is connected to SDICO _ CLK/GPIO4_ D1 pin terminal, said thirty-numbered pin is connected to PRSDICO _ BKPLICO _ D4 _ D38 3 pin, said SDIC _ DET _ D3884 terminal and SDMC _ DET _ D2 terminal, the twenty-sixth pin is connected with a SDICO _ PWR/GPIO4_ D4 pin end, the fifty-nine pin is connected with the SPIO _ CSN 0pin end, the fifty-seven pin is connected with the UARTO _ RXD pin end, the fifty-five pin is connected with a UARTD _ TXD pin end, the fifty-one pin is connected with a SDOD _ D1/GPIO4_ C5 pin end, the forty-nine pin is connected with the SDIOD _ D2/GPIO4_ C6 pin end, the forty-seven pin is connected with the SDIO _ CMD/GPIO4_ D0 pin end, the forty-five pin is connected with the SDIOD _ D0/GPIO4_ C4 pin end, the forty-first pin is connected with a UART1_ RXD pin end, the thirty-ninth pin is connected with a UART1_ TXD pin end, the thirty-five pin is connected with the UART4_ TXD/SPI0_ TXD pin terminal, the thirty-third pin and the UART4_ RXD/SPIO _ RXD pin terminal,
the fifty-two pin, the forty-eight pin, the forty-two pin, the thirty-six pin, the thirty-two pin, the twenty-four pin, the twenty-two pin, the four pin, the two pin, the fifty-three pin, the forty-three pin, the thirty-seven pin, the thirty-eleven pin, the twenty-three pin, the twenty-one pin, the three pin and the one pin are grounded,
and the No. twenty pin, the No. eighteen pin, the No. sixteen pin, the No. fourteen pin, the No. twelve pin, the No. ten pin, the No. eight pin, the No. six pin, the No. nineteen pin, the No. seventeen pin, the No. fifteen pin, the No. thirteen pin, the No. eleven pin, the No. nine pin, the No. seven pin and the No. five pin are not connected.
7. The circuit switching device of a localization chip as claimed in claim 2, wherein said pin header pins comprise: USB function pin, UART function pin, IIC function pin, SPI function pin, MII function pin, GPIO function pin.
8. The circuit switching device of a localization chip according to claim 7, wherein said pin of said header specifically comprises:
USB function pin: a USB _ HOST2_ N pin, a USB _ HOST2_ P pin, a USB _ OTG _ DRV pin, a USB _ OTG _ ID pin, a VCC _5V pin, a USB _ OTG _ DM pin, a USB _ OTG _ DP pin, a USB _ HOST1_ DM pin, and a USB _ HOST1_ DP pin;
UART function pin: an AM335X _ UART0_ RXD pin, an AM335X _ UART0_ TXD pin, an AM335X _ UART1_ TXD pin, an AM335X _ UART1_ RXD pin, an AAM335X _ Mil1_ RXERR pin, an AM335X _ Mli1_ CRS pin, an AM335X _ UART0_ CTSn pin, an AM335X _ UART0_ RTSn pin, an AM335X _ LCD _ DATA9 pin, an AM335X _ LCD _ DATA8 pin;
IIC function pin: AM335X _ UART1_ RTSn pin, AM335X _ UART1_ CTSn pin;
SPI function pin: an AM335X _ SPIO _ D1 pin, an AM335X _ SPIO _ D0 pin, an AM335X _ SPI0_ CS 0pin, an AM335X _ SPI0_ SCLK pin, an AM335X _ LCD _ PCLK pin;
MII function pin: an AM335X _ Mil1_ MDIO _ CLK pin, an AM335X _ Mil1_ MDIO _ DATA pin, an AM335X _ Mil1_ TXD1 pin, an AM335X _ Mil1_ TXD 0pin, an AM335X _ Mil1_ TXEN pin, an AM335X _ Mil1_ RXDV pin, an AM335X _ Mil1_ RXD 0pin, an AM335X _ Mil1_ RXD1 pin, an AM335X _ Mil1_ TXCLK pin, an AM335X _ USB0_ DRVVBUS pin;
MMC function pin: an AM335X _ MMC _ D0 pin, an AM335X _ MMC _ D1 pin, an AM335X _ MMC _ CLK pin, an AM335X _ MMC _ D3 pin, an AM335X _ MMC _ D2 pin, an AM335X _ MMC _ CMD pin, an AM335X _ MCASP0_ ACLKX pin;
GPIO function pin: an AM335X _ GPMC _ CS1n pin, an AM335X _ CS2n pin, an AM335X _ GPMC _ AD10 pin, an AM335X _ GPMC _ AD8 pin, an AM335X _ GPMC _ AD9 pin, an AM335 9 _ LCD _ AC _ BIAS _ EN pin, an AM335 9 _ MCASP 9 _ AHCLKX pin, a VBACKUP O pin, an AM335 9 _ MCASP 9 _ FSR pin, an AM335 9 _ LCD _ HSTNC pin, an AM335 9 _ LCD _ VSYNC pin, an AM335 9 _ MCASP 9 _ aclkrhr pin, an AM 36335 _ MCASP 9 _ AXR 9 pin, an AM 36335 _ USB 72 _ vvdrbus pin, and an AM335 _ fcsrefr 9 pin.
9. The circuit adapter of claim 8, wherein the pin 1 is connected to the USB _ HOST2_ N pin, the pin 3 is connected to the USB _ HOST2_ P pin, the pin 5 is connected to the USB _ OTG _ DRV pin, the pin 7 is connected to the AM335X _ UART0_ RXD pin, the pin 9 is connected to the AM335X _ UART0_ TXD pin, the pin 13 is connected to the AM335X _ SPIO _ D1, the pin 15 is connected to the AM335X _ SPIO _ D0 pin, the pin 19 is connected to the AM335X _ UART1_ RTSn pin, the pin 21 is connected to the AM335X _ UART1_ CTSn pin, the pin 25 is connected to the AM335 _ LCD _ BIAS _ BIN pin, the pin 27 is connected to the USB _ OTG _ ID pin, the pin 29 is connected to the AM335 _ MIX X _ FCEN _ GCK 4631, the pin 5833 is connected to the AM335 _ ACOCAS _ OCOS _ SPIO _ D4633 pin, and the pin 5831 is connected to the AM335 _ OCAS _ OCEN _ OCX _ OCE _ MCAS _ D4633, pin 39 is connected to AM335X _ SPI0_ SCLK pin, pin 43 is connected to AM335X _ LCD _ DATA9 pin, pin 45 is connected to AM335X _ LCD _ DATA8 pin, pin 53, pin 55, pin 57, pin 59 is connected to VCC _5V pin, pin 6 is connected to USB OTG _ DM pin, pin 8 is connected to USB OTG _ DP pin, pin 12 is connected to USB HOST1_ DM pin, pin 14 is connected to USB HOST1_ DP pin, pin 30 is connected to AM335X _ USB0_ vvbus pin, pin 32 is connected to AM335X _ sp0_ FSR pin, pin 34 is connected to AM X _ GPMC _ 10 pin, pin 36 is connected to AM335 _ USB1_ vv pin, pin milc 335 is connected to milc 53 _ SCLK pin 368672 pin 3646 pin, pin 368672 is connected to AM TXD 368672 pin 3646 pin 1 pin 368672, and pin 368672 is connected to AM TXD 368642 pin 1, pin number 48 is connected to the AM335X _ Mil1_ TXEN pin, pin number 50 is connected to the AM335X _ Mil1_ RXDV pin, pin number 52 is connected to the AM335X _ Mil1_ RXD 0pin, pin number 54 is connected to the AM335X _ Mil1_ RXD1 pin, and pin number 58 is connected to the AM335X _ Mil1_ TXCLK pin.
10. The circuit switching device of a homemade chip as claimed in claim 1, wherein thirty-three pins of said CN2 socket are connected to AM335X _ UART0_ CTSn pin, thirty-five pins are connected to AM335X _ UART0_ RTSn pin, thirty-nine pins are connected to AM335X _ Mil1_ RXERR pin, forty-one pins are connected to AM335X _ Mli1_ CRS pin, forty-five pins are connected to AM335X _ GPMC _ CS1n pin, forty-seven pins are connected to AM335X _ CS2n pin, a forty-nineteen pins are connected to M335X _ GPMC _ AD _ 8 pin, fifty-one pins are connected to AM335X _ GPMC _ AD9 pin, fifty-five pins are connected to AM335X _ UART1_ d pin, fifty-seven pins are connected to AM335 _ 2_ RXD pin, twenty-nine pins are connected to AM335 _ rxjd 2_ RXD pin, twenty-nine pins are connected to VSYNC 8427 pin, twenty-eight pin X pin and VSYNC pin, thirty-first pin is connected with AM335X _ MCASP0_ ACLKR pin, thirty-fourth pin is connected with AM335X _ MCASP0_ AXR1 pin, thirty-eight pin is connected with AM335X _ GPMC _ AD12 pin, forty-first pin is connected with AM335X _ GPMC _ AD11 pin, forty-fourth pin is connected with AM335X _ MMC _ D0 pin, forty-six pin is connected with AM335X _ MMC _ D1 pin, fifty-first pin is connected with AM335X _ MMC _ CLK pin, fifty-fourth pin is connected with AM335X _ MCASP0_ ACLKX pin, fifty-sixth pin is connected with AM335X _ MMC _ D3 pin, eight-first pin is connected with AM335X _ MMC _ D2 pin, and sixty-first pin is connected with AM335 _ 335X _ MMC _ CMD pin.
Technical Field
The invention relates to the technical field of circuit switching, in particular to a circuit switching device of a domestic chip.
Background
In the existing power environment monitoring industry and security monitoring industry, processors used by the mainstream monitoring equipment at present are foreign, such as embedded processors of foreign companies like ATMEL, NXP, TI and the like. However, in the domestic military dynamic environment monitoring industry, the functional requirements of FSU (field monitoring unit) products are the same, but a localization processor is required to be used, and according to the application scene, the localization processor needs to be replaced. It is a common practice to redesign a monitoring device based on a localization processor to realize a new product, and the defects of the whole redesign are as follows:
1. the application products with the same function only require the localization and redesign different products, which causes the low data reuse rate and the increase of the useless work;
2. the low availability causes the corresponding cost to be high;
3. the development period is prolonged;
4. the amount of product maintenance increases.
Disclosure of Invention
In view of the above problems, the present invention provides a circuit switching device for a home-made chip to solve the problems mentioned in the background art.
In order to solve the problems, the invention adopts the following technical scheme: a circuit switching device of a home-made chip is characterized by comprising: a circuit board is provided with a plurality of circuit boards,
the core board butt joint end is arranged on the upper layer of the circuit board and can be used for connecting a core board processor;
the CN1 seat and the CN2 seat, the CN1 seat and the CN1 seat are arranged on the lower layer of the circuit board and positioned on two sides of the butt joint end of the core board, and are used for converting the pins of the butt joint end of the core board into pins of a pin seat;
the pin of the needle seat is arranged on the lower layer of the circuit board and can be used for connecting an external bottom plate;
the butt joint end of the core plate is respectively connected with the CN1 seat and the CN2 seat, and the pin of the needle seat is respectively connected with the CN1 seat and the CN2 seat.
The CN1 seat is provided with No. 1 to No. 60 pins;
the CN2 seat is provided with a pin from I to sixty.
The core board butt joint end includes: USB function pin end, UART function pin end, IIC function pin end, SPI function pin end, RGMII function pin end, MMC function pin end, GPIO function pin end.
The core plate butt joint end specifically includes: USB functional pin terminals: HOST2_ DM pin terminal, HOST2_ DP pin terminal, OTG _ DR pin terminal, OTG _ ID pin terminal, VDD _ SV _ SYS pin terminal, OTG _ DM pin terminal, OTG _ DP pin terminal, HOST1_ DM pin terminal, HOST1_ DP pin terminal;
UART function pin terminal: a UART2_ RXD pin terminal, a UART2_ TXD pin terminal, a UART1_ RXD pin terminal, a UART1_ TXD pin terminal, a UART3_ RXD/GPIO7_ A7 pin terminal, a UART3_ TXD/GPIO7_ B0 pin terminal, a UART4_ TXD/SPI0_ TXD pin terminal, a UART4_ RXD/SPIO _ RXD pin terminal, a UARTO _ RXD pin terminal, a UARTD _ TXD pin terminal;
IIC function pin terminal: I2C1_ SCL _ Sensor pin terminal, I2C1_ SDA _ Sensor pin terminal;
SPI functional pin terminals: an SPI1_ TXD/GPIO7_ B7 pin terminal, an SPI1_ TXD/GPIO7_ B6 pin terminal, an SPI1_ CSNO/GPIO7_ B5 pin terminal, an SPI1_ CLK/GPIO7_ B4 pin terminal, and an SPIO _ CSN 0pin terminal;
RGMII functional pin end: a UARTO _ CTS pin terminal, a UARTO _ RTS pin terminal, a MAC _ MDC pin terminal, a MAC _ MDIO pin terminal, a MAC _ TXD1 pin terminal, a MAC _ TXD 0pin terminal, a MAC _ TXEN pin terminal, a MAC _ RXDV pin terminal, a MAC _ RXD 0pin terminal, a MAC _ RXD1 pin terminal and a MAC _ CLK pin terminal;
MMC function pin end: an SDMMC _ CMD pin end, an SDMMC _ D2 pin end, an SDMMC _ D3 pin end, an SDMMC _ DET pin end, an SDMMC _ CLK pin end, an SDMMC _ D1 pin end, an SDMMC _ D0 pin end and a VDD _3V3_ RTC pin end;
GPIO function pin terminal: a GPIO7_ C5 pin terminal, a UART3_ CTS/GPIO7_ B1 pin terminal, a GPIO5_ C1 pin terminal, a GPIO4_ D7 pin terminal, a GPIO4_ D6 pin terminal, a SDICO _ D3/GPIO4_ C7 pin terminal, a SDICO _ BKPPR/GPIO 4_ D5 pin terminal, a SDICO _ CLK/GPIO4_ D1 pin terminal, a SDICO _ WRPRT/GPIO4_ D3 pin terminal, a SDICO _ DET/GPIO4_ D2 pin terminal, a SDICO _ PWR/GPIO4_ D4 pin terminal, a SDIC _ D1/GPIO4_ C5 pin terminal, a SDIC _ D2/4 _ C6 pin terminal, a SDIC
the No. 11 pin, the No. 17 pin, the No. 23 pin, the No. 35 pin, the No. 41 pin, the No. 47 pin, the No. 49 pin, the No. 51 pin, the No. 2 pin, the No. 4 pin, the No. 10 pin, the No. 16 pin, the No. 28 pin, the No. 38 pin, the No. 56 pin and the No. 60 pin are grounded,
no. 18 pin, No. 20 pin, No. 22 pin, No. 24 pin and No. 26 pin are not connected.
The sixty-number pin is connected with an SDMMC _ CMD pin terminal, the fifty-number pin is connected with an SDMMC _ D2 pin terminal, the fifty-six number pin is connected with an SDMMC _ D3 pin terminal, the fifty-number pin is connected with an SDMMC _ DET pin terminal, the fifty-number pin is connected with an SDMMC _ CLK pin terminal, the forty-six number pin is connected with an SDMMC _ D1 pin terminal, the forty-four number pin is connected with an SDMMC _ D0 pin terminal, the forty-number pin is connected with an SDCO _ D3/GPIO4_ C7 pin terminal, the thirty-eight number pin is connected with an SDCO _ BKPPWR/4 _ D3 pin terminal, the thirty-eight number pin is connected with an SDCO _ CLK/4
the fifty-two pin, the forty-eight pin, the forty-two pin, the thirty-six pin, the thirty-two pin, the twenty-four pin, the twenty-two pin, the four pin, the two pin, the fifty-three pin, the forty-three pin, the thirty-seven pin, the thirty-eleven pin, the twenty-three pin, the twenty-one pin, the three pin and the one pin are grounded,
and the No. twenty pin, the No. eighteen pin, the No. sixteen pin, the No. fourteen pin, the No. twelve pin, the No. ten pin, the No. eight pin, the No. six pin, the No. nineteen pin, the No. seventeen pin, the No. fifteen pin, the No. thirteen pin, the No. eleven pin, the No. nine pin, the No. seven pin and the No. five pin are not connected.
The needle hub pin includes: USB function pin, UART function pin, IIC function pin, SPI function pin, MII function pin, GPIO function pin.
The needle file pin specifically includes:
USB function pin: a USB _ HOST2_ N pin, a USB _ HOST2_ P pin, a USB _ OTG _ DRV pin, a USB _ OTG _ ID pin, a VCC _5V pin, a USB _ OTG _ DM pin, a USB _ OTG _ DP pin, a USB _ HOST1_ DM pin, and a USB _ HOST1_ DP pin;
UART function pin: an AM335X _ UART0_ RXD pin, an AM335X _ UART0_ TXD pin, an AM335X _ UART1_ TXD pin, an AM335X _ UART1_ RXD pin, an AAM335X _ Mil1_ RXERR pin, an AM335X _ Mli1_ CRS pin, an AM335X _ UART0_ CTSn pin, an AM335X _ UART0_ RTSn pin, an AM335X _ LCD _ DATA9 pin, an AM335X _ LCD _ DATA8 pin;
IIC function pin: AM335X _ UART1_ RTSn pin, AM335X _ UART1_ CTSn pin;
SPI function pin: an AM335X _ SPIO _ D1 pin, an AM335X _ SPIO _ D0 pin, an AM335X _ SPI0_ CS 0pin, an AM335X _ SPI0_ SCLK pin, an AM335X _ LCD _ PCLK pin;
MII function pin: an AM335X _ Mil1_ MDIO _ CLK pin, an AM335X _ Mil1_ MDIO _ DATA pin, an AM335X _ Mil1_ TXD1 pin, an AM335X _ Mil1_ TXD 0pin, an AM335X _ Mil1_ TXEN pin, an AM335X _ Mil1_ RXDV pin, an AM335X _ Mil1_ RXD 0pin, an AM335X _ Mil1_ RXD1 pin, an AM335X _ Mil1_ TXCLK pin, an AM335X _ USB0_ DRVVBUS pin;
MMC function pin: an AM335X _ MMC _ D0 pin, an AM335X _ MMC _ D1 pin, an AM335X _ MMC _ CLK pin, an AM335X _ MMC _ D3 pin, an AM335X _ MMC _ D2 pin, an AM335X _ MMC _ CMD pin, an AM335X _ MCASP0_ ACLKX pin;
GPIO function pin: an AM335X _ GPMC _ CS1n pin, an AM335X _ CS2n pin, an AM335X _ GPMC _ AD10 pin, an AM335X _ GPMC _ AD8 pin, an AM335X _ GPMC _ AD9 pin, an
The pin No. 1 is connected to the USB _ HOST2_ N pin, the pin No. 3 is connected to the USB _ HOST2_ P pin, the pin No. 5 is connected to the USB _ OTG _ DRV pin, the pin No. 7 is connected to the AM335X _ UART0_ RXD pin, the pin No. 9 is connected to the AM335X _ UART0_ TXD pin, the pin No. 13 is connected to the AM335 _ SPIO _ D1 pin, the pin No. 15 is connected to the AM335X _ SPIO _ D0 pin, the pin No. 19 is connected to the AM335X _ UART1_ RTSn pin, the pin No. 21 is connected to the AM335 _ UART1_ CTSn pin, the pin No. 25 is connected to the AM335 _ LCD _ AC _ BIAS _ EN pin, the pin No. 27 is connected to the USB _ OTG _ ID pin, the pin No. 29 is connected to the AM X _ reffck X _ fclk pin, the pin No. 3631 is connected to the AM335 _ LCD X _ fclk pin, the pin No. X is connected to the SPI X pin No. X _ up 36335, the pin 3636363672 is connected to the pin 363636363672 pin X, the pin No. 36363636363672 is connected to the pin No. 363672, the pin No. 36363636363672 is connected to the pin X pin, pin No. 53, pin No. 55, pin No. 57, pin No. 59 are connected to the VCC _5V pin, pin No. 6 is connected to the USB _ OTG _ DM pin, pin No. 8 is connected to the USB _ OTG _ DP pin, pin No. 12 is connected to the USB _ HOST1_ DM pin, pin No. 14 is connected to the USB _ HOST1_ DP pin, pin No. 30 is connected to the AM335X _ USB0_ DRVVBUS pin, pin No. 32 is connected to the AM335X _ MCASP0_ FSR pin, pin No. 34 is connected to the AM335X _ GPMC _ AD10 pin, pin No. 36 is connected to the AM335X _ USB1_ DRVVBUS pin, pin No. 40 is connected to the AM335 mil9 _ milc 2_ MDIO _ CLK pin, pin No. 42 is connected to the AM 82335 _ milc 1_ MDIO _ pin, pin No. 44 is connected to the AM 86335 _ milc 867 _ MDIO _ CLK pin, pin No. 42 is connected to the AM 1_
Thirty-three pins of the CN2 socket are connected with an AM335X _ UART0_ CTSn pin, thirty-five pins are connected with an AM335X _ UART0_ RTSn pin, thirty-nine pins are connected with an AM335X _ Mil1_ RXERR pin, forty-one pins are connected with an AM335X _ Mli1_ CRS pin, forty-five pins are connected with an AM335 _ GPMC _ CS1n pin, forty-seven pins are connected with an AM335 _ CS2n pin, a forty-nineteen pins are connected with an M335 n _ GPMC _ AD n pin, a fifty-one pin is connected with an AM335 _ GPMC _ AD n pin, a fifty-five pin is connected with an AM335 _ n _ TXD pin, a seven pin is connected with an AM335 _ n _ RXD pin, a fifty-nine pin is connected with a PCLK _ AM n pin, a twenty-six pin is connected with an AM 5972 _ TXD pin, a thirty-six pin is connected with an acxsam n _ tnam n pin, a thirty-six pin is connected with an acxsam n pin, a thirty-36335 is connected with an acxsam n pin, thirty-eight pins are connected with an AM335X _ GPMC _ AD12 pin, forty pins are connected with an AM335X _ GPMC _ AD11 pin, forty-four pins are connected with an AM335X _ MMC _ D0 pin, forty-six pins are connected with an AM335X _ MMC _ D1 pin, fifty pins are connected with an AM335X _ MMC _ CLK pin, fifty-four pins are connected with an AM335X _ MCASP0_ ACLKX pin, fifty-six pins are connected with an AM335X _ MMC _ D3 pin, fifty-eight pins are connected with an AM335X _ MMC _ D2 pin, and sixty pins are connected with an AM335X _ MMC _ CMD pin.
The invention has the beneficial effects that:
according to the invention, the CN1 seat and the CN2 seat are arranged to convert the butt joint end of the core board into the pin of the pin seat, so that the device replaces the original core board with the connection of a domestic chip and the original bottom board, the repeated utilization rate of product data is improved, the cost is reduced, the development period is shortened, and chips with the same size do not need to be developed.
Drawings
FIG. 1 is a block diagram of the assembly of the present invention with a core board processor, backplane;
FIG. 2 is a diagram of the connection between the CN1 socket and the mating end of the core board according to the present invention;
FIG. 3 is a diagram of the connection between the CN2 socket and the mating end of the core board according to the present invention;
FIG. 4 is a drawing showing the connection relationship between the CN1 hub and the hub pins according to the present invention;
fig. 5 is a connection relationship diagram of the CN2 hub and hub pin according to the present invention.
Detailed Description
It will be apparent to those skilled in the art that various modifications may be made to the above embodiments without departing from the general spirit and concept of the invention. All falling within the scope of protection of the present invention. The protection scheme of the invention is subject to the appended claims.
The invention provides a circuit switching device of a localization chip as shown in figure 1, which comprises:
the core board butt joint end is used for connecting the core board processor;
the CN1 seat and the CN2 seat are used for converting the pin of the butt joint end of the core board into the pin of the pin seat;
the pin of the needle seat is used for connecting an external bottom plate;
the butt ends of the core plate are respectively connected with the CN1 seat and the CN2 seat, and the pins of the needle seat are respectively connected with the CN1 seat and the CN2 seat.
The CN1 seat is provided with No. 1 to No. 60 pins;
the CN2 seat is provided with a pin from I to sixty.
In one embodiment of the present invention, the CN1 seat and the CN2 seat use the female patch row and the male patch row needles manufactured by the fast ruin corporation, and the specification parameters are BTB0.84-6.5, and the detailed parameters are 0.8mm pitch, 2 × 30 Pin.
The core plate butt joint end includes: USB function pin end, UART function pin end, IIC function pin end, SPI function pin end, RGMII function pin end, MMC function pin end, GPIO function pin end.
The core plate butt joint end specifically includes: USB functional pin terminals: HOST2_ DM pin terminal, HOST2_ DP pin terminal, OTG _ DR pin terminal, OTG _ ID pin terminal, VDD _ SV _ SYS pin terminal, OTG _ DM pin terminal, OTG _ DP pin terminal, HOST1_ DM pin terminal, HOST1_ DP pin terminal;
UART function pin terminal: a UART2_ RXD pin terminal, a UART2_ TXD pin terminal, a UART1_ RXD pin terminal, a UART1_ TXD pin terminal, a UART3_ RXD/GPIO7_ A7 pin terminal, a UART3_ TXD/GPIO7_ B0 pin terminal, a UART4_ TXD/SPI0_ TXD pin terminal, a UART4_ RXD/SPIO _ RXD pin terminal, a UARTO _ RXD pin terminal, a UARTD _ TXD pin terminal;
IIC function pin terminal: I2C1_ SCL _ Sensor pin terminal, I2C1_ SDA _ Sensor pin terminal;
SPI functional pin terminals: an SPI1_ TXD/GPIO7_ B7 pin terminal, an SPI1_ TXD/GPIO7_ B6 pin terminal, an SPI1_ CSNO/GPIO7_ B5 pin terminal, an SPI1_ CLK/GPIO7_ B4 pin terminal, and an SPIO _ CSN 0pin terminal;
RGMII functional pin end: a UARTO _ CTS pin terminal, a UARTO _ RTS pin terminal, a MAC _ MDC pin terminal, a MAC _ MDIO pin terminal, a MAC _ TXD1 pin terminal, a MAC _ TXD 0pin terminal, a MAC _ TXEN pin terminal, a MAC _ RXDV pin terminal, a MAC _ RXD 0pin terminal, a MAC _ RXD1 pin terminal and a MAC _ CLK pin terminal;
MMC function pin end: an SDMMC _ CMD pin end, an SDMMC _ D2 pin end, an SDMMC _ D3 pin end, an SDMMC _ DET pin end, an SDMMC _ CLK pin end, an SDMMC _ D1 pin end, an SDMMC _ D0 pin end and a VDD _3V3_ RTC pin end;
GPIO function pin terminal: a GPIO7_ C5 pin terminal, a UART3_ CTS/GPIO7_ B1 pin terminal, a GPIO5_ C1 pin terminal, a GPIO4_ D7 pin terminal, a GPIO4_ D6 pin terminal, a SDICO _ D3/GPIO4_ C7 pin terminal, a SDICO _ BKPPR/GPIO 4_ D5 pin terminal, a SDICO _ CLK/GPIO4_ D1 pin terminal, a SDICO _ WRPRT/GPIO4_ D3 pin terminal, a SDICO _ DET/GPIO4_ D2 pin terminal, a SDICO _ PWR/GPIO4_ D4 pin terminal, a SDIC _ D1/GPIO4_ C5 pin terminal, a SDIC _ D2/4 _ C6 pin terminal, a SDIC _
Pin No. 1 is connected to HOST2_ DM pin terminal, pin No. 3 is connected to HOST2_ DP pin terminal, pin No. 5 is connected to OTG _ DR pin terminal, pin No. 7 is connected to UART2_ RXD pin terminal, pin No. 9 is connected to UART2_ TXD pin terminal, pin No. 13 is connected to SPI1_ TXD/GPIO7_ B7 pin terminal, pin No. 15 is connected to SPI1_ TXD/7 _ B6 pin terminal, pin No. 19 is connected to I2C1_ SCL _ Sensor pin terminal, pin No. 21 is connected to I2C1_ GPIO _ Sensor pin terminal, pin No. 25 is connected to GPIO7_ C5 pin terminal, pin No. 27 is connected to SDA _ ID pin terminal, pin No. 29 is connected to UART2_ GPIO/7 _ B1 pin, pin No. 31 is connected to GPIO 1_ C5 pin GPIO, pin No. 27 is connected to OTG _ ID pin No. 1B 1 terminal, pin No. 1 is connected to SPI1_ GPIO/GPIO 1 pin No. 368672B 1 terminal, pin No. 1/GPIO 1, pin number 43 is connected to the pin terminals UART3_ RXD/GPIO7_ A7, pin number 45 is connected to the pin terminals UART3_ TXD/GPIO7_ B0, pin number 53, pin number 55, pin number 57, pin number 59 are connected to the pin terminals VDD _ SV _ SYS, pin number 6 is connected to the pin terminal OTG _ DM, pin number 8 is connected to the pin terminal OTG _ DP, pin number 12 is connected to the pin terminal HOST1_ DM, pin number 14 is connected to the pin terminal HOST1_ DP, pin number 30 is connected to the pin terminal UARTO _ CTS, pin number 32 is connected to the pin terminal UARTO _ GPIO _ CTS, pin number 34 is connected to the pin terminal GPIO _ D4 _ D7, pin number 36 is connected to the pin terminal TXD 4_ D6, pin number 40 is connected to the pin terminal MAC _ MDC 42, pin number 63EN is connected to the pin terminal MAC 6344, pin number 44 is connected to the pin number TXD _ D4 _ D48, pin number 8 is connected to the pin terminal MAC 6348, pin number 52 is connected to the pin terminal of MAC _ RXD0, pin number 54 is connected to the pin terminal of MAC _ RXD1, pin number 58 is connected to the pin terminal of MAC _ CLK,
pin No. 11, pin No. 17, pin No. 23, pin No. 35, pin No. 41, pin No. 47, pin No. 49, pin No. 51, pin No. 2, pin No. 4, pin No. 10, pin No. 16, pin No. 28, pin No. 38, pin No. 56, and pin No. 60 are grounded,
pin No. 18, pin No. 20, pin No. 22, pin No. 24, and pin No. 26 have no connection.
Sixty pin is connected to SDMMC _ CMD pin terminal, fifty eight pin is connected to SDMMC _ D2 pin terminal, fifty six pin is connected to SDMMC _ D3 pin terminal, fifty four pin is connected to SDMMC _ DET pin terminal, fifty pin is connected to SDMMC _ CLK pin terminal, forty six pin is connected to SDMMC _ D1 pin terminal, forty four pin is connected to SDMMC _ D0 pin terminal, forty pin is connected to SDCO _ D3/GPIO4_ C7 pin terminal, thirty eight pin is connected to SDCO _ BKPP/WR 4_ D5 pin terminal, thirty four pin is connected to SDCO _ CLK/GPIO4_ D1 pin terminal, thirty pin is connected to SDCO _ WRPRT/4 _ D3 pin terminal, twenty eight pin is connected to SDCO _ WRGPIO _ GPIO/GPIO 4 pin terminal, SDCO _ WR _ DET/4 _ D3 pin is connected to SDMC _ CMD _ D2 pin terminal, SDMC _ D _ DET/SDCO _ D2 pin is connected to SDMC _ D6326 pin terminal, and SDMC _ CLK/SDMC _ CLK pin is connected to SDCO _ CLK/SDCO _ CLK pin 4 terminal, fifty-five pins are connected with UARTD _ TXD pin ends, fifty-one pins are connected with SDOD _ D1/GPIO4_ C5 pin ends, forty-nine pins are connected with SDOD _ D2/GPIO4_ C6 pin ends, forty-seven pins are connected with SDOD _ CMD/GPIO4_ D0 pin ends, forty-five pins are connected with SDOD _ D0/GPIO4_ C4 pin ends, forty-one pins are connected with UART1_ RXD pin ends, thirty-nine pins are connected with UART1_ TXD pin ends, thirty-five pins are connected with UART4_ TXD/SPI0_ TXD pin ends, thirty-three pins are connected with UART4_ RXD/SPIO _ RXD pin ends,
a fifty-two pin, a forty-eight pin, a forty-two pin, a thirty-six pin, a thirty-two pin, a twenty-four pin, a twenty-two pin, a four pin, a two pin, a fifty-three pin, a forty-three pin, a thirty-seven pin, a thirty-eleven pin, a twenty-three pin, a twenty-one pin, a three pin and a one pin are grounded,
no. twenty pin, No. eighteen pin, No. sixteen pin, No. fourteen pin, No. twelve pin, No. ten pin, No. eight pin, No. six pin, No. nineteen pin, No. seventeen pin, No. fifteen pin, No. thirteen pin, No. eleven pin, No. nine pin, No. seven pin and No. five pin are not connected.
The needle file pin includes: USB function pin, UART function pin, IIC function pin, SPI function pin, MII function pin, GPIO function pin.
The needle file pin specifically includes:
USB function pin: a USB _ HOST2_ N pin, a USB _ HOST2_ P pin, a USB _ OTG _ DRV pin, a USB _ OTG _ ID pin, a VCC _5V pin, a USB _ OTG _ DM pin, a USB _ OTG _ DP pin, a USB _ HOST1_ DM pin, and a USB _ HOST1_ DP pin;
UART function pin: an AM335X _ UART0_ RXD pin, an AM335X _ UART0_ TXD pin, an AM335X _ UART1_ TXD pin, an AM335X _ UART1_ RXD pin, an AAM335X _ Mil1_ RXERR pin, an AM335X _ Mli1_ CRS pin, an AM335X _ UART0_ CTSn pin, an AM335X _ UART0_ RTSn pin, an AM335X _ LCD _ DATA9 pin, an AM335X _ LCD _ DATA8 pin;
IIC function pin: AM335X _ UART1_ RTSn pin, AM335X _ UART1_ CTSn pin;
SPI function pin: an AM335X _ SPIO _ D1 pin, an AM335X _ SPIO _ D0 pin, an AM335X _ SPI0_ CS 0pin, an AM335X _ SPI0_ SCLK pin, an AM335X _ LCD _ PCLK pin;
MII function pin: an AM335X _ Mil1_ MDIO _ CLK pin, an AM335X _ Mil1_ MDIO _ DATA pin, an AM335X _ Mil1_ TXD1 pin, an AM335X _ Mil1_ TXD 0pin, an AM335X _ Mil1_ TXEN pin, an AM335X _ Mil1_ RXDV pin, an AM335X _ Mil1_ RXD 0pin, an AM335X _ Mil1_ RXD1 pin, an AM335X _ Mil1_ TXCLK pin, an AM335X _ USB0_ DRVVBUS pin;
MMC function pin: an AM335X _ MMC _ D0 pin, an AM335X _ MMC _ D1 pin, an AM335X _ MMC _ CLK pin, an AM335X _ MMC _ D3 pin, an AM335X _ MMC _ D2 pin, an AM335X _ MMC _ CMD pin, an AM335X _ MCASP0_ ACLKX pin;
GPIO function pin: an AM335X _ GPMC _ CS1n pin, an AM335X _ CS2n pin, an AM335X _ GPMC _ AD10 pin, an AM335X _ GPMC _ AD8 pin, an AM335X _ GPMC _ AD9 pin, an
Pin No. 1 is connected to USB _ HOST2_ N pin, pin No. 3 is connected to USB _ HOST2_ P pin, pin No. 5 is connected to USB _ OTG _ DRV pin, pin No. 7 is connected to AM335X _ UART0_ RXD pin, pin No. 9 is connected to AM335X _ UART0_ TXD pin, pin No. 13 is connected to AM335 _ SPIO _ D1 pin, pin No. 15 is connected to AM335X _ SPIO _ D0 pin, pin No. 19 is connected to AM335X _ UART1_ RTSn pin, pin No. 21 is connected to AM335X _ UART1_ CTSn pin, pin No. 25 is connected to AM335 _ LCD _ AC _ BIAS _ EN pin, pin No. 27 is connected to USB _ OTG _ ID pin, pin No. 29 is connected to AM 36335 _ Mil _ rec _ fcsn pin X _ fcfsn pin, pin No. 3631 is connected to AM335 _ LCD _ AC _ BIAS _ X _ pin, pin No. 27 is connected to SPI _ ocx 36335 pin X _ fcocx 36335, pin 363672 is connected to SPI 36363672 pin X, pin 363636363636335 is connected to SPI pin X, pin No. 53, pin No. 55, pin No. 57, pin No. 59 are connected to the VCC _5V pin, pin No. 6 is connected to the USB _ OTG _ DM pin, pin No. 8 is connected to the USB _ OTG _ DP pin, pin No. 12 is connected to the USB _ HOST1_ DM pin, pin No. 14 is connected to the USB _ HOST1_ DP pin, pin No. 30 is connected to the AM335X _ USB0_ DRVVBUS pin, pin No. 32 is connected to the AM335X _ MCASP0_ FSR pin, pin No. 34 is connected to the AM335X _ GPMC _ AD10 pin, pin No. 36 is connected to the AM335X _ USB1_ DRVVBUS pin, pin No. 40 is connected to the AM335 mil9 _ milc 2_ MDIO _ CLK pin, pin No. 42 is connected to the AM 82335 _ milc 1_ MDIO _ pin, pin No. 44 is connected to the AM 86335 _ milc 867 _ MDIO _ CLK pin, pin No. 42 is connected to the AM 1_ txdv 1 pin 1, pin No. 363672 is connected to the AM 1_ txdv 1 pin 1, pin 363672 is connected to the AM 1_ TXD1, pin 54 is connected to pin AM335X _ Mil1_ RXD1, and pin 58 is connected to pin AM335X _ Mil1_ TXCLK.
Thirty-three pins of the CN2 socket are connected with an AM335X _ UART0_ CTSn pin, thirty-five pins are connected with an AM335X _ UART0_ RTSn pin, thirty-nine pins are connected with an AM335X _ Mil1_ RXERR pin, forty-one pins are connected with an AM335X _ Mli1_ CRS pin, forty-five pins are connected with an AM335X _ GPMC _ CS1n pin, forty-seven pins are connected with an AM335X _ CS2n pin, a forty-nineteen pins are connected with an M335 n _ GPMC _ AD n pin, fifty-one pins are connected with an AM335 _ GPMC _ AD n pin, fifty-five pins are connected with an AM335 _ n _ TXD pin, seven pins are connected with an AM335 _ n _ RXD pin, a fifty-nine pins are connected with a PCLK _ AM n pin, a twenty-six pins are connected with an AM 5972 _ TXD pin, thirty-six pins are connected with an AM n pin, an acxsam n pin is connected with an actnam n pin, thirty-three pin is connected with an actnam n pin, a thirty-eight pin 363672 pin is connected with an actnam n pin, thirty-eight pins are connected with an AM335X _ GPMC _ AD12 pin, forty pins are connected with an AM335X _ GPMC _ AD11 pin, forty-four pins are connected with an AM335X _ MMC _ D0 pin, forty-six pins are connected with an AM335X _ MMC _ D1 pin, fifty pins are connected with an AM335X _ MMC _ CLK pin, fifty-four pins are connected with an AM335X _ MCASP0_ ACLKX pin, fifty-six pins are connected with an AM335X _ MMC _ D3 pin, fifty-eight pins are connected with an AM335X _ MMC _ D2 pin, and sixty pins are connected with an AM335X _ MMC _ CMD pin.
In an embodiment of the invention, the core board processor is formed by adopting a RK3288 domestic processor produced by domestic core micro corporation and an SOM3288 core board manufactured by Guangzhou Chuanglong Gong based on 3288 processor, and can be connected with the core board connecting groove of the invention to replace an AM3352 processor of foreign IT company to connect the original functional pins of the bottom board.
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