阅读说明：本技术 瞬态增强型ldo电路、cmos驱动器电源电路及激光器系统 (Transient enhanced LDO (low dropout regulator) circuit, CMOS (complementary metal oxide semiconductor) driver power supply circuit and laser system ) 是由 刘建峰 向少卿 于 2019-08-20 设计创作，主要内容包括：本公开的实施方式涉及一种瞬态增强型LDO电路、CMOS驱动器电源电路及激光器系统。该瞬态增强型LDO电路包括：放大器,所述放大器的其中一个输入端可接收参考电压；功率调整管,耦合到所述放大器的输出,并通过输出端输出所述瞬态增强型LDO电路的输出电压；分压器,耦接所述功率调整管,将所述输出电压耦合到所述放大器的另一个输入端；和灌电流吸收电路,耦接至所述功率调整管的输出端,适于根据所述输出电压的波动,导通并吸收对所述LDO电路的灌电流。从而,提供了一种性能改善的瞬态增强型LDO电路。(Embodiments of the present disclosure relate to a transient enhanced LDO circuit, a CMOS driver power circuit, and a laser system. The transient enhanced LDO circuit includes: an amplifier, one of the inputs of which may receive a reference voltage; a power regulating tube coupled to the output of the amplifier and outputting the output voltage of the transient enhanced LDO circuit through an output end; a voltage divider coupled to the power adjusting tube for coupling the output voltage to another input terminal of the amplifier; and the current sinking absorption circuit is coupled to the output end of the power adjusting tube and is suitable for conducting and absorbing the current sinking to the LDO circuit according to the fluctuation of the output voltage. Thus, a transient enhanced LDO circuit with improved performance is provided.)

1. A transient enhanced LDO circuit, comprising:

an amplifier, one of the inputs of which may receive a reference voltage;

a power regulating tube coupled to the output of the amplifier and outputting the output voltage of the transient enhanced LDO circuit through an output end;

a voltage divider coupled to the power adjusting tube for coupling the output voltage to another input terminal of the amplifier; and

and the current sinking absorption circuit is coupled to the output end of the power adjusting tube and is suitable for conducting and absorbing the current sinking to the LDO circuit according to the fluctuation of the output voltage.

2. The transient-enhanced LDO circuit of claim 1, wherein the sinking current sinking circuit comprises a comparator and a pull-down NMOS transistor driven by the comparator, wherein one input of the comparator receives an input signal reflecting a fluctuation of the output voltage, another input of the comparator receives a threshold signal corresponding to the input signal reflecting the fluctuation of the output voltage, the pull-down NMOS transistor is coupled to an output of the power adjusting transistor and an output of the comparator, wherein the pull-down NMOS transistor conducts and sinks the sinking current to the LDO circuit when a magnitude of the fluctuation of the output voltage exceeds a magnitude of a voltage corresponding to the threshold signal; and when the fluctuation amplitude of the output voltage is less than or equal to the voltage amplitude corresponding to the threshold signal, closing the pull-down NMOS tube.

3. The transient enhanced LDO circuit of claim 2 wherein the comparator is a current comparator having one input connected to the intermediate stage of the amplifier to receive a current reflecting the fluctuation of the output voltage, the other input connected to a reference current signal, and an output connected to the gate of the pull-down NMOS transistor.

4. The transient enhanced LDO circuit of claim 2 wherein the inverting input of the amplifier is configured to receive the reference voltage, the non-inverting input of the amplifier is coupled to the output of the power regulation tube through the voltage divider, and the output of the amplifier is connected to the gate of the power regulation tube;

the voltage divider is a resistor voltage divider and comprises a first resistor and a second resistor which are connected in series, the source electrode of the power adjusting tube is used for being connected with a voltage source (VDD), and the drain electrode of the power adjusting tube outputs the output voltage and is grounded through the voltage divider;

the drain electrode of the pull-down NMOS tube is coupled to the drain electrode of the power adjusting tube, and the source electrode of the pull-down NMOS tube is grounded.

5. The transient enhanced LDO circuit of claim 4, further comprising a first capacitor and a third resistor in parallel with the voltage divider.

6. The transient enhanced LDO circuit of claim 1 or 2 wherein the amplifier (a1) employs a folded cascode structure.

7. The transient enhanced LDO circuit of claim 6 wherein the amplifier (a1) is an error amplifier comprising: a first PMOS (MP1), a second PMOS (MP2), a third PMOS (MP3), a fourth PMOS (MP4), a fifth PMOS (MP5), a sixth PMOS (MP6), a seventh PMOS (MP7), an eighth PMOS (MP8), a first NMOS (MN1), a second NMOS (MN2), a third NMOS (MN3) and a fourth NMOS (MN 4);

the first PMOS tube (MP1) and the second PMOS tube (MP2) form a differential input pair tube, the grid electrode of the first PMOS tube (MP1) is used as the inverting input end of the error amplifier (A1) and used for receiving a reference voltage, and the grid electrode of the second PMOS tube (MP2) is used as the non-inverting input end of the error amplifier (A1);

the third PMOS tube (MP3) and the fourth PMOS tube (MP4) form a cascode current source, and the drain electrode of the fourth PMOS tube (MP4) is connected to the drain electrode of the first PMOS tube (MP1) and the drain electrode of the second PMOS tube (MP 2);

the first NMOS transistor (MN1), the second NMOS transistor (MN2), the third NMOS transistor (MN3) and the fourth NMOS transistor (MN4) form a cascode current source, the source electrode of the second NMOS transistor (MN2) is connected to the drain electrode of the first NMOS transistor (MN1) and to the drain electrode of the second PMOS transistor (MP2), the source electrode of the fourth NMOS transistor (MN4) is interconnected with the drain electrode of the third NMOS transistor (MN3), is connected to the drain electrode of the first PMOS transistor (MP1), and serves as a first intermediate output end;

a fifth PMOS tube (MP5), a sixth PMOS tube (MP6), a seventh PMOS tube (MP7) and an eighth PMOS tube (MP8) form a cascode current mirror load, and the gates of the fifth PMOS tube (MP5) and the seventh PMOS tube (MP7) are interconnected and connected to the drain of the second NMOS tube (MN2) and used as a second intermediate output end; the gates of the sixth PMOS tube (MP6) and the eighth PMOS tube (MP8) are interconnected and used as a third intermediate output end;

the drains of the eighth PMOS transistor (MP8) and the fourth NMOS transistor (MN4) are interconnected and used as the output end of the error amplifier (A1).

8. The transient enhanced LDO circuit of any of claims 2-5 wherein the comparator comprises: a fifth NMOS transistor (MN5), a sixth NMOS transistor (MN6), a ninth PMOS transistor (MP9) and a tenth PMOS transistor (MP10),

wherein, the fifth NMOS transistor (MN5) and the sixth NMOS transistor (MN6) form a cascode structure and are used as the threshold current end of the current comparator (A3),

the ninth PMOS tube (MP9) and the tenth PMOS tube (MP10) form a cascode structure and are used as a signal current end of the current comparator (A3),

the drain of the tenth PMOS transistor (MP10) is connected to the drain of the sixth NMOS transistor (MN6) and is used to connect to the gate of the pull-down NMOS transistor (MN 0).

9. The transient enhanced LDO circuit of any of claims 1-5 wherein the amplifier has an input to receive a reference voltage for connection to a voltage-type digital-to-analog converter and changes the output voltage of the power regulating tube according to the output of the voltage-type digital-to-analog converter; and/or

The transient enhanced LDO circuit further comprises a buffer connected between the output of the amplifier and the power regulating tube.

10. A power supply circuit for a CMOS driver, comprising:

the transient enhanced LDO circuit of any of claims 1-9; and

a voltage-mode digital-to-analog converter coupled to the transient-enhanced LDO circuit and configured to convert the received digital control input to an analog voltage as a reference voltage for an amplifier (A1) of the transient-enhanced LDO circuit.

11. A laser system comprising the power supply circuit of claim 10, a CMOS driver, a switching tube, and a laser;

the power supply circuit is suitable for providing a driving voltage of the CMOS driver;

one end of the CMOS driver receives the driving voltage, and the other end of the CMOS driver is coupled to the switching tube so as to control the on-off of the switching tube;

and one end of the switching tube is coupled to the CMOS driver and is suitable for modulating the power supply current of the laser.

Technical Field

The present disclosure relates generally to low dropout linear regulators (LDOs), and more particularly, to a transient enhanced LDO circuit, a power supply circuit for a CMOS driver, and a laser system.

Background

Low dropout linear regulator (LDO) has become more and more widely used in portable electronic products due to its advantages of low output noise, low voltage drop, low cost, etc. In high-speed digital circuits regulated by LDO, the dominant frequency is getting higher and higher, even up to several GHz. An instantaneous jump in the level in the digital circuit causes an instantaneous jump in the current. Considering the digital circuit as the load of the LDO, the instantaneous jump of the load current will affect the output voltage of the LDO. The transient response of the LDO includes a linear transient response and a load transient response. The linear transient response refers to the response condition of the output voltage of the LDO when the input voltage has step mutation; the load transient response refers to the output response condition of the LDO when the load current is suddenly changed in step.

With the development of the electronic industry and the progress of the society, there is a continuous need for improving the transient response of the LDO circuit.

Disclosure of Invention

One of the objectives of the technical solutions described in the present disclosure is to provide a transient enhanced LDO circuit, which is capable of improving the transient response of the LDO circuit.

According to an aspect of the present disclosure, there is provided a transient enhanced LDO circuit, comprising: an amplifier, one of the inputs of which may receive a reference voltage; a power regulation tube coupled to an output of the amplifier and outputting an output voltage of the transient enhanced LDO circuit to drive a load; the voltage divider is coupled with the power adjusting tube and couples a terminal of the power adjusting tube, which outputs the output voltage, to the other input end of the amplifier; and the current sinking absorption circuit is coupled to the output voltage of the output voltage output terminals of the amplifier and the power adjusting tube, and conducts and absorbs the current sinking of the output voltage according to the fluctuation of the output voltage.

In one embodiment, the sink current absorption circuit may include a comparator and a pull-down NMOS transistor driven by the comparator, wherein one input terminal of the comparator receives an input signal reflecting the fluctuation of the output voltage, another input terminal of the comparator receives a threshold signal corresponding to the input signal reflecting the fluctuation of the output voltage, the pull-down NMOS transistor is coupled to the output terminal of the power adjustment transistor and the comparator, wherein when the output voltage fluctuates, the pull-down NMOS transistor conducts and absorbs the sink current of the output voltage; and when the output voltage is not fluctuated, the pull-down NMOS tube is closed.

Further, the comparator may be a current comparator, the one input terminal of the comparator is connected to the intermediate stage of the amplifier to receive a current reflecting the fluctuation of the output voltage, the other input terminal is connected to a reference current signal, and the output terminal is connected to the gate of the pull-down NMOS transistor.

Further, the inverting input end of the amplifier is used for connecting a reference voltage, the non-inverting input end of the amplifier is coupled to the output end of the power adjusting tube through the voltage divider, and the output end of the amplifier is connected to the grid electrode of the power adjusting tube through a buffer. The voltage divider is a resistor voltage divider and comprises a first resistor and a second resistor which are connected in series, the source electrode of the power adjusting tube is used for being connected with a voltage source (VDD), and the drain electrode of the power adjusting tube outputs the output voltage and is grounded through the voltage divider. The drain electrode of the pull-down NMOS tube is coupled to the drain electrode of the power adjusting tube, and the source electrode of the pull-down NMOS tube is grounded.

In one embodiment, the transient enhanced LDO circuit may further include a first capacitor and a third resistor connected in parallel with the voltage divider.

Further, the amplifier (a1) may employ a folded cascode structure.

In one embodiment, an amplifier (a1) includes: the transistor comprises a first PMOS (P-channel metal oxide semiconductor) tube (MP1), a second PMOS tube (MP2), a third PMOS tube (MP3), a fourth PMOS tube (MP4), a fifth PMOS tube (MP5), a sixth PMOS tube (MP6), a seventh PMOS tube (MP7), an eighth PMOS tube (MP8), a first NMOS tube (MN1), a second NMOS tube (MN2), a third NMOS tube (MN3) and a fourth NMOS tube (MN 4). The first PMOS tube (MP1) and the second PMOS tube (MP2) form a differential input pair tube, the grid electrode of the first PMOS tube (MP1) is used as the inverting input end of the error amplifier (A1) and used for connecting a reference voltage, and the grid electrode of the second PMOS tube (MP2) is used as the non-inverting input end of the error amplifier (A1). The third PMOS tube (MP3) and the fourth PMOS tube (MP4) form a cascode current source, and the drain electrode of the fourth PMOS tube (MP4) is connected to the drain electrode of the first PMOS tube (MP1) and the drain electrode of the second PMOS tube (MP 2). The first NMOS transistor (MN1), the second NMOS transistor (MN2), the third NMOS transistor (MN3) and the fourth NMOS transistor (MN4) form a cascode current source, the source electrode of the second NMOS transistor (MN2) is connected to the drain electrode of the first NMOS transistor (MN1) and to the drain electrode of the second PMOS transistor (MP2), and the source electrode of the fourth NMOS transistor (MN4) is interconnected with the drain electrode of the third NMOS transistor (MN3), is connected to the drain electrode of the first PMOS transistor (MP1), and serves as a first intermediate output end. A fifth PMOS tube (MP5), a sixth PMOS tube (MP6), a seventh PMOS tube (MP7) and an eighth PMOS tube (MP8) form a cascode current mirror load, and the gates of the fifth PMOS tube (MP5) and the seventh PMOS tube (MP7) are interconnected and connected to the drain of the second NMOS tube (MN2) and used as a second intermediate output end; and the gates of the sixth PMOS tube (MP6) and the eighth PMOS tube (MP8) are interconnected and used as a third intermediate output end. The drains of the eighth PMOS transistor (MP8) and the fourth NMOS transistor (MN4) are interconnected and used as the output end of the error amplifier (A1).

In one embodiment, the comparator may include: a fifth NMOS transistor (MN5), a sixth NMOS transistor (MN6), a ninth PMOS transistor (MP9) and a tenth PMOS transistor (MP 10). The fifth NMOS transistor (MN5) and the sixth NMOS transistor (MN6) form a cascode structure and are used as a threshold current end of the current comparator (A3). The ninth PMOS transistor (MP9) and the tenth PMOS transistor (MP10) form a cascode structure, and serve as signal current terminals of the current comparator (A3). The drain of the tenth PMOS transistor (MP10) is connected to the drain of the sixth NMOS transistor (MN6) and is used to connect to the gate of the pull-down NMOS transistor (MN 0).

In another aspect of the present disclosure, there is also provided a power supply circuit of a CMOS driver, including: the transient enhanced LDO circuit of any of the preceding claims; and a voltage-type digital-to-analog converter, coupled to the LDO circuit, configured to convert the received digital control input to an analog voltage as a reference voltage for an error amplifier (a1) of the LDO circuit.

In yet another aspect of the present disclosure, there is also provided a laser system, comprising: the aforementioned power supply circuit; and a laser connected to the power circuit.

Embodiments of the present disclosure provide a transient enhanced LDO circuit structure that, in combination with a power supply, may be used to power a CMOS driver. The LDO can realize high-speed charge drawing or injection through a large capacitor outside a connecting sheet, and can realize quick recovery of voltage overshoot on an output capacitor of the LDO through a transient response enhancement technology.

The features and advantages described in the specification are not all inclusive and, in particular, many additional features and advantages will be apparent to one of ordinary skill in the art in view of the drawings and specification. Moreover, it should be noted that the terminology used in the description has been chosen primarily for readability and instructional purposes, and may not have been chosen to delineate or circumscribe the inventive subject matter.

Drawings

The accompanying drawings, which are included to provide a further understanding of the disclosure, illustrate embodiments of the disclosure and together with the description serve to explain the disclosure and are not to limit the disclosure. In the drawings:

FIG. 1 schematically shows a block diagram of a transient enhanced LDO circuit according to an embodiment of the present invention;

FIG. 2 is a schematic diagram of a circuit structure of a transient enhanced LDO circuit for powering a CMOS device according to an embodiment of the present invention;

FIG. 3 schematically shows an implementation circuit diagram of a transient enhanced LDO circuit according to an embodiment of the present invention;

FIG. 4 shows a simulation graph of current or voltage at each node according to the circuit shown in FIG. 3;

FIG. 5 shows comparative simulation graphs of current or voltage at various nodes under different parameters according to the circuit shown in FIG. 3; and

fig. 6 shows a laser system according to the invention.

Detailed Description

In the following, only certain exemplary embodiments are briefly described. As those skilled in the art can appreciate, the described embodiments can be modified in various different ways, without departing from the spirit or scope of the present disclosure. Accordingly, the drawings and description are to be regarded as illustrative in nature, and not as restrictive.

Reference will now be made in detail to several embodiments of the invention, examples of which are illustrated in the accompanying drawings. It should be noted that wherever practicable similar or like reference numbers may be used in the figures and may be used to indicate similar or like functionality. The figures depict several embodiments of the present invention for purposes of illustration only. One skilled in the art will readily recognize from the following description that alternative embodiments of the structures and methods illustrated herein may be employed without departing from the principles of the embodiments described herein. The method steps described below are not necessarily performed in the order illustrated, where possible.

The flowchart and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of apparatus, methods and computer program products according to various embodiments of the present invention. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified logical function(s). It should be noted that, in some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems which perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.

In the description of the present disclosure, it is to be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "straight", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", and the like, indicate orientations or positional relationships based on those shown in the drawings, and are only for convenience of description and simplicity of description, but do not indicate or imply that the device or element being referred to must have a particular orientation, be constructed in a particular orientation, and be operated, and therefore should not be considered as limiting the present disclosure. Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, features defined as "first", "second", may explicitly or implicitly include one or more of the described features. In the description of the present disclosure, "a plurality" means two or more unless specifically limited otherwise.

In the description of the present disclosure, it should be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and the like are to be construed broadly and may be, for example, fixedly connected, detachably connected, or integrally connected: may be mechanically connected, may be electrically connected or may be in communication with each other; either directly or indirectly through intervening media, either internally or in any other relationship. The specific meaning of the above terms in the present disclosure can be understood by those of ordinary skill in the art as appropriate. For example, the present disclosure uses the term "coupled" to indicate that the connection between two terminals can be direct connection, indirect connection through an intermediate medium, electrically wired connection, or wireless connection.

In the present disclosure, unless expressly stated or limited otherwise, the first feature "on" or "under" the second feature may comprise the first and second features being in direct contact, or may comprise the first and second features being in contact, not directly, but via another feature in between. Also, the first feature being "on," "above" and "over" the second feature includes the first feature being directly on and obliquely above the second feature, or merely indicating that the first feature is at a higher level than the second feature. A first feature being "under," "below," and "beneath" a second feature includes the first feature being directly above and obliquely above the second feature, or simply meaning that the first feature is at a lesser level than the second feature.

The following disclosure provides many different embodiments or examples for implementing different features of the disclosure. To simplify the disclosure of the present disclosure, specific example components and arrangements are described below. Of course, they are merely examples and are not intended to limit the present disclosure. Moreover, the present disclosure may repeat reference numerals and/or reference letters in the various examples, which have been repeated for purposes of simplicity and clarity and do not in themselves dictate a relationship between the various embodiments and/or arrangements discussed. In addition, the present disclosure provides examples of various specific processes and materials, but one of ordinary skill in the art may recognize applications of other processes and/or use of other materials.

It is to be noted that, unless otherwise specified, technical or scientific terms used in the present disclosure shall have the ordinary meaning as understood by those skilled in the art to which the present invention pertains.

Specific embodiments of the present disclosure are described below in conjunction with the appended drawings, it being understood that the preferred embodiments described herein are merely for purposes of illustrating and explaining the present disclosure and are not intended to limit the present disclosure.