Ultra-low power consumption voltage reference source circuit with adjustable output voltage
阅读说明：本技术 一种输出电压可调的超低功耗电压基准源电路 (Ultra-low power consumption voltage reference source circuit with adjustable output voltage ) 是由 杜凯旋 彭春雨 卢文娟 吴秀龙 蔺智挺 黎轩 高珊 陈军宁 于 2019-11-05 设计创作，主要内容包括：本发明公开了一种输出电压可调的超低功耗电压基准源电路,包括：依次连接的偏置电流模块、阈值电压差产生模块、以及输出电压调节模块；其中：所述偏置电流模块通过NMOS管实现,NMOS管的阈值电压低于设定值,且NMOS管工作在亚阈值区；所述阈值电压差产生模块,采用了NMOS管阈值电压差来产生基准电压；所述输出电压调节模块,通过宽长比调节电路降低输出的基准电压。其具有超低功耗、面积小和输出基准电压可调的优点。(The invention discloses an ultra-low power consumption voltage reference source circuit with adjustable output voltage, which comprises: the bias current module, the threshold voltage difference generation module and the output voltage regulation module are connected in sequence; wherein: the bias current module is realized through an NMOS (N-channel metal oxide semiconductor) tube, the threshold voltage of the NMOS tube is lower than a set value, and the NMOS tube works in a sub-threshold region; the threshold voltage difference generation module generates a reference voltage by adopting the threshold voltage difference of the NMOS tube; and the output voltage regulating module reduces the output reference voltage through the width-to-length ratio regulating circuit. The circuit has the advantages of ultra-low power consumption, small area and adjustable output reference voltage.)
1. An ultra-low power consumption voltage reference source circuit with adjustable output voltage is characterized by comprising: the bias current module, the threshold voltage difference generation module and the output voltage regulation module are connected in sequence; wherein:
the bias current module is realized through an NMOS (N-channel metal oxide semiconductor) tube, the threshold voltage of the NMOS tube is lower than a set value, and the NMOS tube works in a sub-threshold region;
the threshold voltage difference generation module generates a reference voltage by adopting the threshold voltage difference of the NMOS tube;
the output voltage adjusting module adjusts the reference voltage through the width-length-ratio adjustable circuit.
2. The ultra-low power consumption voltage reference source circuit with adjustable output voltage of claim 1, wherein the bias current module is implemented by a first NMOS transistor NM1, a gate of the first NMOS transistor NM1 is grounded, a drain is connected to VDD, a substrate is grounded, and a source is connected to the threshold voltage difference generating module.
3. The ultra-low power consumption voltage reference source circuit with adjustable output voltage of claim 1, wherein the threshold voltage difference generating module comprises: a second NMOS transistor MN2, a third NMOS transistor MN3, and a fourth NMOS transistor MN 4; wherein:
the grid electrode of the second NMOS transistor MN2 is connected with the grid electrodes of the third NMOS transistor MN3 and the fourth NMOS transistor MN4, and then is connected to the drain electrode of the second NMOS transistor MN 2;
the source of the second NMOS transistor MN2, the drain of the third NMOS transistor MN3 and the drain of the fourth NMOS transistor MN4 are connected together to form a reference voltage VrefAn output end;
the substrates of the second NMOS transistor MN2, the third NMOS transistor MN3, and the fourth NMOS transistor MN4 are grounded.
4. The ultra-low power consumption voltage reference source circuit with adjustable output voltage of claim 3, wherein the output voltage adjusting module comprises: a fifth NMOS transistor MN5, a sixth NMOS transistor MN6, and a third NMOS transistor MN3 and a fourth NMOS transistor MN4 in the threshold voltage difference generating module; wherein:
the fifth NMOS transistor MN5 and the sixth NMOS transistor MN6 are both switching transistors;
the source electrode of the third NMOS transistor MN3 is connected with the drain electrode of the fifth NMOS transistor MN 5; the source electrode of the fourth NMOS transistor MN4 is connected with the drain electrode of the sixth NMOS transistor MN 6;
the grid electrode of the fifth NMOS tube MN5 is connected with the external input S0; the gate of the sixth NMOS transistor MN6 is connected to the external input S1; the values of the output reference voltages are controlled by S0 and S1;
the sources and the substrate of the fifth NMOS transistor MN5 and the sixth NMOS transistor MN6 are grounded.
5. The ultra-low power consumption voltage reference source circuit with adjustable output voltage according to claim 4,
when S0 is low and S1 is high, i.e. only the fourth NMOS transistor MN4 is active, the output reference voltage V isrefIs the gate-source voltage V of the fourth NMOS transistor MN4GS4Minus the gate-source voltage V of the second NMOS transistor MN2GS2Then the reference voltage VrefExpressed as:
wherein η is the subthreshold slope factor, VTIs a thermal voltage, k4Is the width-to-length ratio, k, of the fourth NMOS transistor MN42Is the width-to-length ratio, DeltaV, of the second NMOS transistor MN2TH＝VTH4-VTH2，VTH4、VTH2Threshold voltages of the fourth NMOS transistor MN4 and the second NMOS transistor MN2 respectively;
similarly, when the voltages S0 and S1 are simultaneously high, the third NMOS transistor MN3 is connected in parallel with the fourth NMOS transistor MN4, and the width-to-length ratio of the parallel connection becomes half of that of the fourth NMOS transistor MN4, so that the output reference voltage V is outputrefAnd (4) descending.
Technical Field
The invention relates to the technical field of integrated circuits, in particular to an ultra-low power consumption voltage reference source circuit with adjustable output voltage.
Background
The voltage reference circuit is an indispensable part of all electronic systems, and in the fields of internet of things and most wireless communication, because the system is powered by a battery or self-powered, the requirement of the system on power consumption is very high, and the development of a module with ultra-low power consumption is urgent. The traditional reference source circuit uses a bipolar transistor to provide reference voltage and has the defects of large area and high power consumption.
In recent years, field effect transistors operating in a sub-threshold region have been used instead of bipolar transistors in order to reduce power consumption. The threshold voltage of the field effect transistor is greatly influenced along with the process, and the reference voltage is inaccurate when the threshold voltage is directly applied to a circuit, so that the output reference voltage needs to be adjusted according to actual requirements.
Disclosure of Invention
The invention aims to provide an ultra-low power consumption voltage reference source circuit with adjustable output voltage, which has the advantages of ultra-low power consumption, small area and adjustable output reference voltage.
The purpose of the invention is realized by the following technical scheme:
an ultra-low power consumption voltage reference source circuit with adjustable output voltage comprises: the bias current module, the threshold voltage difference generation module and the output voltage regulation module are connected in sequence; wherein:
the bias current module is realized through an NMOS (N-channel metal oxide semiconductor) tube, the threshold voltage of the NMOS tube is lower than a set value, and the NMOS tube works in a sub-threshold region;
the threshold voltage difference generation module generates a reference voltage by adopting the threshold voltage difference of the NMOS tube;
the output voltage adjusting module adjusts the reference voltage through the width-length-ratio adjustable circuit.
According to the technical scheme provided by the invention, 1) the NMOS tube of the bias current module works in a subthreshold region, so that the whole working current is only nano-ampere level; 2) in order to reduce the influence of the process on the threshold voltage of the low-threshold NMOS tube, the threshold voltage difference generation module generates the reference voltage by adopting the threshold voltage difference of the NMOS tube instead of the threshold voltage, so that the influence of the process is counteracted; 3) the core of the output voltage adjustable module is a width-length ratio adjusting circuit which can adjust the reference voltage. 4) Because the circuit is composed of NMOS tubes, passive devices such as resistors and capacitors are not used, and the area is greatly saved.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on the drawings without creative efforts.
Fig. 1 is a schematic structural diagram of an ultra-low power consumption voltage reference source circuit with adjustable output voltage according to an embodiment of the present invention;
FIG. 2 is a graph of output reference voltage as a function of supply voltage provided by an embodiment of the present invention;
fig. 3 is a graph of the output reference voltage varying with temperature according to an embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention are clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments of the present invention without making any creative effort, shall fall within the protection scope of the present invention.
The embodiment of the invention provides an ultra-low power consumption voltage reference source circuit with adjustable output voltage, as shown in fig. 1, which mainly comprises: the device comprises a bias current module, a threshold voltage difference generation module and an output voltage regulation module which are connected in sequence.
1. A bias current module.
In the embodiment of the invention, the bias current module is realized by an NMOS (N-channel metal oxide semiconductor) tube, the threshold voltage of the NMOS tube is lower than a set value, and the NMOS tube works in a sub-threshold region.
As shown in fig. 1, the first NMOS transistor NM1 constitutes a bias current module, the gate of the first NMOS transistor NM1 is grounded, the drain is connected to VDD, the substrate is grounded, and the source is connected to a threshold voltage difference generation module, specifically, the source is connected to the drain of the second NMOS transistor MN 2.
The first NMOS transistor NM1 is a low threshold voltage, which is only tens of millivolts for example, so that the first NMOS transistor NM1 can be guaranteed to operate in the sub-threshold region even if the gate of the first NMOS transistor NM1 is grounded. The current I thus generatedDOnly of nanoampere grade.
2. And a threshold voltage difference generation module.
In the embodiment of the invention, the threshold voltage difference generation module generates the reference voltage by adopting the threshold voltage difference of the NMOS tube.
As shown in fig. 1, the threshold voltage difference generating module mainly includes: a second NMOS transistor MN2, a third NMOS transistor MN3, and a fourth
the grid electrode of the second NMOS transistor MN2 is connected with the grid electrodes of the third NMOS transistor MN3 and the fourth NMOS transistor MN4, and then is connected to the drain electrode of the second NMOS transistor MN 2;
the source of the second NMOS transistor MN2, the drain of the third NMOS transistor MN3 and the drain of the fourth NMOS transistor MN4 are connected together to form a reference voltage VrefAn output end;
the substrates of the second NMOS transistor MN2, the third NMOS transistor MN3, and the fourth NMOS transistor MN4 are grounded.
For example, the second NMOS transistor MN2 is a low-threshold-voltage NMOS transistor, and the third NMOS transistor MN3 and the fourth NMOS transistor MN4 are medium-threshold-voltage NMOS transistors; the low threshold and the medium threshold are both threshold standards set by a user.
3. Output voltage regulating module
The output voltage adjusting module adjusts the reference voltage through the width-length-ratio adjustable circuit.
As shown in fig. 1, the output voltage regulating module includes: a fifth NMOS transistor MN5, a sixth NMOS transistor MN6, and a third NMOS transistor MN3 and a fourth NMOS transistor MN4 in the threshold voltage difference generating module; wherein:
the fifth NMOS transistor MN5 and the sixth NMOS transistor MN6 are both switching transistors;
the source electrode of the third NMOS transistor MN3 is connected with the drain electrode of the fifth NMOS transistor MN 5; the source electrode of the fourth NMOS transistor MN4 is connected with the drain electrode of the sixth NMOS transistor MN 6;
the grid electrode of the fifth NMOS tube MN5 is connected with the external input S0; the gate of the sixth NMOS transistor MN6 is connected to the external input S1; the values of the output reference voltages are controlled by S0 and S1;
the sources and the substrate of the fifth NMOS transistor MN5 and the sixth NMOS transistor MN6 are grounded.
The above mainly describes the composition and structure of the circuit, and the following description is directed to the working principle.
As shown in fig. 1, when S0 is low (S0 is 0) and S1 is high (S1 is 1), that is, only the fourth NMOS transistor MN4 is active, the output reference voltage V is outputrefIs the gate-source voltage V of the fourth NMOS transistor MN4GS4Minus the gate-source voltage V of the second NMOS transistor MN2GS2Then the reference voltage VrefExpressed as:
wherein η is the subthreshold slope factor, VTIs a thermal voltage, k4Is the width-to-length ratio, k, of the fourth NMOS transistor MN42Is the width-to-length ratio, DeltaV, of the second NMOS transistor MN2TH＝VTH4-VTH2，VTH4、VTH2Threshold voltages of the fourth NMOS transistor MN4 and the second NMOS transistor MN2 respectively; due to VTH4、VTH2Has a negative temperature coefficient, and VTHas positive temperature coefficient, so that the reference voltage independent of temperature can be obtained by adjusting the size of the NMOS tube.
Similarly, when S0 and S1 are both high (S0 is equal to 1)And S1 is 1), the third NMOS transistor MN3 and the fourth NMOS transistor MN4 are connected in parallel, and the width-to-length ratio after parallel connection becomes half of the fourth NMOS transistor MN4, so that the output reference voltage V is outputrefAnd (4) descending.
As shown in FIG. 2, the reference voltage (V) is outputref) Graph of variation with supply Voltage (VDD). The provided reference source can work at the lowest voltage of 0.3V, and only generates 4mV change within 0.3-1.8V.
As shown in fig. 3, is a graph of the output reference voltage as a function of temperature (T). The temperature coefficient of the reference source circuit is 30.8 ppm/DEG C within the range of-40 to 85 ℃.
The above description is only for the preferred embodiment of the present invention, but the scope of the present invention is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present invention are included in the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.
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