阅读说明：本技术 一种低压差稳压电路及其方法 (Low dropout voltage regulator circuit and method thereof ) 是由 曹魏栋 蒋祥顺 曾毅 钱哲弘 于 2019-11-14 设计创作，主要内容包括：本发明提供一种低压差稳压电路及其方法,所述电路包括：偏置电压产生电路,用于产生偏置电压,并基于RC滤波实现低输出噪声的偏置电压输出；稳压环路输出电路,连接于偏置电压产生电路,用于根据偏置电压产生输出电压,并在负载电流发生变化时,基于稳压环路输出电路中的反馈环路对输出电压进行调节,以保持输出电压恒定不变；PSRR补偿电路,连接于稳压环路输出电路,用于采集电源上的扰动,并将采集的扰动信号处理后反馈至稳压环路输出电路中连接于电源电压和电压输出节点之间MOS管的栅极端,以使该MOS管的源极端和栅极端同步变化,实现PSRR补偿。通过本发明解决了现有LDO电路无法同时满足低输出噪声和高PSRR的问题。(The invention provides a low dropout voltage regulator circuit and a method thereof, wherein the circuit comprises: the bias voltage generating circuit is used for generating bias voltage and realizing bias voltage output with low output noise based on RC filtering; the voltage stabilizing loop output circuit is connected with the bias voltage generating circuit and used for generating output voltage according to the bias voltage and regulating the output voltage based on a feedback loop in the voltage stabilizing loop output circuit when the load current changes so as to keep the output voltage constant; and the PSRR compensation circuit is connected to the voltage stabilizing loop output circuit and used for collecting disturbance on a power supply and feeding back the collected disturbance signal after processing to the grid terminal of an MOS (metal oxide semiconductor) tube connected between a power supply voltage and a voltage output node in the voltage stabilizing loop output circuit so as to ensure that the source terminal and the grid terminal of the MOS tube synchronously change and realize PSRR compensation. The invention solves the problem that the existing LDO circuit can not meet the requirements of low output noise and high PSRR at the same time.)

1. The low dropout voltage regulator circuit comprises:

the bias voltage generating circuit is used for generating bias voltage and realizing bias voltage output with low output noise based on RC filtering;

the voltage stabilizing loop output circuit is connected with the bias voltage generating circuit and used for generating output voltage according to the bias voltage and regulating the output voltage based on a feedback loop in the voltage stabilizing loop output circuit when the load current changes so as to keep the output voltage constant;

and the PSRR compensation circuit is connected with the voltage stabilizing loop output circuit and used for collecting disturbance on a power supply and feeding back the collected disturbance signal after processing to the grid terminal of an MOS (metal oxide semiconductor) tube connected between a power supply voltage and a voltage output node in the voltage stabilizing loop output circuit so as to ensure that the source terminal and the grid terminal of the MOS tube are synchronously changed, thereby realizing PSRR compensation.

2. The low dropout voltage regulator circuit of claim 1, wherein the bias voltage generating circuit comprises: the MOS transistor comprises a first MOS transistor, a second MOS transistor, a third MOS transistor, a fourth MOS transistor, a fifth MOS transistor, a sixth MOS transistor, a seventh MOS transistor, a first resistor, a second resistor, a third resistor, a fourth resistor, a first capacitor, a second capacitor and a third capacitor; wherein the content of the first and second substances,

the source terminal of the first MOS transistor is connected to a power supply voltage, the drain terminal of the first MOS transistor is connected to the gate terminal of the first MOS transistor, the drain terminal of the second MOS transistor, the gate terminal of the third MOS transistor and one terminal of the first resistor in common, the gate terminal of the second MOS transistor is connected to a first reference voltage, the source terminal of the second MOS transistor is grounded, the source terminal of the third MOS transistor is connected to the power supply voltage, the drain terminal of the third MOS transistor is connected to the drain terminal of the fourth MOS transistor, the gate terminal of the fourth MOS transistor and one terminal of the second resistor in common, the source terminal of the fourth MOS transistor is connected to one terminal of the fourth resistor, the other terminal of the fourth resistor is grounded, the other terminal of the first resistor is connected to one terminal of the first capacitor and the gate terminal of the fifth MOS transistor in common and serves as a first output node of the bias voltage generating circuit, the other end of the first capacitor is connected with a power supply voltage, the other end of the second resistor is connected with one end of the second capacitor, and is used as a second output node of the bias voltage generating circuit, the other end of the second capacitor is grounded, the source terminal of the fifth MOS tube is connected with power supply voltage, the drain terminal of the fifth MOS tube is connected with the source terminal of the sixth MOS tube, and a second reference voltage is connected, the drain terminal of the sixth MOS transistor is connected with the gate terminal of the sixth MOS transistor, the drain terminal of the seventh MOS transistor and one end of the third resistor, the grid end of the seventh MOS tube is connected with the first reference voltage, the source end of the seventh MOS tube is grounded, the other end of the third resistor is connected with one end of the third capacitor, the other end of the third capacitor is grounded; the first MOS transistor, the third MOS transistor, the fifth MOS transistor and the sixth MOS transistor are PMOS transistors, and the second MOS transistor, the fourth MOS transistor and the seventh MOS transistor are NMOS transistors.

3. The low dropout voltage regulator circuit of claim 1, wherein the regulator loop output circuit comprises: the eighth MOS tube, the ninth MOS tube, the tenth MOS tube, the eleventh MOS tube and the fifth resistor are connected in series; wherein the content of the first and second substances,

the gate terminal of the eighth MOS transistor is connected to the first output node of the bias voltage generating circuit, the source terminal of the eighth MOS tube is connected with a power supply voltage, the drain terminal of the eighth MOS tube is connected with the drain terminal of the ninth MOS tube and the gate terminal of the tenth MOS tube, and is used as a feedback node of the voltage stabilizing loop output circuit, the gate terminal of the ninth MOS transistor is connected with the second output node of the bias voltage generating circuit, the source terminal of the ninth MOS transistor is commonly connected with the drain terminal of the eleventh MOS transistor and one terminal of the fifth resistor, the other end of the fifth resistor is grounded, the source terminal of the tenth MOS transistor is connected with a power supply voltage, the drain terminal of the tenth MOS transistor is connected with the source terminal of the eleventh MOS transistor, the gate end of the eleventh MOS tube is connected to the third output node of the bias voltage generating circuit; the ninth MOS transistor, the tenth MOS transistor, the eleventh MOS transistor and the fifth resistor form a feedback loop, the eighth MOS transistor, the tenth MOS transistor and the eleventh MOS transistor are PMOS transistors, and the ninth MOS transistor is an NMOS transistor.

4. The low dropout voltage regulator circuit of claim 1, wherein the PSRR compensation circuit comprises: a twelfth MOS tube, a thirteenth MOS tube, a fourteenth MOS tube, a fifteenth MOS tube, a sixth resistor, a seventh resistor, an eighth resistor, a fourth capacitor and a fifth capacitor; wherein the content of the first and second substances,

a source terminal of the twelfth MOS tube is connected with a power supply voltage, a drain terminal of the twelfth MOS tube is connected with a gate terminal of the twelfth MOS tube, a drain terminal of the thirteenth MOS tube and one end of the sixth resistor in common, a gate terminal of the thirteenth MOS tube is connected with the first reference voltage, a source terminal of the thirteenth MOS tube is grounded, the other end of the sixth resistor is connected with one end of the fourth capacitor and a gate terminal of the fourteenth MOS tube in common, the other end of the fourth capacitor is grounded, a source terminal of the fourteenth MOS tube is connected with the power supply voltage, a drain terminal of the fourteenth MOS tube is connected with a source terminal of the fifteenth MOS tube and one end of the fifth capacitor in common, the other end of the fifth capacitor is connected with a feedback node of the voltage stabilizing loop output circuit, a drain terminal of the fifteenth MOS tube is grounded, a gate terminal of the fifteenth MOS tube is connected with one end of the seventh resistor and one end of the eighth resistor in common, the other end of the seventh resistor is connected to a voltage output node of the voltage stabilizing loop output circuit, and the other end of the eighth resistor is grounded; the twelfth MOS tube, the fourteenth MOS tube and the fifteenth MOS tube are PMOS tubes, and the thirteenth MOS tube is an NMOS tube.

5. A low dropout voltage stabilizing circuit according to any one of claims 1 to 4, wherein the low dropout voltage stabilizing method comprises:

generating the bias voltage through the bias voltage generating circuit, and realizing the bias voltage output with low output noise based on RC filtering;

generating the output voltage through the voltage stabilizing loop output circuit, and regulating the output voltage based on a feedback loop in the voltage stabilizing loop output circuit when the load current changes so as to keep the output voltage constant;

the PSRR compensation circuit is used for collecting disturbance on a power supply, processing a collected disturbance signal and feeding the processed disturbance signal back to the grid terminal of an MOS (metal oxide semiconductor) tube connected between a power supply voltage and a voltage output node in the voltage stabilizing loop output circuit, so that the source terminal and the grid terminal of the MOS tube are synchronously changed, and the PSRR compensation is realized.

6. The low dropout regulation method of claim 5 wherein in order to keep the output voltage constantly equal to the second reference voltage, R4-N R5,

7. The low dropout voltage stabilization method according to claim 5, wherein, in order to realize low output noise of the output voltage, the width-to-length ratio of the eighth MOS transistor is 55 μm/0.5 μm to 65 μm/0.5 μm, the width-to-length ratio of the ninth MOS transistor is 90 μm/0.2 μm to 120 μm/0.2 μm, the width-to-length ratio of the tenth MOS transistor is 2.6mm/0.07 μm to 3mm/0.07 μm, and the width-to-length ratio of the eleventh MOS transistor is 750 μm/0.1 μm to 780 μm/0.1 μm.

8. The low dropout voltage stabilizing method according to claim 7, wherein the quiescent current of the branch in which the eighth MOS transistor and the ninth MOS transistor are located is 5 μ Α to 10 μ Α, and the quiescent current of the branch in which the tenth MOS transistor and the eleventh MOS transistor are located is 50 μ Α to 70 μ Α.

9. The low dropout regulation method of claim 5 wherein the fourteenth MOS transistor and the fifteenth MOS transistor have a width to length ratio of 1:1 in order to achieve source and gate terminals of the MOS transistor connected between the power supply voltage and the voltage output node to vary synchronously.

Technical Field

The invention belongs to the field of integrated circuits, and particularly relates to a low dropout voltage regulator circuit and a method thereof.

Background

The power management circuit is widely applied to various portable electronic devices, along with the improvement of the integration level of a chip, a plurality of on-chip voltage regulators are mostly adopted in a single-chip SOC, and the voltage regulators can be direct current-to-direct current power supplies DCDC or low dropout regulators LDO; the LDO can independently supply power for each submodule, the power supply scheme can meet the noise voltage requirement of the submodule, meanwhile, the circuit performance of the submodule can be optimized through a customized power supply, and crosstalk from the power supply among different modules is reduced.

In order to improve efficiency, the power of the LDO is usually derived from DCDC, and the output of the DCDC usually has ripples with different frequency bands, which puts high requirements on PSRR (power supply voltage rejection ratio) of the LDO. On the other hand, in order to reduce the system cost and off-chip devices, the low output noise and high PSRR performance of the LDO usually employ internal compensation, which also increases the difficulty of circuit design.

In the existing LDO application system, especially in the Internet of things transceiver system, the submodule puts higher requirements on the noise performance and PSRR performance of the LDO; the conventional LDO circuit structure cannot simultaneously meet low output noise and high PSRR, and PSRR is more obviously deteriorated especially when the frequency is required to reach 1 MHz.

Disclosure of Invention

In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide a low dropout voltage regulator and a method thereof, which are used to solve the problem that the conventional LDO circuit cannot satisfy both low output noise and high PSRR.

To achieve the above and other related objects, the present invention provides a low dropout voltage regulator circuit, including:

the bias voltage generating circuit is used for generating bias voltage and realizing bias voltage output with low output noise based on RC filtering;

the voltage stabilizing loop output circuit is connected with the bias voltage generating circuit and used for generating output voltage according to the bias voltage and regulating the output voltage based on a feedback loop in the voltage stabilizing loop output circuit when the load current changes so as to keep the output voltage constant;

and the PSRR compensation circuit is connected with the voltage stabilizing loop output circuit and used for collecting disturbance on a power supply and feeding back the collected disturbance signal after processing to the grid terminal of an MOS (metal oxide semiconductor) tube connected between a power supply voltage and a voltage output node in the voltage stabilizing loop output circuit so as to ensure that the source terminal and the grid terminal of the MOS tube are synchronously changed, thereby realizing PSRR compensation.

Optionally, the bias voltage generating circuit includes: the MOS transistor comprises a first MOS transistor, a second MOS transistor, a third MOS transistor, a fourth MOS transistor, a fifth MOS transistor, a sixth MOS transistor, a seventh MOS transistor, a first resistor, a second resistor, a third resistor, a fourth resistor, a first capacitor, a second capacitor and a third capacitor; wherein the content of the first and second substances,

the source terminal of the first MOS transistor is connected to a power supply voltage, the drain terminal of the first MOS transistor is connected to the gate terminal of the first MOS transistor, the drain terminal of the second MOS transistor, the gate terminal of the third MOS transistor and one terminal of the first resistor in common, the gate terminal of the second MOS transistor is connected to a first reference voltage, the source terminal of the second MOS transistor is grounded, the source terminal of the third MOS transistor is connected to the power supply voltage, the drain terminal of the third MOS transistor is connected to the drain terminal of the fourth MOS transistor, the gate terminal of the fourth MOS transistor and one terminal of the second resistor in common, the source terminal of the fourth MOS transistor is connected to one terminal of the fourth resistor, the other terminal of the fourth resistor is grounded, the other terminal of the first resistor is connected to one terminal of the first capacitor and the gate terminal of the fifth MOS transistor in common and serves as a first output node of the bias voltage generating circuit, the other end of the first capacitor is connected with a power supply voltage, the other end of the second resistor is connected with one end of the second capacitor, and is used as a second output node of the bias voltage generating circuit, the other end of the second capacitor is grounded, the source terminal of the fifth MOS tube is connected with power supply voltage, the drain terminal of the fifth MOS tube is connected with the source terminal of the sixth MOS tube, and a second reference voltage is connected, the drain terminal of the sixth MOS transistor is connected with the gate terminal of the sixth MOS transistor, the drain terminal of the seventh MOS transistor and one end of the third resistor, the grid end of the seventh MOS tube is connected with the first reference voltage, the source end of the seventh MOS tube is grounded, the other end of the third resistor is connected with one end of the third capacitor, the other end of the third capacitor is grounded; the first MOS transistor, the third MOS transistor, the fifth MOS transistor and the sixth MOS transistor are PMOS transistors, and the second MOS transistor, the fourth MOS transistor and the seventh MOS transistor are NMOS transistors.

Optionally, the regulator loop output circuit includes: the eighth MOS tube, the ninth MOS tube, the tenth MOS tube, the eleventh MOS tube and the fifth resistor are connected in series; wherein the content of the first and second substances,

the gate terminal of the eighth MOS transistor is connected to the first output node of the bias voltage generating circuit, the source terminal of the eighth MOS tube is connected with a power supply voltage, the drain terminal of the eighth MOS tube is connected with the drain terminal of the ninth MOS tube and the gate terminal of the tenth MOS tube, and is used as a feedback node of the voltage stabilizing loop output circuit, the gate terminal of the ninth MOS transistor is connected with the second output node of the bias voltage generating circuit, the source terminal of the ninth MOS transistor is commonly connected with the drain terminal of the eleventh MOS transistor and one terminal of the fifth resistor, the other end of the fifth resistor is grounded, the source terminal of the tenth MOS transistor is connected with a power supply voltage, the drain terminal of the tenth MOS transistor is connected with the source terminal of the eleventh MOS transistor, the gate end of the eleventh MOS tube is connected to the third output node of the bias voltage generating circuit; the ninth MOS transistor, the tenth MOS transistor, the eleventh MOS transistor and the fifth resistor form a feedback loop, the eighth MOS transistor, the tenth MOS transistor and the eleventh MOS transistor are PMOS transistors, and the ninth MOS transistor is an NMOS transistor.

Optionally, the PSRR compensation circuit comprises: a twelfth MOS tube, a thirteenth MOS tube, a fourteenth MOS tube, a fifteenth MOS tube, a sixth resistor, a seventh resistor, an eighth resistor, a fourth capacitor and a fifth capacitor; wherein the content of the first and second substances,

a source terminal of the twelfth MOS tube is connected with a power supply voltage, a drain terminal of the twelfth MOS tube is connected with a gate terminal of the twelfth MOS tube, a drain terminal of the thirteenth MOS tube and one end of the sixth resistor in common, a gate terminal of the thirteenth MOS tube is connected with the first reference voltage, a source terminal of the thirteenth MOS tube is grounded, the other end of the sixth resistor is connected with one end of the fourth capacitor and a gate terminal of the fourteenth MOS tube in common, the other end of the fourth capacitor is grounded, a source terminal of the fourteenth MOS tube is connected with the power supply voltage, a drain terminal of the fourteenth MOS tube is connected with a source terminal of the fifteenth MOS tube and one end of the fifth capacitor in common, the other end of the fifth capacitor is connected with a feedback node of the voltage stabilizing loop output circuit, a drain terminal of the fifteenth MOS tube is grounded, a gate terminal of the fifteenth MOS tube is connected with one end of the seventh resistor and one end of the eighth resistor in common, the other end of the seventh resistor is connected to a voltage output node of the voltage stabilizing loop output circuit, and the other end of the eighth resistor is grounded; the twelfth MOS tube, the fourteenth MOS tube and the fifteenth MOS tube are PMOS tubes, and the thirteenth MOS tube is an NMOS tube.

The invention also provides a low dropout voltage stabilizing method realized by using the low dropout voltage stabilizing circuit, which comprises the following steps:

generating the bias voltage through the bias voltage generating circuit, and realizing the bias voltage output with low output noise based on RC filtering;

generating the output voltage through the voltage stabilizing loop output circuit, and regulating the output voltage based on a feedback loop in the voltage stabilizing loop output circuit when the load current changes so as to keep the output voltage constant;

the PSRR compensation circuit is used for collecting disturbance on a power supply, processing a collected disturbance signal and feeding the processed disturbance signal back to the grid terminal of an MOS (metal oxide semiconductor) tube connected between a power supply voltage and a voltage output node in the voltage stabilizing loop output circuit, so that the source terminal and the grid terminal of the MOS tube are synchronously changed, and the PSRR compensation is realized.

Optionally, in order to make the output voltage constantly equal to the second reference voltage, R4-N R5,

wherein

Is the width-to-length ratio of the first MOS transistor,is the width-to-length ratio of the second MOS transistor,

is the width-to-length ratio of the third MOS transistor,

is the width-to-length ratio of the fourth MOS transistor,

is the width-to-length ratio of the fifth MOS transistor,is the width-to-length ratio of the sixth MOS transistor,

is the width-to-length ratio of the seventh MOS transistor,

is the width-to-length ratio of the ninth MOS transistor,

the width-length ratio of the eleventh MOS transistor is shown, R4 is the resistance value of the fourth resistor, R5 is the resistance value of the fifth resistor, N is the ratio multiple of the fourth resistor to the fifth resistor, and M is the ratio multiple of the width-length ratio of the ninth MOS transistor to the width-length ratio of the fourth MOS transistor.

Optionally, in order to achieve low output noise of the output voltage, the width-to-length ratio of the eighth MOS transistor is 55 μm/0.5 μm to 65 μm/0.5 μm, the width-to-length ratio of the ninth MOS transistor is 90 μm/0.2 μm to 120 μm/0.2 μm, the width-to-length ratio of the tenth MOS transistor is 2.6mm/0.07 μm to 3mm/0.07 μm, and the width-to-length ratio of the eleventh MOS transistor is 750 μm/0.1 μm to 780 μm/0.1 μm.

Optionally, the quiescent current of the branch where the eighth MOS transistor and the ninth MOS transistor are located is 5 μ a to 10 μ a, and the quiescent current of the branch where the tenth MOS transistor and the eleventh MOS transistor are located is 50 μ a to 70 μ a.

Optionally, in order to realize that the source terminal and the gate terminal of the MOS transistor connected between the power voltage and the voltage output node are changed synchronously, the width-to-length ratio of the fourteenth MOS transistor and the fifteenth MOS transistor is 1: 1.

As described above, according to the low dropout voltage regulator circuit and the method thereof of the present invention, the bias voltage is generated by the bias voltage generating circuit, and the output of the bias voltage with low output noise is realized based on the RC filter; then, generating an output voltage through the voltage stabilizing loop output circuit, and regulating the output voltage based on a feedback loop in the voltage stabilizing loop output circuit when the load current changes so as to keep the output voltage constant; meanwhile, the PSRR compensation circuit is used for collecting disturbance on a power supply, and the collected disturbance signal is processed and fed back to the grid terminal of an MOS (metal oxide semiconductor) tube connected between a power supply voltage and a voltage output node in the voltage stabilizing loop output circuit, so that the source terminal and the grid terminal of the MOS tube are synchronously changed, and PSRR compensation is realized; therefore, the low-dropout voltage stabilizing circuit and the method thereof realize high PSRR and low output noise while realizing linear voltage-stabilizing output of the voltage through the design of the bias voltage generating circuit, the voltage-stabilizing loop output circuit and the PSRR compensating circuit.

Drawings

FIG. 1 is a block diagram of a low dropout voltage regulator circuit according to the present invention.

Fig. 2 is a specific circuit diagram of the bias voltage generating circuit according to the present invention.

Fig. 3 is a specific circuit diagram of the output circuit of the regulator loop according to the present invention.

Fig. 4 is a specific circuit diagram of the PSRR compensation circuit according to the present invention.

FIG. 5 is a specific circuit diagram of the low dropout voltage regulator circuit according to the present invention.

Description of the element reference numerals

100 low dropout voltage stabilizing circuit

101 bias voltage generating circuit

102 voltage-stabilizing loop output circuit

103 PSRR compensating circuit

Detailed Description

The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.

Please refer to fig. 1 to 5. It should be noted that the drawings provided in the present embodiment are only schematic and illustrate the basic idea of the present invention, and although the drawings only show the components related to the present invention and are not drawn according to the number, shape and size of the components in actual implementation, the form, quantity and proportion of the components in actual implementation may be changed arbitrarily, and the layout of the components may be more complicated.

As shown in fig. 1, the present embodiment provides a low dropout voltage stabilizing circuit 100, which includes:

a bias voltage generating circuit 101 for generating a bias voltage and outputting the bias voltage with low output noise based on RC filtering;

a voltage stabilizing loop output circuit 102, connected to the bias voltage generating circuit 101, for generating an output voltage according to the bias voltage, and adjusting the output voltage based on a feedback loop in the voltage stabilizing loop output circuit when a load current changes, so as to keep the output voltage constant;

and the PSRR compensation circuit 103 is connected to the voltage stabilization loop output circuit 102, and is configured to collect disturbance on a power supply, process the collected disturbance signal, and feed back the processed disturbance signal to a gate terminal of an MOS transistor connected between a power supply voltage and a voltage output node in the voltage stabilization loop output circuit, so that a source terminal and a gate terminal of the MOS transistor change synchronously, thereby implementing PSRR compensation.

As an example, as shown in fig. 2, the bias voltage generating circuit 101 includes: a first MOS transistor M1, a second MOS transistor M2, a third MOS transistor M3, a fourth MOS transistor M4, a fifth MOS transistor M5, a sixth MOS transistor M6, a seventh MOS transistor M7, a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a first capacitor C1, a second capacitor C2 and a third capacitor C3; wherein the content of the first and second substances,

a source terminal of the first MOS transistor M1 is connected to a power supply voltage VDD, a drain terminal of the first MOS transistor M1 is connected to a gate terminal of the first MOS transistor M1, a drain terminal of the second MOS transistor M2, a gate terminal of the third MOS transistor M3 and one end of the first resistor R1 in common, a gate terminal of the second MOS transistor M2 is connected to a first reference voltage VB, a source terminal of the second MOS transistor M2 is connected to ground VSS, a source terminal of the third MOS transistor M3 is connected to the power supply voltage VDD, a drain terminal of the third MOS transistor M3 is connected to a drain terminal of the fourth MOS transistor M4, a gate terminal of the fourth MOS transistor M4 and one end of the second resistor R2 in common, a source terminal of the fourth MOS transistor M4 is connected to one end of the fourth resistor R4, the other end of the fourth resistor R4 is connected to ground, and the other end of the first resistor R1 is connected to one end of the first capacitor C1 and the gate terminal of the fifth MOS transistor M5 in common, the other end of the first capacitor C1 is connected to a power supply voltage VDD, the other end of the second resistor R2 is connected to one end of the second capacitor C2 and serves as a second output node V2 of the bias voltage generating circuit 101, the other end of the second capacitor C2 is connected to a VSS, the source terminal of the fifth MOS tube M5 is connected to the power supply voltage VDD, the drain terminal of the fifth MOS tube M5 is connected to the source terminal of the sixth MOS tube M6 and is connected to a second reference voltage VREF, the drain terminal of the sixth MOS tube M6 is connected to the gate terminal of the sixth MOS tube M6, the drain terminal of the seventh MOS tube M7 and one end of the third resistor R3, the gate terminal of the seventh MOS tube M7 is connected to the first reference voltage VB, the drain terminal of the seventh MOS tube M7 is connected to the ground, and the other end of the third resistor R3 is connected to one end of the third capacitor C3, and as a third output node V3 of the bias voltage generating circuit 101, the other end of the third capacitor C3 is grounded VSS; the first MOS transistor M1, the third MOS transistor M3, the fifth MOS transistor M5 and the sixth MOS transistor M6 are PMOS transistors, and the second MOS transistor M2, the fourth MOS transistor M4 and the seventh MOS transistor M7 are NMOS transistors.

As shown in fig. 2, the present example achieves low noise output of the voltage in the bias voltage generating circuit 101 by performing RC filtering at each output node of the bias voltage generating circuit 101, such as RC filtering at a first output node V1 through R1/C1, RC filtering at a second output node V2 through R2/C2, and RC filtering at a third output node V3 through R3/C3, to eliminate most of the noise, particularly high frequency noise, of the bias voltage and current at each output node.

As an example, as shown in fig. 3, the regulator loop output circuit 102 includes: an eighth MOS transistor M8, a ninth MOS transistor M9, a tenth MOS transistor M10, an eleventh MOS transistor M11, and a fifth resistor R5; wherein the content of the first and second substances,

a gate terminal of the eighth MOS transistor M8 is connected to the first output node V1 of the bias voltage generating circuit 101, a source terminal of the eighth MOS transistor M8 is connected to the power supply voltage VDD, a drain terminal of the eighth MOS transistor M8 is commonly connected to a drain terminal of the ninth MOS transistor M9 and a gate terminal of the tenth MOS transistor M10 and serves as a feedback node V4 of the regulator loop output circuit 102, a gate terminal of the ninth MOS transistor M9 is connected to the second output node V2 of the bias voltage generating circuit 101, a source terminal of the ninth MOS transistor M9 is commonly connected to a drain terminal of the eleventh MOS transistor M11 and one terminal of the fifth resistor R5, the other terminal of the fifth resistor R5 is grounded VSS, a source terminal of the tenth MOS transistor M10 is connected to the power supply voltage VDD, a drain terminal of the tenth MOS transistor M10 is connected to a source terminal of the eleventh transistor M11 and serves as a voltage output node Vout of the regulator loop output circuit 102, the gate terminal of the eleventh MOS transistor M11 is connected to the third output node V3 of the bias voltage generating circuit 101; the ninth MOS transistor M9, the tenth MOS transistor M10, the eleventh MOS transistor M11, and the fifth resistor R5 form a feedback loop, the eighth MOS transistor M8, the tenth MOS transistor M10, and the eleventh MOS transistor M11 are PMOS transistors, and the ninth MOS transistor M9 is an NMOS transistor.

As shown in fig. 3, when the load current carried by the voltage output node Vout changes, a fast response can be obtained through the feedback loop, which is as follows: when the load current carried by the voltage output node Vout suddenly becomes large, the current flowing through the eleventh MOS transistor M11 is reduced, and the voltage drop on the fifth resistor R5 is reduced, at this time, the voltage at the source electrode of the ninth MOS transistor M9 is reduced, and after the amplification effect of the ninth MOS transistor M9, the voltage at the feedback node V4 is pulled down, so that the output voltage Vout is kept unchanged when the load current is switched; on the contrary, when the load current carried by the voltage output node Vout is small, the current flowing through the eleventh MOS transistor M11 increases, and at the same time, the voltage drop across the fifth resistor R5 increases, at this time, the voltage at the source terminal of the ninth MOS transistor M9 increases, and after the amplification action of the ninth MOS transistor M9, the voltage at the feedback node V4 is pulled up, so that the output voltage Vout is kept unchanged when the load current is switched.

As an example, as shown in fig. 4, the PSRR compensation circuit 103 includes: a twelfth MOS transistor M12, a thirteenth MOS transistor M13, a fourteenth MOS transistor M14, a fifteenth MOS transistor M15, a sixth resistor R6, a seventh resistor R7, an eighth resistor R8, a fourth capacitor C4 and a fifth capacitor C5; wherein the content of the first and second substances,

a source terminal of the twelfth MOS transistor M12 is connected to a power supply voltage VDD, a drain terminal of the twelfth MOS transistor M12 is commonly connected to a gate terminal of the twelfth MOS transistor M12, a drain terminal of the thirteenth MOS transistor M13 and one terminal of the sixth resistor R6, a gate terminal of the thirteenth MOS transistor M13 is connected to the first reference voltage VB, a source terminal of the thirteenth MOS transistor M13 is grounded VSS, the other terminal of the sixth resistor R6 is commonly connected to one terminal of the fourth capacitor C4 and a gate terminal of the fourteenth MOS transistor M14, the other terminal of the fourth capacitor C4 is grounded, a source terminal of the fourteenth MOS transistor M14 is connected to the power supply voltage VDD, a drain terminal of the fourteenth MOS transistor M14 is commonly connected to a source terminal of the fifteenth MOS transistor M15 and one terminal of the fifth capacitor C5, the other terminal of the fifth capacitor C5 is connected to the feedback node V4 of the regulated voltage loop output circuit 102, and a drain terminal of the fifteenth MOS transistor M15 is grounded, a gate terminal of the fifteenth MOS transistor M15 is commonly connected to one end of the seventh resistor R7 and one end of the eighth resistor R8, the other end of the seventh resistor R7 is connected to the voltage output node Vout of the regulator loop output circuit 102, and the other end of the eighth resistor R8 is connected to the ground VSS; the twelfth MOS transistor M12, the fourteenth MOS transistor M14 and the fifteenth MOS transistor M15 are PMOS transistors, and the thirteenth MOS transistor M13 is an NMOS transistor.

As shown in fig. 3, the main path for transferring the power disturbance to the output is through the tenth MOS transistor M10, i.e. the source terminal disturbance of the tenth MOS transistor M10 can be directly transferred to the output; however, under the power disturbance, if the source terminal and the gate terminal of the tenth MOS transistor M10 can be made to change synchronously, the influence of the power disturbance can be reduced to the maximum extent. As shown in fig. 4, the PSRR compensation circuit in this example collects the disturbance on the power supply and transmits the disturbance to the gate terminal of the tenth MOS transistor, so that the source terminal and the gate terminal of the tenth MOS transistor M10 change synchronously, thereby implementing PSRR compensation; the method comprises the following specific steps: the gate terminal of the fourteenth MOS transistor M14 is biased by the twelfth MOS transistor M12 and filtered by R6/C4, and the fourteenth MOS transistor M14 may be used as a common-gate amplifying transistor for amplifying the AC signal of the power supply voltage and outputting the amplified AC signal to the gate terminal of the tenth MOS transistor M10 through the fifth capacitor C5, so that the source terminal and the gate terminal of the tenth MOS transistor M10 are synchronously changed, thereby achieving the purpose of compensating the PSRR.

The present example further provides a low dropout voltage stabilizing method implemented by using the low dropout voltage stabilizing circuit, where the low dropout voltage stabilizing method includes:

generating the bias voltage through the bias voltage generating circuit, and realizing the bias voltage output with low output noise based on RC filtering;

generating the output voltage through the voltage stabilizing loop output circuit, and regulating the output voltage based on a feedback loop in the voltage stabilizing loop output circuit when the load current changes so as to keep the output voltage constant;

the PSRR compensation circuit is used for collecting disturbance on a power supply, processing a collected disturbance signal and feeding the processed disturbance signal back to the grid terminal of an MOS (metal oxide semiconductor) tube connected between a power supply voltage and a voltage output node in the voltage stabilizing loop output circuit, so that the source terminal and the grid terminal of the MOS tube are synchronously changed, and the PSRR compensation is realized.

As an example, in order to make the output voltage Vout constantly equal to the second reference voltage VRFE, R4-N R5,

wherein

The width-to-length ratio of the first MOS transistor M1,

the width-to-length ratio of the second MOS transistor M2,

the width-to-length ratio of the third MOS transistor M3,

the width-to-length ratio of the fourth MOS transistor M4,

the width-to-length ratio of the fifth MOS transistor M5,

the width-to-length ratio of the sixth MOS transistor M6,

the width-to-length ratio of the seventh MOS transistor M7,

the width-to-length ratio of the ninth MOS transistor M9,

the width-length ratio of the eleventh MOS transistor M11, R4, R5, N, and M are the ratio multiples of the width-length ratio of the ninth MOS transistor M11, the ratio of the fourth resistor R3526, the ratio of the fifth resistor R5, the ratio of the fourth resistor N to the fifth resistor N, and the ratio of the width-length ratio of the ninth MOS transistor M to the width-length ratio of the fourth MOS transistor M.

By way of example, in order to achieve low output noise of the output voltage, the width-to-length ratio of the eighth MOS transistor M8 is 55 μ M/0.5 μ M to 65 μ M/0.5 μ M, the width-to-length ratio of the ninth MOS transistor M9 is 90 μ M/0.2 μ M to 120 μ M/0.2 μ M, the width-to-length ratio of the tenth MOS transistor M10 is 2.6mm/0.07 μ M to 3mm/0.07 μ M, and the width-to-length ratio of the eleventh MOS transistor M11 is 750 μ M/0.1 μ M to 780 μ M/0.1 μ M. Specifically, the quiescent current of the branch in which the eighth MOS transistor M8 and the ninth MOS transistor M9 are located is 5 μ a to 10 μ a, and the quiescent current of the branch in which the tenth MOS transistor M10 and the eleventh MOS transistor M11 are located is 50 μ a to 70 μ a.

As an example, in order to realize that the source terminal and the gate terminal of the MOS transistor connected between the power voltage and the voltage output node are varied in synchronization, the width-to-length ratio of the fourteenth MOS transistor M14 and the fifteenth MOS transistor M15 is 1: 1.

Referring to FIG. 5, the operation of the low dropout voltage regulator circuit of the present example will be explained.

First, as shown in fig. 5, assume that the DC operating current of the third MOS transistor M3 is I_D3Then the voltage at the second output node V2 is I_D3*R4+V_GS4In which V is_GS4The voltage difference between the grid end and the source end of the fourth MOS transistor M4 is shown; the source of the sixth MOS transistor M6 is connected to a second reference voltage VREF, and the sixth MOS transistor M6 obtains a voltage VRFF-V at the third output node V3 through the bias of the fifth MOS transistor M5 and the seventh MOS transistor M7, which are current source transistors_SG6In which V is_SG6The voltage difference between a source terminal and a gate terminal of the sixth MOS transistor M6; this is achieved bySince R4 is N × R5,

then there is V_SG6＝V_SG11Therefore, Vout is equal to VREF-V_SG6+V_SG11VREF, i.e., VREF is the DC output voltage of Vout, thereby achieving a linear regulated output of the low dropout voltage regulator circuit output voltage Vout described in this example.

When the load current carried by the voltage output node Vout changes, a fast response can be obtained through the feedback loop, specifically as follows: when the load current carried by the voltage output node Vout suddenly becomes large, the current flowing through the eleventh MOS transistor M11 is reduced, and the voltage drop on the fifth resistor R5 is reduced, at this time, the voltage at the source electrode of the ninth MOS transistor M9 is reduced, and after the amplification effect of the ninth MOS transistor M9, the voltage at the feedback node V4 is pulled down, so that the output voltage Vout is kept unchanged when the load current is switched; on the contrary, when the load current carried by the voltage output node Vout is small, the current flowing through the eleventh MOS transistor M11 increases, and at the same time, the voltage drop across the fifth resistor R5 increases, at this time, the voltage at the source terminal of the ninth MOS transistor M9 increases, and after the amplification action of the ninth MOS transistor M9, the voltage at the feedback node V4 is pulled up, so that the output voltage Vout is kept unchanged when the load current is switched.

Secondly, as shown in fig. 5, the bias voltage generating circuit 101 can eliminate most of the noise of the bias voltage and the current at each output node, especially the high frequency noise, by the filtering action of R1/C1, R2/C2, R3/C3, thereby realizing the low noise output of the voltage in the bias voltage generating circuit 101.

At this time, the noise of the output voltage Vout mainly comes from the eighth MOS transistor M8, the ninth MOS transistor M9, the tenth MOS transistor M10 and the eleventh MOS transistor M11 in the regulator loop output circuit 102, wherein since the ninth MOS transistor M9, the tenth MOS transistor M10 and the eleventh MOS transistor M11 provide voltage source noise, the larger the transconductance gm of the ninth MOS transistor M9, the tenth MOS transistor M10 and the eleventh MOS transistor M11 is, the smaller the voltage source noise it contributes to. And because of the need of loop gain, the width-to-length ratio of the ninth MOS transistor is increased to 90 mu m/0.2 mu m-120 mu m/0.2 mu m, so that the transconductance of the ninth MOS transistor is 0.28 mS-0.32 mS; the tenth MOS tube is used as a power tube, the width-length ratio of the tenth MOS tube is set to be 2.6mm/0.07 mu m-3 mm/0.07 mu m, the transconductance of the tenth MOS tube is larger than or equal to 2mS, the maximum 20mA current load capacity is ensured by designing the width-length ratio to be larger than or equal to 2.6mm/0.07 mu m, and the PSRR under high frequency is prevented from being influenced by too large width-length ratio by designing the width-length ratio to be smaller than or equal to 3mm/0.07 mu m; increasing the width-to-length ratio of the eleventh MOS transistor M11 to 750 mu M/0.1 mu M-780 mu M/0.1 mu M to enable the transconductance of the eleventh MOS transistor M11 to be 1.85 mS-1.95 mS; since the voltage output node Vout is used as the secondary pole of the loop, the equivalent impedance of the node needs to be reduced as much as possible to achieve a better loop phase margin, so that the loop bandwidth can be made wider, and the quiescent current of the branch where the tenth MOS transistor M10 and the eleventh MOS transistor M11 are located is 50 μ a to 70 μ a. In this example, since the transconductance gm of the ninth MOS transistor M9, the tenth MOS transistor M10, and the eleventh MOS transistor M11 is large, the contribution of the output noise of the ninth MOS transistor M9, the tenth MOS transistor M10, and the eleventh MOS transistor M11 is small.

At this time, as for the output noise of the whole circuit, only the current thermal noise of the eighth MOS transistor M8 is left, and the transconductance is set to be 0.18mS to 0.22mS by setting the width-to-length ratio of the eighth MOS transistor M8 to be 55 μ M/0.5 μ M to 65 μ M/0.5 μ M, and the quiescent current of the branch in which the eighth MOS transistor M8 and the ninth MOS transistor M9 are located is set to be 5 μ a to 10 μ a; the noise contribution of the eighth MOS transistor M8 can also be reduced.

Finally, as shown in fig. 5, the main path for transferring the power disturbance to the output is through the tenth MOS transistor M10, i.e. the source-end disturbance of the tenth MOS transistor M10 can be directly transferred to the output; however, under the power disturbance, if the source terminal and the gate terminal of the tenth MOS transistor M10 can be made to change synchronously, the influence of the power disturbance can be reduced to the maximum extent. In this example, the PSRR compensation circuit collects the disturbance on the power supply and transmits the disturbance to the gate terminal of the tenth MOS transistor, so that the source terminal and the gate terminal of the tenth MOS transistor M10 change synchronously, thereby implementing PSRR compensation; the method comprises the following specific steps: a power supply voltage is used as an AC signal source, a gate terminal of the fourteenth MOS transistor M14 is biased by the twelfth MOS transistor M12 and filtered by R6/C4, and the fourteenth MOS transistor M14 may be used as a common-gate amplifier transistor, configured to amplify an AC signal of the power supply voltage and output the AC signal to a gate terminal of the tenth MOS transistor M10 through the fifth capacitor C5; the source end and the gate end of the tenth MOS transistor M10 are changed synchronously by adjusting the width-to-length ratio of the fourteenth MOS transistor M14 to the fifteenth MOS transistor M15 to be 1:1, so as to achieve the purpose of compensating the PSRR.

It should be noted that, in order to realize that the source terminal and the gate terminal of the tenth MOS transistor M10 are changed synchronously, the width-to-length ratio of the fourteenth MOS transistor M14 and the fifteenth MOS transistor M15 should be 1: 1; however, in practical applications, the width-to-length ratio of the fourteenth MOS transistor M14 and the fifteenth MOS transistor M15 is difficult to be 1:1, so that in practical applications, the width-to-length ratio of the fourteenth MOS transistor M14 and the fifteenth MOS transistor M15 is close to 1: 1.

In summary, in the low dropout voltage regulator and the method thereof of the present invention, the bias voltage generating circuit generates the bias voltage, and the bias voltage output with low output noise is realized based on the RC filter; then, generating an output voltage through the voltage stabilizing loop output circuit, and regulating the output voltage based on a feedback loop in the voltage stabilizing loop output circuit when the load current changes so as to keep the output voltage constant; meanwhile, the PSRR compensation circuit is used for collecting disturbance on a power supply, and the collected disturbance signal is processed and fed back to the grid terminal of an MOS (metal oxide semiconductor) tube connected between a power supply voltage and a voltage output node in the voltage stabilizing loop output circuit, so that the source terminal and the grid terminal of the MOS tube are synchronously changed, and PSRR compensation is realized; therefore, the low-dropout voltage stabilizing circuit and the method thereof realize high PSRR and low output noise while realizing linear voltage-stabilizing output of the voltage through the design of the bias voltage generating circuit, the voltage-stabilizing loop output circuit and the PSRR compensating circuit. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.

The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.