阅读说明：本技术 结晶性半导体膜和板状体以及半导体装置 (Crystalline semiconductor film, plate-like body, and semiconductor device ) 是由 人罗俊实 织田真也 高塚章夫 于 2015-07-21 设计创作，主要内容包括：本发明提供半导体特性优异、特别是可抑制漏电流,耐压性和放热性优异的半导体膜和板状体,以及半导体装置。本发明提供结晶性半导体膜或板状体、以及具备含有所述结晶性半导体膜或所述板状体的半导体结构的半导体装置,所述结晶性半导体膜的特征在于,含有具有刚玉结构的氧化物半导体作为主成分,且含有半导体成分即选自镓、铟和铝中的1种或2种以上的氧化物作为主成分,膜厚为1μm以上。(The invention provides a semiconductor film and a plate-like body which are excellent in semiconductor characteristics, particularly, can suppress leakage current, and are excellent in pressure resistance and heat radiation, and a semiconductor device. The present invention provides a crystalline semiconductor film or a plate-like body, and a semiconductor device having a semiconductor structure including the crystalline semiconductor film or the plate-like body, wherein the crystalline semiconductor film contains an oxide semiconductor having a corundum structure as a main component, contains 1 or 2 or more oxides selected from gallium, indium, and aluminum as a semiconductor component, and has a film thickness of 1 μm or more.)

1. A crystalline semiconductor film characterized by containing, as a main component, an oxide semiconductor having a corundum structure, the oxide semiconductor containing, as a main component, one or two or more oxides selected from gallium, indium, and aluminum, the crystalline semiconductor film having a film thickness of 1 μm or more, and the crystalline semiconductor film containing substantially no carbon.

2. The crystalline semiconductor film according to claim 1, wherein the oxide semiconductor contains at least gallium.

3. The crystalline semiconductor film according to claim 1 or 2, wherein the film thickness is 7.6 μm or more.

4. A crystalline semiconductor film according to any one of claims 1 to 3, which is a self-supporting film.

5. A plate-like body characterized by containing, as a main component, an oxide semiconductor having a corundum structure, the oxide semiconductor containing, as a main component, one or two or more oxides selected from gallium, indium and aluminum, and the crystalline semiconductor film containing substantially no carbon.

6. The plate-like body according to claim 5, wherein the oxide semiconductor contains at least gallium.

7. The plate-like body according to claim 5 or 6, wherein the thickness is 50 μm or more.

8. A semiconductor structure comprising the crystalline semiconductor film according to any one of claims 1 to 4 or the plate-like body according to any one of claims 5 to 7.

9. A semiconductor device comprising the semiconductor structure according to claim 8.

10. The semiconductor device according to claim 9, which is a vertical apparatus.

11. A semiconductor device according to claim 9 or 10, characterized in that it is a power equipment.

12. The semiconductor device according to any one of claims 9 to 11, which is a schottky barrier diode SBD; a metal semiconductor field effect transistor (MESFET); a High Electron Mobility Transistor (HEMT); a Metal Oxide Semiconductor Field Effect Transistor (MOSFET); a static induction transistor SIT; a Junction Field Effect Transistor (JFET); an Insulated Gate Bipolar Transistor (IGBT); or a light emitting diode.

13. The semiconductor device according to any one of claims 9 to 12, which is a Schottky barrier diode SBD.

14. A crystalline semiconductor film characterized by containing, as a main component, an oxide semiconductor having a corundum structure, the oxide semiconductor containing, as a main component, one or two or more oxides selected from gallium, indium, and aluminum, the crystalline semiconductor film having a film thickness of 1 μm or more, and containing a dopant, the crystalline semiconductor film containing carbon in a smaller amount than the dopant.

Technical Field

The present invention relates to a crystalline semiconductor film and a plate-like body useful for a semiconductor device, and a semiconductor device using the crystalline semiconductor film or the plate-like body.

Background

Gallium oxide (Ga) having a wide band gap is used as a next-generation conversion element capable of realizing high withstand voltage, low loss, and high heat resistance₂O₃) The semiconductor device of (3) is attracting attention, and application to a power semiconductor device such as an inverter is expected. According to non-patent document 1, the gallium oxide can control the band gap by mixing indium or aluminum alone or In combination to form a mixed crystal, In_X’Al_Y’Ga_Z’O₃InAlGaO semiconductors represented by (0 ≦ X '≦ 2, 0 ≦ Y' ≦ 2, 0 ≦ Z '≦ 2, and X' + Y '+ Z' ≦ 1.5 to 2.5) are very attractive materials.

Patent document 1 describes highly crystalline conductive α -Ga containing a dopant (4-valent tin)₂O₃A film. However, the thin film described in patent document 1 cannot maintain sufficient pressure resistance, and contains a large amount of carbon impurities, so that semiconductor characteristics including conductivity are not satisfied, and it is difficult to apply the thin film to a semiconductor device.

Patent document 2 discloses α -Al₂O₃The substrate is formed with p-type α - (Al)_x”Ga_1-x”)₂O₃Ga of single crystal film₂O₃However, patent document 2 describes α -Al as a semiconductor element₂O₃The use of the MBE method for obtaining a p-type semiconductor requires ion implantation and heat treatment at high temperature, and therefore, it is difficult to realize the methodNow p-type α -Al₂O₃Actually, the semiconductor element itself described in patent document 2 is difficult to realize.

Non-patent document 2 describes that α -Ga can be formed on sapphire by MBE method₂O₃A film. However, it is also stated that: although crystals grow to a film thickness of 100nm at a temperature of 450 ℃ or less, the crystal quality deteriorates when the film thickness exceeds 100nm, and films having a film thickness of 1 μm or more cannot be obtained.

Therefore, α -Ga having a film thickness of 1 μm or more and having no deterioration in crystal quality is desired₂O₃A film.

Patent document 3 describes a method for producing an oxide crystal thin film by an aerosol CVD method using a bromide or iodide of gallium or indium.

Patent documents 4 to 6 describe a multilayer structure in which a semiconductor layer having a corundum-type crystal structure and an insulating film having a corundum-type crystal structure are stacked on a base substrate having a corundum-type crystal structure.

Patent documents 3 to 6 are all related to the patent or patent application of the present applicant, and at the time of application, a crystalline thin film having a thickness of 1 μm or more cannot be obtained. In addition, none of the films obtained by the methods described in patent documents 3 to 6 can be peeled from the substrate.

[ patent document 1 ] Japanese patent laid-open publication No. 2013-28480

[ patent document 2 ] Japanese patent laid-open publication No. 2013-58637

[ patent document 3 ] Japanese patent No. 5397794

[ patent document 4 ] Japanese patent No. 5343224

[ patent document 5 ] Japanese patent No. 5397795

[ patent document 6 ] Japanese patent laid-open No. 2014-72533

[ Nonpatent document 1 ] Jinzi Jiantailang, growth and physical properties of "gallium oxide series mixed crystal thin film with corundum structure", doctor paper of Kyoto university, Pingcheng 25 years and 3 months

[ non-patent document 2 ] Raveen Kumaran, "New Solid State Laser Crystals Createdby Epitaxial Growth", A thesis Submitted for The grid of sector of phosphor, The University of British Columbia, September 2012

Disclosure of Invention

The purpose of the present invention is to provide a semiconductor film, a plate-like body, and a semiconductor device which have excellent semiconductor characteristics, particularly, which can suppress a leak current, and which have excellent voltage resistance and heat dissipation.

The present inventors have conducted intensive studies to achieve the above object, and as a result, succeeded in producing a crystalline semiconductor film containing an oxide semiconductor having a corundum structure as a main component and having a film thickness of 1 μm or more.

Further, the present inventors have further studied and succeeded in producing a plate-like body containing an oxide semiconductor having a corundum structure as a main component.

The present inventors have also found that a semiconductor device manufactured using the crystalline semiconductor film or the plate-like body can suppress leak current and is excellent in voltage resistance and heat dissipation, and have further studied after obtaining the above-described findings, and have completed the present invention.

The crystalline semiconductor film and the plate-like body of the present invention have excellent semiconductor characteristics, and the semiconductor device of the present invention can suppress leakage current and has excellent pressure resistance and heat dissipation properties.

Drawings

Fig. 1 is a diagram schematically showing a preferred example of a Schottky Barrier Diode (SBD) according to the present invention.

Fig. 2 is a diagram schematically showing a preferred example of the Schottky Barrier Diode (SBD) of the present invention.

Fig. 3 is a diagram schematically showing a preferred example of the Schottky Barrier Diode (SBD) of the present invention.

Fig. 4 is a diagram schematically showing a preferred example of a metal semiconductor field effect transistor (MESFET) of the present invention.

Fig. 5 is a diagram schematically showing a preferred example of the High Electron Mobility Transistor (HEMT) of the present invention.

Fig. 6 is a view schematically showing a preferred example of a Metal Oxide Semiconductor Field Effect Transistor (MOSFET) according to the present invention.

Fig. 7 is a schematic diagram for explaining a part of a manufacturing process of the Metal Oxide Semiconductor Field Effect Transistor (MOSFET) of fig. 6.

Fig. 8 is a diagram schematically showing an example of a Metal Oxide Semiconductor Field Effect Transistor (MOSFET) according to the present invention.

Fig. 9 is a diagram schematically showing a preferred example of the Static Induction Transistor (SIT) of the present invention.

Fig. 10 is a diagram schematically showing a preferred example of the Schottky Barrier Diode (SBD) of the present invention.

Fig. 11 is a diagram schematically showing a preferred example of the Schottky Barrier Diode (SBD) of the present invention.

Fig. 12 is a diagram schematically showing a preferred example of the High Electron Mobility Transistor (HEMT) of the present invention.

Fig. 13 is a view schematically showing a preferred example of a Metal Oxide Semiconductor Field Effect Transistor (MOSFET) according to the present invention.

Fig. 14 is a diagram schematically showing a preferred example of a Junction Field Effect Transistor (JFET) of the present invention.

Fig. 15 schematically shows a preferred example of an Insulated Gate Bipolar Transistor (IGBT) according to the present invention.

Fig. 16 is a diagram schematically showing a preferred example of the light-emitting element (LED) of the present invention.

Fig. 17 is a diagram schematically showing a preferred example of the light-emitting element (LED) of the present invention.

FIG. 18 is a schematic diagram of a mist CVD apparatus used in examples.

Fig. 19 is a diagram illustrating a base used in the embodiment.

FIG. 20 is a diagram showing the relationship between the cross-sectional areas of the susceptor and the supply pipe used in the example.

FIG. 21 is a graph showing the relationship between the content of dopant in liquid and the content of germanium in the film in the example of the present invention.

Fig. 22 is a diagram illustrating the structure of a Schottky Barrier Diode (SBD) in the embodiment.

Fig. 23 is a graph showing the results of SIMS analysis of the semiconductor layer doped with germanium in the example.

Fig. 24 is a graph showing the results of SIMS analysis of the semiconductor layer doped with silicon in the example.

FIG. 25 is a view showing an X-ray diffraction image of the self-supporting film obtained in example.

Fig. 26 is a diagram illustrating the structure of a Schottky Barrier Diode (SBD) in the embodiment.

Fig. 27 is a diagram showing current-voltage characteristics of the SBD obtained in the example.

Fig. 28 is a view showing the structure of a MESFET produced in example.

Fig. 29 is a graph showing DC characteristics of the MESFET produced in the example. The vertical axis represents the drain current (a), and the horizontal axis represents the drain voltage (V).

FIG. 30 is a schematic configuration diagram of an atomizing CVD apparatus used in examples.

Fig. 31 is a diagram showing the evaluation results of the forward current-voltage characteristics in the example.

Fig. 32 is a diagram showing the evaluation results of the reverse current-voltage characteristics in the example.

Fig. 33 is a graph showing the results of XRD in examples.

FIG. 34 is a photograph showing a film in the examples.

FIG. 35 is a photograph showing a film in the examples.

Detailed Description

The crystalline semiconductor film of the present invention contains an oxide semiconductor having a corundum structure as a main component, and is not particularly limited as long as the film thickness is 1 μm or more, and in the present invention, the film thickness is preferably 2 μm or more, more preferably 3 μm or more, and most preferably 5 μm or more. In the present invention, the film thickness is preferably 7.6 μm or more, and if the film thickness is 7.6 μm or more, the crystalline semiconductor film can be independently supported. In the present invention, a multilayer film (for example, a laminate of an n-type semiconductor layer and an n + -type semiconductor layer) having a film thickness of more preferably 10 μm or more and the same main component is most preferable because the semiconductor characteristics can be further improved. In addition, the shape of the crystalline semiconductor filmThe shape of the surface layer is not particularly limited, and may be a square, a circle, or a polygon. The surface area of the crystalline semiconductor film is not particularly limited, but in the present invention, it is preferably 3mm square or more (9 mm)²Above), more preferably 5mm square or more (25 mm)²Above), most preferably 50mm or more in diameter. In the present invention, the crystalline semiconductor film of 3mm square or more, which has not been realized in the past, can be easily obtained by using the aerosol CVD method under specific conditions.

The crystalline semiconductor film may be a single crystal film or a polycrystalline film, and in the present invention, the crystalline semiconductor film preferably includes a single crystal film which may be polycrystalline. The oxide semiconductor is not particularly limited as long as it is an oxide semiconductor having a corundum structure. Examples of the oxide semiconductor include metal oxide semiconductors containing 1 or 2 or more metals selected from Al, Ga, In, Fe, Cr, V, Ti, Rh, Ni, Co, and the like. In the present invention, the oxide semiconductor preferably contains 1 or 2 or more elements selected from indium, aluminum, and gallium as a main component, more preferably contains at least indium or/and gallium as a main component, and most preferably contains at least gallium as a main component. In the present invention, the "main component" means that the oxide semiconductor having a corundum structure is contained in an atomic ratio of preferably 50% or more, more preferably 70% or more, further preferably 90% or more, and may be 100% with respect to the total components of the crystalline semiconductor film.

In the present invention, the oxide semiconductor is preferably α type In_XAl_YGa_ZO₃(0≦X≦2、0≦Y≦2、0≦Z≦2、X+Y+Z＝1.5～2.5、0<X or 0<Z) the oxide semiconductor is α type In_XAl_YGa_ZO₃The preferable composition in the case is not particularly limited as long as the object of the present invention is not impaired, and the total atomic ratio of gallium, indium, and aluminum in the metal element contained in the crystalline semiconductor film is preferably 0.5 or more, and more preferably 0.8 or more. In addition, a preferable composition when the oxide semiconductor contains gallium is preferably one contained in the crystalline semiconductor filmThe atomic ratio of gallium in the metal element is 0.5 or more, and more preferably 0.8 or more.

The crystalline semiconductor film may contain a dopant. The dopant is not particularly limited as long as it does not inhibit the object of the present invention. Examples of the dopant include n-type dopants such as tin, germanium, silicon, titanium, zirconium, vanadium, and niobium, and p-type dopants. The concentration of the dopant may typically be about 1X 10¹⁶/cm³～1×10²²/cm³In addition, the concentration of the dopant is set to, for example, about 1X 10¹⁷/cm³The following low concentration, for example, in the case of an n-type dopant, can yield an n-type semiconductor or the like. In addition, according to the present invention, it may be at about 1 × 10²⁰/cm³The dopant is contained at a high concentration as described above, and for example, in the case of an n-type dopant, an n + -type semiconductor or the like can be obtained. In the present invention, the n-type dopant is preferably germanium, silicon, titanium, zirconium, vanadium, or niobium, and when forming the n-type semiconductor layer, the concentration of germanium, silicon, titanium, zirconium, vanadium, or niobium in the crystalline semiconductor film is preferably set to about 1 × 10¹³～5×10¹⁷/cm³More preferably about 1X 10¹⁵～1×10¹⁷/cm³. In the case where an n + -type semiconductor layer is formed using germanium, silicon, titanium, zirconium, vanadium, or niobium as an n-type dopant, the concentration of germanium, silicon, titanium, zirconium, vanadium, or niobium in the crystalline semiconductor film is preferably set to about 1 × 10²⁰/cm³～1×10²³/cm³More preferably about 1X 10²⁰/cm³～1×10²¹/cm³. Thus, by adding germanium, silicon, titanium, zirconium, vanadium, or niobium to the crystalline semiconductor film, a crystalline semiconductor film having excellent electrical characteristics can be obtained as compared with the case of using tin as a dopant.

The crystalline semiconductor film may be formed directly on the base substrate or may be formed with another layer interposed therebetween. Examples of the other layer include a corundum-structure crystal thin film, a crystal thin film other than corundum structure, an amorphous thin film, and the like. The structure may be a single-layer structure or a multilayer structure. Further, a crystal phase of 2 phases or more may be mixed in the same layer. In the case of a multilayer structure, the crystalline semiconductor film is formed by, for example, laminating an insulating thin film and a conductive thin film, but the present invention is not limited thereto. When the insulating thin film and the conductive thin film are laminated to form a multilayer structure, the insulating thin film and the conductive thin film may have the same composition or different compositions from each other. The thickness ratio of the insulating thin film to the conductive thin film is not particularly limited, and for example, the ratio of (the thickness of the conductive thin film)/(the thickness of the insulating thin film) is preferably 0.001 to 100, and more preferably 0.1 to 5. Specifically, the more preferable ratio is, for example, 0.1, 0.2, 0.3, 0.4, 0.5, 0.6, 0.7, 0.8, 0.9, 1, 1.1, 1.2, 1.3, 1.4, 1.5, 1.6, 1.7, 1.8, 1.9, 2, 3, 4, 5, and may be in a range between any 2 values exemplified herein.

In the present invention, the crystalline semiconductor film can be stacked directly on a base substrate or via another layer by an aerosol CVD method using a susceptor, an abnormal crystal grain inhibitor, or the like shown in fig. 19 and 20, for example.

< base substrate >

The base substrate is preferably a substrate containing a crystal having a corundum structure as a main component or a substrate containing a crystal having a β -gallia structure as a main component, and the substrate containing a crystal having a corundum structure as a main component is preferably 70% or more, more preferably 90% or more, and the substrate containing a crystal having a corundum structure as a main component is preferably a substrate containing a crystal having a corundum structure as a main component, for example, a sapphire substrate (for example, a c-plane sapphire substrate), a α type gallium oxide substrate, and the like, and the substrate containing a crystal having a β -gallia structure as a main component is preferably a substrate containing a crystal having a corundum structure as a main component, for example, a β -gallia crystal having a β -gallia structure as a composition ratio of the substrate, and the substrate containing 70% or more, and the substrate containing a crystal having a β -gallia structure as a main component is preferably a substrate containing a crystal having a corundum structure as a composition ratio of 50% or more, and the substrate is not particularly limitedMore preferably 90% or more, and β -Ga is exemplified as the substrate mainly composed of a crystal having an β -gallia structure₂O₃Substrate or containing Ga₂O₃And Al₂O₃、Al₂O₃More than 0 wt% and 60 wt% or less. Examples of the other base substrate include substrates having a hexagonal crystal structure (e.g., SiC substrates, ZnO substrates, and GaN substrates). The crystalline semiconductor film is preferably formed over a substrate having a hexagonal crystal structure directly or with another layer (e.g., a buffer layer) interposed therebetween. The thickness of the base substrate is not particularly limited in the present invention, but is preferably 50 to 2000. mu.m, and more preferably 200 to 800. mu.m.

When the base substrate is a substrate having a metal film on the surface thereof, the metal film may be provided on a part or the whole of the surface of the substrate, and a mesh-like or dot-like metal film may be provided. The thickness of the metal film is not particularly limited, but is preferably 10 to 1000nm, and more preferably 10 to 500 nm. Examples of the material constituting the metal film include metals such as platinum (Pt), gold (Au), palladium (Pd), silver (Ag), chromium (Cr), copper (Cu), iron (Fe), tungsten (W), titanium (Ti), tantalum (Ta), niobium (Nb), manganese (Mn), molybdenum (Mo), aluminum (Al), or hafnium (Hf), and alloys thereof. The metal is preferably uniaxially oriented. The uniaxially oriented metal may have a single crystal orientation in a constant direction such as a film thickness direction, a film in-plane direction, or a film thickness direction, and may include a uniaxially preferentially oriented metal. In the present invention, uniaxial orientation in the film thickness direction is preferred. As for the orientation, whether or not the orientation is uniaxial can be confirmed by an X-ray diffraction method. For example, when the integrated intensity ratio of a peak derived from a uniaxially oriented crystal plane to a peak derived from another crystal plane is larger (preferably at least two times larger, more preferably at least one digit larger) than the integrated intensity ratio of a peak derived from a uniaxially oriented crystal plane to a peak derived from another crystal plane of the same crystal powder randomly oriented, it can be judged that the crystal powder is uniaxially oriented.

In the present invention, the base substrate is preferably a sapphire substrate (e.g., c-plane sapphire substrate), α -type gallium oxide substrate, or β -Ga₂O₃Substrate or containing Ga₂O₃And Al₂O₃And Al₂O₃More than 0 wt% and 60 wt% or less, or a mixed crystal substrate having a metal film formed on the surface thereof. By using such a preferable base substrate, the carbon content, carrier concentration, and half-width of the impurity of the crystalline semiconductor film can be further reduced as compared with the case of using another base substrate.

The atomization CVD method is not particularly limited as long as it is a film forming method including the following steps: for example, a step (1) of atomizing a raw material by an ultrasonic vibrator to generate mist; a step (2) of supplying a carrier gas; and a step (3) of carrying the mist to the base substrate held by the susceptor by a carrier gas to form a film. More specifically, the atomization method includes, for example, an atomization epitaxy method and an atomization CVD method.

The step (1) is not particularly limited as long as the raw material is atomized to generate mist. In the step (1), a mist generator for atomizing the raw material to generate mist may be used. The mist generator is not particularly limited as long as it can atomize the raw material to generate mist, and may be a known mist generator. Note that, the raw materials will be described below.

The step (2) is not particularly limited as long as the carrier gas is supplied. The carrier gas is not particularly limited as long as it is in a gaseous state that can transport the mist generated by atomizing the raw material to the substrate. The carrier gas is not particularly limited, and examples thereof include oxygen, nitrogen, argon, and synthetic gas.

The step (3) is not particularly limited as long as the mist can be carried to the base substrate held by the susceptor by a carrier gas to form a film. In the step (3), it is preferable to use a tube furnace capable of forming a film in a supply tube by carrying mist to the substrate with a carrier gas.

In the present invention, when the film is formed in the supply tube in the step (3), it is preferable to form the crystalline semiconductor film using a susceptor shown in fig. 19 and 20, for example, as the susceptor.

Fig. 19 shows an embodiment of the base. The susceptor 51 shown in fig. 19 includes a mist acceleration portion 52, a substrate holding portion 53, and a support portion 54. The support 54 is rod-shaped, and is configured to have a contact angle of approximately 90 ° with the supply pipe 55 by changing the angle in the middle. By adopting such a configuration, the stability of the base 51 can be improved, but in the present invention, the shape of the support portion 54 is not particularly limited, and various suitable shapes can be used.

Fig. 19(a) shows a cross section in the supply pipe from the upstream to the downstream of the mist to the substrate, and it can be seen that the outer peripheral shape of the substrate-side surface of the supply pipe is substantially semicircular and substantially the same shape along the inner periphery of the supply pipe. FIG. 19(b) shows a cross section of the supply pipe, the substrate and the susceptor when the mist is present in the upstream direction and in the downstream direction. The mist is not likely to settle down in the supply pipe due to its nature, but the base 51 is configured to be able to transport the settled mist to the substrate by accelerating the rising of the mist by inclining the mist accelerating portion 52.

In fig. 20, the region of the susceptor and the substrate shown in fig. 19 is represented as a substrate/susceptor region 61 and the region where unreacted mist is discharged is represented as a discharge region 62 in the supply pipe 55, whereby the relationship between the total area of the susceptor and the substrate and the area of the discharge region can be clarified. In the present invention, as shown in fig. 20, in a cross section of the supply pipe divided into a susceptor region occupied by the susceptor, the substrate region, and a discharge region for discharging unreacted mist, a total area of the susceptor region and the substrate is preferably larger than an area of the discharge region. By using such a preferable susceptor, the haze can be accelerated on the substrate, and a crystalline semiconductor film having a more uniform and thicker thickness can be obtained.

In the formation of the crystalline semiconductor film, doping treatment with a dopant may be performed. In the present invention, the doping treatment is usually performed by adding an abnormal grain inhibitor to the raw material. By doping the above-mentioned raw materials with an abnormal crystal grain inhibitor, a crystalline semiconductor film having excellent surface smoothness can be obtained. The doping amount is not particularly limited as long as the object of the present invention is not hindered, and is preferably 0.01 to 10% by mole, more preferably 0.1 to 5% by mole in the raw material.

The abnormal crystal grain inhibitor is an additive having an effect of inhibiting the generation of by-product particles during film formation, and is not particularly limited as long as the surface roughness (Ra) of the crystalline semiconductor film can be made, for example, 0.1 μm or less, and in the present invention, an abnormal crystal grain inhibitor composed of at least 1 selected from Br, I, F, and Cl is preferable. When Br or I is introduced into the film as an abnormal grain inhibitor for stable film formation, deterioration of surface roughness due to abnormal grain growth can be suppressed. The amount of the abnormal grain inhibitor to be added is not particularly limited as long as the abnormal grains can be inhibited, and is preferably 50% or less, more preferably 30% or less, and most preferably in the range of 1 to 30% by volume in the raw material solution. By using the abnormal crystal grain inhibitor in such a preferable range, the function as the abnormal crystal grain inhibitor can be exerted, and therefore, the growth of abnormal crystal grains in the crystalline semiconductor film can be suppressed and the surface can be smoothed.

The method for forming the crystalline semiconductor film is not particularly limited as long as the object of the present invention is not impaired, and can be formed, for example, as follows: depending on the composition of the crystalline semiconductor film, a gallium compound and an indium compound, an aluminum compound, or the like used as desired are combined, and the combined raw materials are reacted. This enables crystal growth of the crystalline semiconductor film on the base substrate from the base substrate side. As the gallium compound, gallium metal may be used as a starting material and converted into a gallium compound before film formation. Examples of the gallium compound include an organometallic complex of gallium (e.g., an acetylacetonate complex) and a halide (e.g., a fluoride, chloride, bromide, iodide), and in the present invention, a halide (e.g., a fluoride, chloride, bromide, iodide) is preferably used. By forming a film by using a halide as a raw material compound by aerosol CVD, the crystalline semiconductor film can be made to contain substantially no carbon.

More specifically, the crystalline semiconductor film can be formed by: the method includes supplying raw material fine particles generated from a raw material solution in which a raw material compound is dissolved into a film forming chamber, and reacting the raw material compound in the film forming chamber using the susceptor. The solvent of the raw material solution is not particularly limited, and water, hydrogen peroxide, or an organic solvent is preferable. In the present invention, the above-mentioned raw material compounds are usually reacted in the presence of a dopant raw material. The dopant raw material is preferably contained in a raw material solution and is micronized together with or separately from the raw material compound. The crystalline semiconductor film preferably contains less carbon than the dopant, and the crystalline semiconductor film preferably contains substantially no carbon. Note that the crystalline semiconductor film of the present invention is also preferable because halogen (preferably Br) can form a good semiconductor structure. Examples of the dopant material include metal monomers or compounds (e.g., halides, oxides, etc.) of tin, germanium, silicon, titanium, zirconium, vanadium, or niobium.

By performing the film formation as described above, a crystalline semiconductor film having a film thickness of 1 μm or more can be industrially advantageously obtained. In the present invention, the film thickness can be set to 1 μm or more by appropriately adjusting the film forming time.

In the present invention, annealing treatment may be performed after film formation. The temperature of the annealing treatment is not particularly limited, but is preferably 600 ℃ or lower, and more preferably 550 ℃ or lower. By performing the annealing treatment at such a preferable temperature, the carrier concentration of the crystalline semiconductor film can be more appropriately adjusted. The treatment time of the annealing treatment is not particularly limited as long as the object of the present invention is not impaired, and is preferably 10 seconds to 10 hours, and more preferably 10 seconds to 1 hour.

The base substrate may be peeled off from the crystalline semiconductor film. The peeling method is not particularly limited as long as the object of the present invention is not impaired, and may be a known method. Examples of the peeling method include a method of peeling by applying mechanical impact; a method of peeling by thermal stress by heating; a method of applying vibration such as ultrasonic waves to perform peeling; a method of performing peeling by etching, and the like. By the above peeling, the crystalline semiconductor film can be obtained as a self-supporting film.

When the base substrate is a substrate having a metal film formed on the surface thereof, only a part of the substrate may be peeled off, and the metal film may remain on the surface of the semiconductor layer. By leaving the metal film on the surface of the semiconductor layer, an electrode can be easily and satisfactorily formed on the surface of the semiconductor layer.

Further, the above-mentioned film formation can be repeated, and by repeating the film formation, the film thickness can be made thicker, and a plate-like body containing an oxide semiconductor having a corundum structure as a main component can be obtained. In the present invention, a crystalline semiconductor film may be formed again on the free-standing film.

In the present invention, the film formation is carried out as described above, whereby a plate-like body having a thickness of 7.6 μm or more, preferably 10 μm or more, more preferably 15 μm or more, and most preferably 50 μm or more can be obtained. The plate-like body can be used not only as a semiconductor layer but also as a substrate.

The crystalline semiconductor film or the plate-like body has a semiconductor structure useful for a semiconductor device, and in the present invention, the crystalline semiconductor film or the plate-like body can be applied to a semiconductor device as it is or after further processing or the like is performed as desired. When the semiconductor structure is used for a semiconductor device, the semiconductor structure of the present invention may be used as it is for a semiconductor device, or other layers (for example, an insulator layer, a semi-insulator layer, a conductor layer, a semiconductor layer, a buffer layer, other intermediate layers, or the like) may be further formed.

The semiconductor structure of the present invention is useful for various semiconductor devices, particularly power devices. The semiconductor device can be classified into a horizontal device (horizontal device) in which an electrode is formed on one surface side of a semiconductor layer and a vertical device (vertical device) in which electrodes are provided on both front and back surfaces of the semiconductor layer. Examples of the semiconductor device include a Schottky Barrier Diode (SBD), a metal semiconductor field effect transistor (MESFET), a High Electron Mobility Transistor (HEMT), a Metal Oxide Semiconductor Field Effect Transistor (MOSFET), a Static Induction Transistor (SIT), a Junction Field Effect Transistor (JFET), an Insulated Gate Bipolar Transistor (IGBT), a light emitting diode, and the like. In the present invention, the semiconductor device is preferably an SBD, a MOSFET, a SIT, a JFET, or an IGBT, and more preferably an SBD, a MOSFET, or a SIT. In the present invention, the semiconductor device may not include a p-type semiconductor layer.

Hereinafter, preferred examples of applying the crystalline semiconductor film having the above-described semiconductor structure to an n-type semiconductor layer (an n + type semiconductor, an n-type semiconductor, or the like) will be described with reference to the drawings. The semiconductor devices exemplified below may include other layers (for example, an insulator layer, a semi-insulator layer, a conductor layer, a semiconductor layer, a buffer layer, other intermediate layers, and the like) and the like, and the buffer layer (buffer layer) and the like may be omitted, as long as the object of the present invention is not impaired.

(SBD)

Fig. 1 shows an example of a Schottky Barrier Diode (SBD) according to the present invention. The SBD of fig. 1 includes an n-type semiconductor layer 101a, an n + -type semiconductor layer 101b, a schottky electrode 105a, and an ohmic electrode 105 b.

The material of the schottky electrode and the ohmic electrode may be a known electrode material, and examples of the electrode material include metals such as Al, Mo, Co, Zr, Sn, Nb, Fe, Cr, Ta, Ti, Au, Pt, V, Mn, Ni, Cu, Hf, W, Ir, Zn, In, Pd, Nd, or Ag, alloys thereof, metal oxide conductive films such as tin oxide, zinc oxide, Indium Tin Oxide (ITO), and zinc indium oxide (IZO), organic conductive compounds such as polyaniline, polythiophene, or polypyrrole, and mixtures thereof.

The schottky electrode and the ohmic electrode can be formed by a known method such as a vacuum deposition method or a sputtering method. More specifically, for example, when forming a schottky electrode, the following can be performed: a layer made of Mo and a layer made of Al were laminated, and patterning by photolithography was performed on the layer made of Mo and the layer made of Al.

When a reverse bias is applied to the SBD of fig. 1, a depletion layer (not shown) expands in the n-type semiconductor layer 101a, and thus the SBD has a high breakdown voltage. In addition, when a forward bias is applied, electrons flow from the ohmic electrode 105b to the schottky electrode 105 a. The SBD using the semiconductor structure is excellent in high withstand voltage and large current applications, and also has a high switching speed and excellent withstand voltage and reliability.

Fig. 2 shows an example of a Schottky Barrier Diode (SBD) according to the present invention. The SBD of fig. 2 includes an insulator layer 104 in addition to the SBD of fig. 1. More specifically, the semiconductor device includes an n-type semiconductor layer 101a, an n + -type semiconductor layer 101b, a schottky electrode 105a, an ohmic electrode 105b, and an insulator layer 104.

Examples of the material of the insulator layer 104 include GaO, AlGaO, InAlGaO, and AlInZnGaO₄、AlN、Hf₂O₃、SiN、SiON、Al₂O₃、MgO、GdO、SiO₂Or Si₃N₄In the present invention, a material having a corundum structure is preferable. By using an insulator having a corundum structure for the insulator layer, the function of the semiconductor characteristics at the interface can be exhibited well. The insulator layer 104 is provided between the n-type semiconductor layer 101 and the schottky electrode 105 a. The insulator layer can be formed by a known method such as sputtering, vacuum evaporation, or CVD.

As In the case of the SBD shown In fig. 1, the schottky electrode and the ohmic electrode may be formed by a known method such as sputtering, vacuum deposition, pressure bonding, or CVD, for example, and may be formed of a metal such as Al, Mo, Co, Zr, Sn, Nb, Fe, Cr, Ta, Ti, Au, Pt, V, Mn, Ni, Cu, Hf, W, Ir, Zn, In, Pd, Nd, or Ag, an alloy thereof, a metal oxide conductive film such as tin oxide, zinc oxide, Indium Tin Oxide (ITO), or zinc indium oxide (IZO), an organic conductive compound such as polyaniline, polythiophene, or polypyrrole, or a mixture thereof.

The SBD of fig. 2 is more excellent in insulation characteristics and has higher current controllability than the SBD of fig. 1.

The SBD in fig. 3 shows an example of a Schottky Barrier Diode (SBD) according to the present invention. The SBD of fig. 3 is significantly different from the SBD of fig. 1 and 2 in that it has a trench structure and includes a semi-insulator layer 103. The SBD of fig. 3 includes n-type semiconductor layer 101a, n + -type semiconductor layer 101b, schottky electrode 105a, ohmic electrode 105b, and semi-insulator layer 103, and can significantly reduce leakage current while maintaining voltage resistance and also achieve significantly low on-resistance.

The semi-insulator layer 103 may Be a semi-insulator, and examples of the semi-insulator include a semi-insulator containing a semi-insulator dopant such as magnesium (Mg), ruthenium (Ru), iron (Fe), beryllium (Be), cesium (Cs), strontium, or barium, and a semi-insulator subjected to a doping treatment.

(MESFET)

Fig. 4 shows an example of a metal semiconductor field effect transistor (MESFET) according to the present invention. The MESFET of fig. 4 includes an n-type semiconductor layer 111a, an n + -type semiconductor layer 111b, a buffer layer (buffer layer) 118, a semi-insulator layer 114, a gate electrode 115a, a source electrode 115b, and a drain electrode 115 c.

The material of the gate electrode, the drain electrode, and the source electrode may be a known electrode material, and examples of the electrode material include metals such as Al, Mo, Co, Zr, Sn, Nb, Fe, Cr, Ta, Ti, Au, Pt, V, Mn, Ni, Cu, Hf, W, Ir, Zn, In, Pd, Nd, or Ag, alloys thereof, metal oxide conductive films such as tin oxide, zinc oxide, Indium Tin Oxide (ITO), and zinc indium oxide (IZO), organic conductive compounds such as polyaniline, polythiophene, or polypyrrole, and mixtures thereof. The gate electrode, the drain electrode, and the source electrode can be formed by a known method such as a vacuum deposition method or a sputtering method.

The semi-insulator layer 114 may Be a semi-insulator, and examples of the semi-insulator include a semi-insulator containing a semi-insulator dopant such as magnesium (Mg), ruthenium (Ru), iron (Fe), beryllium (Be), cesium (Cs), strontium, or barium, and a semi-insulator subjected to a doping treatment.

In the MESFET of fig. 4, since a good depletion layer is formed under the gate electrode, the current flowing from the drain electrode to the source electrode can be efficiently controlled.

(HEMT)

Fig. 5 shows an example of a High Electron Mobility Transistor (HEMT) according to the present invention. The HEMT of fig. 5 includes an n-type semiconductor layer 121a having a narrow band gap, an n-type semiconductor layer 121b having a narrow band gap, an n + -type semiconductor layer 121c, a semi-insulator layer 124, a buffer layer 128, a gate electrode 125a, a source electrode 125b, and a drain electrode 125 c.

The materials of the gate electrode, the drain electrode, and the source electrode are known electrode materials, and examples of the electrode materials include metals such as Al, Mo, Co, Zr, Sn, Nb, Fe, Cr, Ta, Ti, Au, Pt, V, Mn, Ni, Cu, Hf, W, Ir, Zn, In, Pd, Nd, or Ag, alloys thereof, metal oxide conductive films such as tin oxide, zinc oxide, Indium Tin Oxide (ITO), and zinc indium oxide (IZO), organic conductive compounds such as polyaniline, polythiophene, and polypyrrole, and mixtures thereof. The gate electrode, the drain electrode, and the source electrode can be formed by a known method such as a vacuum deposition method or a sputtering method.

The n-type semiconductor layer under the gate electrode may be composed of at least a wide band gap layer 121a and a narrow band gap layer 121b, and the semi-insulator layer 124 may be composed of a semi-insulator, and examples of the semi-insulator include a semi-insulator containing a semi-insulator dopant such as ruthenium (Ru) or iron (Fe), and a semi-insulator subjected to a doping treatment.

In the HEMT of fig. 5, since a good depletion layer is formed under the gate electrode, the current flowing from the drain electrode to the source electrode can be efficiently controlled. In addition, in the present invention, by further forming the recess structure, the normally closed state can be exhibited.

(MOSFET)

Fig. 6 shows an example of a case where the semiconductor device of the present invention is a MOSFET. The MOSFET of fig. 6 is a channel MOSFET, and includes an n-type semiconductor layer 131a, n + -type semiconductor layers 131b and 131c, a gate insulating film 134, a gate electrode 135a, a source electrode 135b, and a drain electrode 135 c.

An n + -type semiconductor layer 131b having a thickness of, for example, 100nm to 100 μm is formed on the drain electrode 135c, and an n-type semiconductor layer 131a having a thickness of, for example, 100nm to 100 μm is formed on the n + -type semiconductor layer 131 b. An n + -type semiconductor layer 131c is formed on the n-type semiconductor layer 131a, and an active electrode 135b is formed on the n + -type semiconductor layer 131 c.

Further, the n + semiconductor layer 131c is formed to penetrate the n-type semiconductor layer 131a and the n + type semiconductor layer 131c, and a plurality of trenches having a depth reaching the middle of the n-type semiconductor layer 131a are formed. The trench is embedded with a gate electrode 135a through a gate insulating film 134 having a thickness of, for example, 10nm to 1 μm.

In the on state of the MOSFET of fig. 6, when a voltage is applied between the source electrode 135b and the drain electrode 135c and a positive voltage is applied to the gate electrode 135a with respect to the source electrode 135b, a channel layer is formed on the side surface of the n-type semiconductor layer 131a, and electrons are injected into the n-type semiconductor layer 131a, thereby turning on the MOSFET. In the off state, when the voltage of the gate electrode is set to 0V, the channel layer is not formed, and the n-type semiconductor layer 131a is filled with a depletion layer and turned off.

Fig. 7 shows a part of the manufacturing process of the MOSFET of fig. 6. For example, in the semiconductor structure shown in fig. 7(a), an etching mask is provided in a predetermined region between the n-type semiconductor layer 131a and the n + -type semiconductor layer 131c, and after the etching mask is masked, anisotropic etching is performed by a reactive ion etching method or the like to form a trench deep from the surface of the n + -type semiconductor layer 131c to a point in the middle of the n-type semiconductor layer 131a as shown in fig. 7 (b). Next, as shown in fig. 7(c), after a gate insulating film 134 having a thickness of, for example, 50nm to 1 μm is formed on the side surface and the bottom surface of the trench by a known method such as a thermal oxidation method, a vacuum evaporation method, a sputtering method, or a CVD method, a gate electrode material 135a such as, for example, polysilicon having a thickness of not more than the thickness of the n-type semiconductor layer is formed in the trench by the CVD method, the vacuum evaporation method, the sputtering method, or the like.

Then, a power MOSFET can be manufactured by forming a source electrode 135b on the n + -type semiconductor layer 131c and forming a drain electrode 135c on the n + -type semiconductor layer 131b by a known method such as a vacuum deposition method, a sputtering method, or a CVD method. The electrode materials of the source electrode and the drain electrode may be known electrode materials, and examples of the electrode materials include metals such as Al, Mo, Co, Zr, Sn, Nb, Fe, Cr, Ta, Ti, Au, Pt, V, Mn, Ni, Cu, Hf, W, Ir, Zn, In, Pd, Nd, and Ag, alloys thereof, metal oxide conductive films such as tin oxide, zinc oxide, Indium Tin Oxide (ITO), and zinc indium oxide (IZO), organic conductive compounds such as polyaniline, polythiophene, and polypyrrole, and mixtures thereof.

The MOSFET thus obtained has a higher voltage resistance than a conventional trench MOSFET. Although fig. 6 shows an example of a trench type vertical MOSFET, the present invention is not limited to this, and can be applied to various MOSFETs. For example, the trench in fig. 6 may be dug to a depth reaching the bottom surface of the n-type semiconductor layer 131a to reduce the series resistance. Fig. 8 shows an example of the horizontal MOSFET. The MOSFET of fig. 8 includes an n-type semiconductor layer 131a, a 1n + -type semiconductor layer 131b, a 2n + -type semiconductor layer 131c, a gate insulating film 134, a gate electrode 135a, a source electrode 135b, a drain electrode 135c, a buffer layer 138, and a semi-insulator layer 139. As shown in fig. 8, by embedding the n + -type semiconductor layer in the n-type semiconductor layer, a current can be made to flow more favorably than in other horizontal MOSFETs.

(SIT)

Fig. 9 shows an example of the case where the semiconductor device of the present invention is an SIT. The SIT of fig. 9 includes an n-type semiconductor layer 141a, n + -type semiconductor layers 141b and 141c, a gate electrode 145a, a source electrode 145b, and a drain electrode 145 c.

An n + -type semiconductor layer 141b having a thickness of, for example, 100nm to 100 μm is formed on the drain electrode 145c, and an n-type semiconductor layer 141a having a thickness of, for example, 100nm to 100 μm is formed on the n + -type semiconductor layer 141 b. An n + -type semiconductor layer 141c is formed on the n-type semiconductor layer 141a, and an active electrode 145b is formed on the n + -type semiconductor layer 141 c.

Further, the n + semiconductor layer 141c is formed to penetrate through the n-type semiconductor layer 141a, and a plurality of trenches are formed to reach halfway through the n-type semiconductor layer 141 a. A gate electrode 145a is formed on the n-type semiconductor layer in the trench.

In the on state of the SIT of fig. 9, when a voltage is applied between the source electrode 145b and the drain electrode 145c and a voltage positive to the source electrode 145b is applied to the gate electrode 145a, a channel layer is formed in the n-type semiconductor layer 141a and electrons are injected into the n-type semiconductor layer 141a, thereby turning on the SIT. In the off state, when the voltage of the gate electrode is set to 0V, the channel layer is not formed, and the n-type semiconductor layer 141a is in a state of being filled with a depletion layer and is turned off.

A known method can be used for manufacturing the SIT shown in fig. 9. For example, using the semiconductor structure shown in fig. 7(a), an etching mask is provided in a predetermined region between the n-type semiconductor layer 141a and the n + -type semiconductor layer 141c in the same manner as in the process for manufacturing the MOSFET shown in fig. 7, and after the etching mask is masked, anisotropic etching is performed by, for example, a reactive ion etching method, to form a trench having a depth from the surface of the n + -type semiconductor layer 141c to a depth halfway in the n-type semiconductor layer 141 a. Next, a gate electrode material such as polysilicon having an n-type semiconductor layer thickness of less than or equal to the n-type semiconductor layer is formed in the trench by CVD, vacuum evaporation, sputtering, or the like. Then, the source electrode 145b is formed on the n + -type semiconductor layer 141c and the drain electrode 145c is formed on the n + -type semiconductor layer 141b by a known method such as a vacuum deposition method, a sputtering method, or a CVD method, whereby SIT shown in fig. 9 can be manufactured.

The electrode materials of the source electrode and the drain electrode may be known electrode materials, and examples of the electrode materials include metals such as Al, Mo, Co, Zr, Sn, Nb, Fe, Cr, Ta, Ti, Au, Pt, V, Mn, Ni, Cu, Hf, W, Ir, Zn, In, Pd, Nd, and Ag, alloys thereof, metal oxide conductive films such as tin oxide, zinc oxide, Indium Tin Oxide (ITO), and zinc indium oxide (IZO), organic conductive compounds such as polyaniline, polythiophene, and polypyrrole, and mixtures thereof.

In the above examples, an example in which a p-type semiconductor is not used is shown, but the present invention is not limited thereto, and a p-type semiconductor may be used. Examples of using p-type semiconductors are shown in FIGS. 10 to 16. These semiconductor devices can be manufactured in the same manner as in the above example. The p-type semiconductor may be the same material as the n-type semiconductor and contain a p-type dopant, or may be a different p-type semiconductor.

Fig. 10 shows a preferred example of a Schottky Barrier Diode (SBD) including an n-type semiconductor layer 101a, an n + -type semiconductor layer 101b, a p-type semiconductor layer 102, an insulator layer 104, a schottky electrode 105a, and an ohmic electrode 105 b.

Fig. 11 shows a preferred example of a channel Schottky Barrier Diode (SBD) including an n-type semiconductor layer 101a, an n + -type semiconductor layer 101b, a p-type semiconductor layer 102, a schottky electrode 105a, and an ohmic electrode 105 b. According to the trench-type SBD, leakage current can be greatly reduced while maintaining voltage resistance, and a significantly low on-resistance can be realized.

Fig. 12 shows a preferred example of a High Electron Mobility Transistor (HEMT) having an n-type semiconductor layer 121a with a wide band gap, an n-type semiconductor layer 121b with a narrow band gap, an n + -type semiconductor layer 121c, a p-type semiconductor layer 123, a gate electrode 125a, a source electrode 125b, a drain electrode 125c, and a substrate 129.

Fig. 13 shows a preferred example of a Metal Oxide Semiconductor Field Effect Transistor (MOSFET) including an n-type semiconductor layer 131a, a 1n + -type semiconductor layer 131b, a 2n + -type semiconductor layer 131c, a p-type semiconductor layer 132, a p + -type semiconductor layer 132a, a gate insulating film 134, a gate electrode 135a, a source electrode 135b, and a drain electrode 135 c. The p + -type semiconductor layer 132a may be a p-type semiconductor layer, and may be the same as the p-type semiconductor layer 132.

Fig. 14 shows a preferred example of a Junction Field Effect Transistor (JFET) including an n-type semiconductor layer 141a, a 1n + -type semiconductor layer 141b, a 2n + -type semiconductor layer 141c, a p-type semiconductor layer 142, a gate electrode 145a, a source electrode 145b, and a drain electrode 145 c.

Fig. 15 shows a preferred example of an Insulated Gate Bipolar Transistor (IGBT) including an n-type semiconductor layer 151, an n-type semiconductor layer 151a, an n + -type semiconductor layer 151b, a p-type semiconductor layer 152, a gate insulating film 154, a gate electrode 155a, an emitter electrode 155b, and a collector electrode 155 c.

(LED)

Fig. 16 shows an example of a case where the semiconductor device of the present invention is a Light Emitting Diode (LED). The semiconductor light-emitting element in fig. 16 includes an n-type semiconductor layer 161 on a 2 nd electrode 165b, and a light-emitting layer 163 is stacked on the n-type semiconductor layer 161. A p-type semiconductor layer 162 is stacked on the light-emitting layer 163. A light-transmitting electrode 167 which transmits light generated by the light-emitting layer 163 is provided on the p-type semiconductor layer 162, and a 1 st electrode 165a is stacked on the light-transmitting electrode 167. Note that the semiconductor light-emitting element of fig. 16 may be covered with a protective layer except for an electrode portion.

Examples of the material of the light-transmissive electrode include a conductive material containing an oxide of indium (In) or titanium (Ti). More specifically, for example, In₂O₃、ZnO、SnO₂、Ga₂O₃、TiO₂、CeO₂Or a mixed crystal of 2 or more of them or a material doped with them. These materials can be provided by a known method such as sputtering to form the light-transmissive electrode. After the formation of the light-transmissive electrode, thermal annealing may be performed to make the light-transmissive electrode transparent.

In the semiconductor light-emitting element shown in fig. 16, the light-emitting layer 163 emits light by passing a current through the p-type semiconductor layer 162, the light-emitting layer 163, and the n-type semiconductor layer 161 with the 1 st electrode 165a serving as a positive electrode and the 2 nd electrode 165b serving as a negative electrode.

Examples of the material of the 1 st electrode 165a and the 2 Nd electrode 165b include metals such as Al, Mo, Co, Zr, Sn, Nb, Fe, Cr, Ta, Ti, Au, Pt, V, Mn, Ni, Cu, Hf, W, Ir, Zn, In, Pd, Nd, or Ag, alloys thereof, metal oxide conductive films such as tin oxide, zinc oxide, Indium Tin Oxide (ITO), and Indium Zinc Oxide (IZO), organic conductive compounds such as polyaniline, polythiophene, or polypyrrole, and mixtures thereof. The method of forming the electrode is not particularly limited, and may be appropriately selected from the following methods in consideration of compatibility with the material, and the electrode is formed on the substrate by the selected method: a wet method such as a printing method, a spraying method, or a coating method, a physical method such as a vacuum deposition method, a sputtering method, or an ion plating method, a chemical method such as a CVD or a plasma CVD method, or the like.

Fig. 17 shows another embodiment of the light-emitting element. In the light-emitting element in fig. 17, an n-type semiconductor layer 161 is stacked on a substrate 169, and a 2 nd electrode 165b is stacked on a part of a semiconductor layer exposed surface of the n-type semiconductor layer 161 exposed by notching a part of the p-type semiconductor layer 162, the light-emitting layer 163, and the n-type semiconductor layer 161.