阅读说明：本技术 一种宽摆幅单位增益电压缓冲器 (Wide-swing unit-gain voltage buffer ) 是由 白春风 殷琪浩 乔东海 于 2019-12-02 设计创作，主要内容包括：本发明公开了一种宽摆幅单位增益电压缓冲器,当输入(输出)电压较低时,第五NMOS管N5进入线性区,第五NMOS管N5的栅极电压显著升高,只要第五NMOS管N5的栅极电压没有上升到VDD-2Vdsat,第四NMOS管N4就能维持恒定偏置电流,进而第四NMOS管N4的源极电压能够跟随其栅极电压。此时OTA的输出级的第三NMOS管N3能够充分工作在饱和区,因而OTA能够维持高电压增益,同时由于OTA和源极跟随器都在闭环回路中,充足的环路增益保证了缓冲器输出电压与输入电压之间的近似相等,即便输入电压非常靠近地,也能够精确的实现电压缓冲,因此,本发明的单位增益电压缓冲器具有宽输入范围的特点。(The invention discloses a wide-swing unit-gain voltage buffer, when the input (output) voltage is lower, a fifth NMOS tube N5 enters a linear area, the gate voltage of a fifth NMOS tube N5 is obviously increased, as long as the gate voltage of a fifth NMOS tube N5 is not increased to VDD-2 Vddsat, a fourth NMOS tube N4 can maintain constant bias current, and further the source voltage of a fourth NMOS tube N4 can follow the gate voltage. At the moment, the third NMOS tube N3 of the output stage of the OTA can fully work in a saturation region, so the OTA can maintain high voltage gain, and meanwhile, because the OTA and the source follower are both in a closed loop circuit, sufficient loop gain ensures that the output voltage of the buffer is approximately equal to the input voltage, and even if the input voltage is very close to the ground, the voltage buffering can be accurately realized, so the unit gain voltage buffer has the characteristic of wide input range.)

1. A wide-swing unit gain voltage buffer is characterized by comprising an operational transconductance amplifier and a source electrode follower;

the operational transconductance amplifier adopts a PMOS tube folding cascode input type operational transconductance amplifier and comprises a first PMOS tube P1, a second PMOS tube P2, a third PMOS tube P3, a fourth PMOS tube P4, a fifth PMOS tube P5, a sixth PMOS tube P6, a seventh PMOS tube P7, an eighth PMOS tube P8, a first NMOS tube N1, a second NMOS tube N2, a third NMOS tube N3, a sixth NMOS tube N6, a seventh NMOS tube N7, a resistor R, a capacitor C and a voltage source VDD; the source follower comprises a ninth PMOS tube P9, a tenth PMOS tube P10, a fourth NMOS tube N4, a fifth NMOS tube N5 and an eighth NMOS tube N8;

the grid electrode of the first PMOS tube P1 is connected to a voltage input end, the source electrode of the first PMOS tube P1 is respectively connected to the source electrode of a second PMOS tube P2 and the drain electrode of a third PMOS tube P3, and the drain electrode of the first PMOS tube P1 is respectively connected to the source electrode of a second NMOS tube N2 and the drain electrode of a seventh NMOS tube N7; the drain electrode of the second PMOS tube P2 is respectively connected to the source electrode of the first NMOS tube N1 and the drain electrode of the sixth NMOS tube N6; the drain electrode of the fourth PMOS tube P4 is connected to the source electrode of a sixth PMOS tube P6, and the gate electrode of the fourth PMOS tube P4 is respectively connected to the gate electrode of a fifth PMOS tube P5, the drain electrode of the sixth PMOS tube P6 and the drain electrode of a first NMOS tube N1; the drain electrode of the fifth PMOS tube P5 is connected to the source electrode of a seventh PMOS tube P7, the drain electrode of the seventh PMOS tube P7 is respectively connected to the drain electrode of the second NMOS tube N2, the gate electrode of the third NMOS tube N3 and one end of a resistor R, the other end of the resistor R is connected with one end of a capacitor C, and the other end of the capacitor C is connected with the drain electrode of the eighth PMOS tube P8, the drain electrode of the third NMOS tube N3 and the gate electrode of the fourth NMOS tube N4; the drain electrode of the ninth PMOS transistor P9 is respectively connected to the source electrode of a tenth PMOS transistor P10 and the drain electrode of a fourth NMOS transistor N4, and the drain electrode of the tenth PMOS transistor P10 is connected to the gate electrode of a fifth NMOS transistor N5 and the drain electrode of an eighth NMOS transistor N8;

meanwhile, the gates of the third PMOS transistor P3, the eighth PMOS transistor P8 and the ninth PMOS transistor P9 are connected to a first bias voltage Vbias 1, the gates of the sixth PMOS transistor P6, the seventh PMOS transistor P7 and the tenth PMOS transistor P10 are connected to a second bias voltage Vbias2, the gates of the first NMOS transistor N1 and the second NMOS transistor N2 are connected to a third bias voltage Vbias3, and the gates of the sixth NMOS transistor N6, the seventh NMOS transistor N7 and the eighth NMOS transistor N8 are connected to a fourth bias voltage Vbias 4; the grid electrode of the second PMOS pipe P2, the source electrode of the fourth NMOS pipe N4 and the drain electrode of the fifth NMOS pipe N5 are connected to a voltage output end.

2. The wide-swing unity-gain voltage buffer according to claim 1, wherein the source of the third PMOS transistor P3, the source of the fourth PMOS transistor P4, the source of the fifth PMOS transistor P5, the source of the eighth PMOS transistor P8, and the source of the ninth PMOS transistor P9 are all connected to a voltage source VDD.

3. The wide-swing unity-gain voltage buffer according to claim 1, wherein the source of said third NMOS transistor N3, the source of said fifth NMOS transistor N5, the source of said sixth NMOS transistor N6, the source of said seventh NMOS transistor N7, and the source of said eighth NMOS transistor N8 are all grounded.

Technical Field

The invention belongs to the field of analog integrated circuit design, and particularly relates to a wide-swing unity-gain voltage buffer.

Background

The most commonly used unity gain voltage buffer is shown in fig. 1, in which the non-inverting input of an Operational Transconductance Amplifier (OTA) is used as the voltage input, and the inverting input and the output of the OTA are connected together to be used as the voltage output. Since the voltage gain (a) of the OTA is very high, the output voltage versus input voltage is:

the relative error of the buffered output is equal to 1/(1+ a), so the higher the gain of the OTA, the smaller the error of the unity-gain voltage buffer, i.e. the better the effect of the output voltage following the input voltage.

From the port impedance point of view, the input impedance of the unity gain voltage buffer shown in fig. 1 is equal to that of OTA, which is very high in CMOS process; its output impedance is equal to the OTA itself output impedance divided by (1+ a), a very low value. Therefore, the performance of such unity-gain voltage buffers depends on the level of the gain (a) of the OTA.

For the unity-gain voltage buffer shown in fig. 1, if the input voltage is a near-rail voltage, the PMOS transistor (the input voltage is close to the power rail) or the NMOS transistor (the input voltage is close to the ground rail) at the output terminal of the OTA may be in a linear region, and its transconductance value is very low, which causes the gain (a) of the OTA to become very low, and thus, the voltage buffer can no longer be accurately implemented. Fig. 2 shows the transfer characteristics of a 180nm CMOS process and an OTA-based unity-gain voltage buffer at 1.8V in the low input voltage range, and it can be seen that the output voltage starts to deviate significantly from the input voltage after the input voltage is below 0.35V. Furthermore, if the input is designed without rail-to-rail input, the bias current of the OTA input stage can be drastically reduced when a near-rail voltage is input, resulting in a reduced bandwidth.

Disclosure of Invention

The invention aims to provide a wide-swing unity-gain voltage buffer, because an OTA and a source follower are both in a closed loop, sufficient loop gain ensures that the output voltage and the input voltage of the buffer are approximately equal, and even if the input voltage is very close to the ground, the voltage buffering can be accurately realized, so the unity-gain voltage buffer has the characteristic of wide input range.

The technical scheme of the invention is as follows: a wide-swing unit gain voltage buffer comprises an operational transconductance amplifier and a source electrode follower;

the operational transconductance amplifier adopts a PMOS tube folding cascode input type operational transconductance amplifier and comprises a first PMOS tube P1, a second PMOS tube P2, a third PMOS tube P3, a fourth PMOS tube P4, a fifth PMOS tube P5, a sixth PMOS tube P6, a seventh PMOS tube P7, an eighth PMOS tube P8, a first NMOS tube N1, a second NMOS tube N2, a third NMOS tube N3, a sixth NMOS tube N6, a seventh NMOS tube N7, a resistor R, a capacitor C and a voltage source VDD; the source follower comprises a ninth PMOS tube P9, a tenth PMOS tube P10, a fourth NMOS tube N4, a fifth NMOS tube N5 and an eighth NMOS tube N8;

the grid electrode of the first PMOS tube P1 is connected to a voltage input end, the source electrode of the first PMOS tube P1 is respectively connected to the source electrode of a second PMOS tube P2 and the drain electrode of a third PMOS tube P3, and the drain electrode of the first PMOS tube P1 is respectively connected to the source electrode of a second NMOS tube N2 and the drain electrode of a seventh NMOS tube N7; the drain electrode of the second PMOS tube P2 is respectively connected to the source electrode of the first NMOS tube N1 and the drain electrode of the sixth NMOS tube N6; the drain electrode of the fourth PMOS tube P4 is connected to the source electrode of a sixth PMOS tube P6, and the gate electrode of the fourth PMOS tube P4 is respectively connected to the gate electrode of a fifth PMOS tube P5, the drain electrode of the sixth PMOS tube P6 and the drain electrode of a first NMOS tube N1; the drain electrode of the fifth PMOS tube P5 is connected to the source electrode of a seventh PMOS tube P7, the drain electrode of the seventh PMOS tube P7 is respectively connected to the drain electrode of the second NMOS tube N2, the gate electrode of the third NMOS tube N3 and one end of a resistor R, the other end of the resistor R is connected with one end of a capacitor C, and the other end of the capacitor C is connected with the drain electrode of the eighth PMOS tube P8, the drain electrode of the third NMOS tube N3 and the gate electrode of the fourth NMOS tube N4; the drain electrode of the ninth PMOS transistor P9 is respectively connected to the source electrode of a tenth PMOS transistor P10 and the drain electrode of a fourth NMOS transistor N4, and the drain electrode of the tenth PMOS transistor P10 is connected to the gate electrode of a fifth NMOS transistor N5 and the drain electrode of an eighth NMOS transistor N8;

meanwhile, the gates of the third PMOS transistor P3, the eighth PMOS transistor P8 and the ninth PMOS transistor P9 are connected to a first bias voltage Vbias 1, the gates of the sixth PMOS transistor P6, the seventh PMOS transistor P7 and the tenth PMOS transistor P10 are connected to a second bias voltage Vbias2, the gates of the first NMOS transistor N1 and the second NMOS transistor N2 are connected to a third bias voltage Vbias3, and the gates of the sixth NMOS transistor N6, the seventh NMOS transistor N7 and the eighth NMOS transistor N8 are connected to a fourth bias voltage Vbias 4; the grid electrode of the second PMOS pipe P2, the source electrode of the fourth NMOS pipe N4 and the drain electrode of the fifth NMOS pipe N5 are connected to a voltage output end.

Preferably, the source of the third PMOS transistor P3, the source of the fourth PMOS transistor P4, the source of the fifth PMOS transistor P5, the source of the eighth PMOS transistor P8, and the source of the ninth PMOS transistor P9 are all connected to a voltage source VDD.

Preferably, the source of the third NMOS transistor N3, the source of the fifth NMOS transistor N5, the source of the sixth NMOS transistor N6, the source of the seventh NMOS transistor N7, and the source of the eighth NMOS transistor N8 are all grounded.

The invention has the advantages that:

1. according to the wide-swing unity-gain voltage buffer, because the OTA and the source follower are both in the closed loop, sufficient loop gain ensures that the output voltage and the input voltage of the buffer are approximately equal, and even if the input voltage is very close to the ground, voltage buffering can be accurately realized, so that the unity-gain voltage buffer has the characteristic of wide input range;

2. the wide-swing unit-gain voltage buffer of the invention has the advantages that the load is only the input parasitic capacitance of the source follower, so the frequency compensation of the OTA is easier to realize.

Drawings

The invention is further described with reference to the following figures and examples:

fig. 1 is a schematic diagram of a common circuit structure of a unity-gain voltage buffer implemented based on OTA:

FIG. 2 is a graph of transfer characteristics of an OTA-based voltage buffer in a low input voltage segment;

FIG. 3 is a schematic diagram of a wide swing unity gain voltage buffer according to the present invention;

FIG. 4 is a graph of a simulation of the relationship between gain mode value and input common mode voltage at 100kHz according to the present invention (dashed line in the figure) compared to a conventional configuration (solid line in the figure);

fig. 5 is a graph of the transient response of the present invention and conventional structure to a small signal input voltage at a lower common mode voltage (50 mV).

Detailed Description