阅读说明：本技术 一种阻抗控制电路及装置 (Impedance control circuit and device ) 是由 陆让天 梁爱梅 温长清 于 2019-10-09 设计创作，主要内容包括：本发明提供一种阻抗控制电路,通过第一偏置电路和IO端接阻抗电路；第一偏置电路包括参考电阻、第一IO端口和第二偏置电路；所述第二偏置电路包括第一偏置输出VBN和第二偏置输出VBP；参考电阻通过第一IO端口与第二偏置电路连接；第一偏置输出VBN和第二偏置输出VBP分别与IO端接阻抗电路连接；IO端接阻抗电路包括K(K为大于等于1的整数)个第二IO端口；通过串联端接或并联端接,第二IO端口的端接阻抗与传输线的特征阻抗匹配。在某些实施过程中,只需外围连接一个参考电阻,可高精度、高稳定度、高实时效地实现多个IO端口的端接阻抗与传输线的特征阻抗匹配,包括串联端接和并联端接,无需占用系统宝贵的时钟资源,同时减少芯片面积。(The invention provides an impedance control circuit, which is connected with an impedance circuit through a first biasing circuit and an IO terminal; the first bias circuit comprises a reference resistor, a first IO port and a second bias circuit; the second bias circuit includes a first bias output VBN and a second bias output VBP; the reference resistor is connected with the second bias circuit through the first IO port; the first bias output VBN and the second bias output VBP are respectively connected with the IO terminating impedance circuit; the IO termination impedance circuit comprises K (K is an integer greater than or equal to 1) second IO ports; the termination impedance of the second IO port is matched to the characteristic impedance of the transmission line by either series termination or parallel termination. In some implementation processes, only one reference resistor needs to be connected to the periphery, so that the terminating impedance of a plurality of IO ports can be matched with the characteristic impedance of a transmission line in high precision, high stability and high real-time effect, the terminating impedance comprises series connection and parallel connection, precious clock resources of a system are not occupied, and the chip area is reduced.)

1. An impedance control circuit comprising:

a first bias circuit and an IO termination impedance circuit;

the first bias circuit comprises a reference resistor, a first IO port and a second bias circuit; the second bias circuit includes a first bias output VBN and a second bias output VBP; the reference resistor is connected with the second bias circuit through the first IO port; the first bias output VBN and the second bias output VBP are respectively connected with the IO termination impedance circuit;

the IO termination impedance circuit comprises K (K is an integer greater than or equal to 1) second IO ports; the termination impedance of the second IO port is matched to the characteristic impedance of the transmission line by either series termination or parallel termination.

2. The impedance control circuit of claim 1, wherein the first bias circuit comprises a first negative feedback loop and a second negative feedback loop; the first negative feedback loop generates the first bias output VBN; the second negative feedback loop generates the second bias output VBP.

3. The impedance control circuit of claim 2,

the first negative feedback loop comprises: a first single-stage amplification circuit AN and a first operational amplifier OPN; the first single-stage amplifying circuit AN comprises a first NMOS and the reference resistor; the output of the first single-stage amplifying circuit AN is the non-inverting input of the first operational amplifier OPN, and the output of the first operational amplifier OPN is the input of the first single-stage amplifying circuit AN; when the first negative feedback loop is stable, the equivalent impedance value of the first NMOS is equal to the reference resistance;

the second negative feedback loop comprises: a second single-stage amplification circuit AP and a second operational amplifier OPP; the second single-stage amplification circuit AP includes a first replica NMOS and a first PMOS; the first replica NMOS is a replica unit of the first NMOS; the output of the second single-stage amplification circuit AP is the non-inverting input of the second operational amplifier OPP, and the output of the second operational amplifier OPP is the input of the second single-stage amplification circuit AP; when the second negative feedback loop is stable, the equivalent impedance value of the first PMOS is equal to the reference resistor.

4. The impedance control circuit of claim 2,

the first negative feedback loop comprises: a first single-stage amplification circuit AN and a first operational amplifier OPN; the first single-stage amplifying circuit AN comprises a first NMOS and a first copy PMOS; the output of the first single-stage amplifying circuit AN is the non-inverting input of the first operational amplifier OPN, and the output of the first operational amplifier OPN is the input of the first single-stage amplifying circuit AN; when the first negative feedback loop is stable, the equivalent impedance value of the first NMOS is equal to the reference resistance;

the second negative feedback loop comprises: a second single-stage amplification circuit AP and a second operational amplifier OPP; the second single-stage amplification circuit AP comprises a first PMOS and the reference resistor; the first copy PMOS is a copy unit of a first PMOS; the output of the second single-stage amplification circuit AP is the non-inverting input of the second operational amplifier OPP, and the output of the second operational amplifier OPP is the input of the second single-stage amplification circuit AP; when the second negative feedback loop is stable, the equivalent impedance value of the first PMOS is equal to the reference resistor.

5. Impedance control circuit according to claim 3,

the resistance value of the reference resistor is X times of the characteristic impedance of the transmission line.

6. Impedance control circuit according to claim 3,

the IO termination impedance circuit comprises K second NMOS; the high level of the gate driving signal of the second NMOS is consistent with the high level of the first enabling signal in the second biasing circuit; the body terminal potential of the second NMOS is the first bias output VBN; the drain terminal of the second NMOS is correspondingly connected with the second IO port;

the second NMOS is a current mirror tube of the first NMOS; the size of the second NMOS is YN times of the size of the first NMOS; the equivalent impedance value of the second NMOS is X/YN times the characteristic impedance of the transmission line.

The IO termination impedance circuit further comprises K second PMOSs; the low level of the gate driving signal of the second PMOS is consistent with the low level of the second enabling signal in the second bias circuit; the body terminal potential of the second PMOS is the second bias output VBP; the drain terminal of the second PMOS is correspondingly connected with the second IO port;

the second PMOS is a current mirror tube of the first PMOS; the size of the second PMOS is YP times the size of the first PMOS; the second PMOS has an equivalent impedance value that is X/YP times the characteristic impedance of the transmission line.

7. The impedance control circuit of claim 6, wherein the matching of the terminated impedance of the second IO port to the characteristic impedance of the transmission line by either series termination or parallel termination comprises:

when the series connection termination is adopted, the equivalent impedance value of the second NMOS and the equivalent impedance value of the second PMOS are consistent with the characteristic impedance of the transmission line, and the output impedance of the driver is matched with the characteristic impedance of the transmission line;

when the parallel connection termination is adopted, the equivalent impedance value of the second NMOS and the equivalent impedance value of the second PMOS are both twice of the characteristic impedance of the transmission line, and the impedance of the receiver or the transmitter is matched with the characteristic impedance of the transmission line.

8. The impedance control circuit of claim 7, comprising:

and when the first enable signal is set to 0 and the second enable signal is set to 1, setting the gate drive signal of the second NMOS to be low level and the gate drive signal of the second PMOS to be high level, and turning off the impedance control circuit.

9. The impedance control circuit of claim 8, wherein the first bias circuit and the IO termination impedance circuit employ SOI technology.

10. An impedance control device, characterized in that it comprises an impedance control circuit according to any one of claims 1-9.

Technical Field

The present invention relates to, but not limited to, the field of integrated circuit design, and more particularly, to, but not limited to, an impedance control circuit and apparatus.

Background

In very large scale integrated circuits (VLSI) of the prior art, a clock is an important signal that controls the rate of data processing and transfer. For example, in the field of Field Programmable Gate Array (FPGA) applications, as the FPGA size becomes larger and larger, the system clock speed also becomes faster and faster. Maintaining signal integrity becomes a serious problem due to the faster clock edge rate. The design and production of printed circuit boards becomes more difficult. The printed circuit board must be properly terminated so that the device IO impedance matches the characteristic impedance of the transmission line to avoid reflections.

Disclosure of Invention

The technical problem that this embodiment provides an impedance control circuit and device mainly solves is: the number of peripheral termination resistors in the existing termination circuit increases with the number of IO devices, resulting in large substrate area and high production cost.

In order to solve the above technical problem, the present embodiment provides an impedance control circuit, including:

a first bias circuit and an IO termination impedance circuit;

the first bias circuit comprises a reference resistor, a first IO port and a second bias circuit; the second bias circuit includes a first bias output VBN and a second bias output VBP; the reference resistor is connected with the second bias circuit through the first IO port; the first bias output VBN and the second bias output VBP are respectively connected with the IO termination impedance circuit;

the IO termination impedance circuit comprises K (K is an integer greater than or equal to 1) second IO ports; the termination impedance of the second IO port is matched to the characteristic impedance of the transmission line by either series termination or parallel termination.

Optionally, the first bias circuit includes a first negative feedback loop and a second negative feedback loop; the first negative feedback loop generates the first bias output VBN; the second negative feedback loop generates the second bias output VBP.

Optionally, the first negative feedback loop comprises: a first single-stage amplification circuit AN and a first operational amplifier OPN; the first single-stage amplifying circuit AN comprises a first NMOS and the reference resistor; the output of the first single-stage amplifying circuit AN is the non-inverting input of the first operational amplifier OPN, and the output of the first operational amplifier OPN is the input of the first single-stage amplifying circuit AN; when the first negative feedback loop is stable, the equivalent impedance value of the first NMOS is equal to the reference resistance;

the second negative feedback loop comprises: a second single-stage amplification circuit AP and a second operational amplifier OPP; the second single-stage amplification circuit AP includes a first replica NMOS and a first PMOS; the first replica NMOS is a replica unit of the first NMOS; the output of the second single-stage amplification circuit AP is the non-inverting input of the second operational amplifier OPP, and the output of the second operational amplifier OPP is the input of the second single-stage amplification circuit AP; when the second negative feedback loop is stable, the equivalent impedance value of the first PMOS is equal to the reference resistor.

Optionally, the first negative feedback loop comprises: a first single-stage amplification circuit AN and a first operational amplifier OPN; the first single-stage amplifying circuit AN comprises a first NMOS and a first copy PMOS; the output of the first single-stage amplifying circuit AN is the non-inverting input of the first operational amplifier OPN, and the output of the first operational amplifier OPN is the input of the first single-stage amplifying circuit AN; when the first negative feedback loop is stable, the equivalent impedance value of the first NMOS is equal to the reference resistance;

the second negative feedback loop comprises: a second single-stage amplification circuit AP and a second operational amplifier OPP; the second single-stage amplification circuit AP comprises a first PMOS and the reference resistor; the first copy PMOS is a copy unit of a first PMOS; the output of the second single-stage amplification circuit AP is the non-inverting input of the second operational amplifier OPP, and the output of the second operational amplifier OPP is the input of the second single-stage amplification circuit AP; when the second negative feedback loop is stable, the equivalent impedance value of the first PMOS is equal to the reference resistor.

Optionally, the resistance of the reference resistor is X times the characteristic impedance of the transmission line.

Optionally, the IO termination impedance circuit includes K second NMOS; the high level of the gate driving signal of the second NMOS is consistent with the high level of the first enabling signal in the second biasing circuit; the body terminal potential of the second NMOS is the first bias output VBN; the drain terminal of the second NMOS is correspondingly connected with the second IO port;

the second NMOS is a current mirror tube of the first NMOS; the size of the second NMOS is YN times of the size of the first NMOS; the equivalent impedance value of the second NMOS is X/YN times the characteristic impedance of the transmission line.

The IO termination impedance circuit further comprises K second PMOSs; the low level of the gate driving signal of the second PMOS is consistent with the low level of the second enabling signal in the second bias circuit; the body terminal potential of the second PMOS is the second bias output VBP; the drain terminal of the second PMOS is correspondingly connected with the second IO port;

the second PMOS is a current mirror tube of the first PMOS; the size of the second PMOS is YP times the size of the first PMOS; the second PMOS has an equivalent impedance value that is X/YP times the characteristic impedance of the transmission line.

Optionally, the matching, by the series termination or the parallel termination, the termination impedance of the second IO port with the characteristic impedance of the transmission line includes:

when the series connection termination is adopted, the equivalent impedance value of the second NMOS and the equivalent impedance value of the second PMOS are consistent with the characteristic impedance of the transmission line, and the output impedance of the driver is matched with the characteristic impedance of the transmission line;

when the parallel connection termination is adopted, the equivalent impedance value of the second NMOS and the equivalent impedance value of the second PMOS are both twice of the characteristic impedance of the transmission line, and the impedance of the receiver or the transmitter is matched with the characteristic impedance of the transmission line.

Optionally, when the first enable signal is set to 0 and the second enable signal is set to 1, the gate drive signal of the second NMOS is set to a low level and the gate drive signal of the second PMOS is set to a high level, and the impedance control circuit is turned off.

Optionally, the first bias circuit and the IO termination impedance circuit use an SOI process.

In order to solve the above technical problem, the present embodiment provides an impedance control apparatus including the impedance control circuit as described above.

The invention has the beneficial effects that:

according to the impedance control circuit and the impedance control device provided by the embodiment, the impedance circuit is terminated through the first bias circuit and the IO; the first bias circuit comprises a reference resistor, a first IO port and a second bias circuit; the second bias circuit includes a first bias output VBN and a second bias output VBP; the reference resistor is connected with the second bias circuit through the first IO port; the first bias output VBN and the second bias output VBP are respectively connected with the IO termination impedance circuit; the IO termination impedance circuit comprises K (K is an integer greater than or equal to 1) second IO ports; the termination impedance of the second IO port is matched to the characteristic impedance of the transmission line by either series termination or parallel termination. In certain implementations, technical effects including, but not limited to, the following may be achieved: on one hand, the impedance control circuit provided by the invention can realize the matching of the termination impedance of a plurality of IO ports and the characteristic impedance of the transmission line only by connecting one reference resistor at the periphery, and comprises a series connection termination and a parallel connection termination; because the number of peripheral components is reduced, the difficulty of substrate wiring is reduced, the area of the substrate is saved, the device is easily suitable for application occasions with strict requirements on the size, and the signal integrity design of the printed circuit board is easier. On the other hand, the impedance control circuit provided by the invention can realize matching of the IO impedance of the device and the characteristic impedance of the transmission line with high precision, high stability and high real-time efficiency, does not need to occupy precious clock resources of a system, and simultaneously reduces the chip area.

Additional features and corresponding advantages of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention.

Drawings

FIG. 1 is a schematic diagram of a prior art series termination;

FIG. 2 is a prior art parallel termination schematic;

fig. 3 is a block diagram of an impedance control circuit according to the first embodiment;

fig. 4 is a circuit structure diagram of a first bias circuit according to the first embodiment;

fig. 5 is a circuit configuration diagram of a first bias circuit according to the first embodiment;

fig. 6 is a circuit configuration diagram of an IO termination impedance circuit according to the first embodiment;

fig. 7 is a circuit configuration diagram of an impedance control circuit according to the second embodiment.

DETAILED DESCRIPTION OF EMBODIMENT (S) OF INVENTION

In order to make the objects, technical solutions and advantages of the present invention more apparent, embodiments of the present invention are described in detail below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.