阅读说明：本技术 漏电反馈动态d触发器、数据运算单元、芯片、算力板及计算设备 (Electric leakage feedback dynamic D trigger, data operation unit, chip, force calculation board and computing equipment ) 是由 刘杰尧 张楠赓 吴敬杰 马晟厚 于 2019-09-30 设计创作，主要内容包括：本发明提供一种漏电反馈动态D触发器、数据运算单元、芯片、算力板及计算设备。漏电反馈动态D触发器,包括一输入端,一输出端,一时钟信号端；一第一数据传输单元；一第一数据锁存单元；一第二数据传输单元；一第二数据锁存单元；所述第一数据传输单元、所述第一数据锁存单元、所述第二数据传输单元、所述第二数据锁存单元依次串接在所述输入端和所述输出端之间,所述第一数据传输单元、所述第一数据锁存单元之间具有一节点；其中,还包括一漏电反馈单元,所述漏电反馈单元电性连接在所述节点以及所述输出端之间。可以有效补偿节点的动态漏电流,提高数据的安全性和正确率。(The invention provides a leakage feedback dynamic D trigger, a data operation unit, a chip, a calculation board and calculation equipment. The leakage feedback dynamic D trigger comprises an input end, an output end and a clock signal end; a first data transmission unit; a first data latch unit; a second data transmission unit; a second data latch unit; the first data transmission unit, the first data latch unit, the second data transmission unit and the second data latch unit are sequentially connected in series between the input end and the output end, and a node is arranged between the first data transmission unit and the first data latch unit; the leakage current feedback unit is electrically connected between the node and the output end. The dynamic leakage current of the node can be effectively compensated, and the safety and accuracy of data are improved.)

1. A leakage feedback dynamic D flip-flop, comprising:

an input end for inputting a data;

an output terminal for outputting the data;

a clock signal terminal for providing a clock signal;

a first data transmission unit for transmitting the data under the control of the clock signal;

the first data latch unit is used for latching the data transmitted by the first data transmission unit;

the second data transmission unit is used for transmitting the data latched by the first data latch unit under the control of the clock signal;

the second data latch unit is used for latching the data transmitted by the second data transmission unit;

the first data transmission unit, the first data latch unit, the second data transmission unit and the second data latch unit are sequentially connected in series between the input end and the output end, and a node is arranged between the first data transmission unit and the first data latch unit;

the leakage current feedback unit is electrically connected between the node and the output end.

2. The leaky feedback dynamic D flip-flop of claim 1, wherein: the leakage feedback unit has a first end, a second end and a control end, wherein the first end is electrically connected to the output end, and the second end is electrically connected to the node.

3. The leaky feedback dynamic D flip-flop of claim 2, wherein: the leakage feedback unit comprises a PMOS transistor and an NMOS transistor which are connected in series between the output end and the node.

4. The leaky feedback dynamic D flip-flop of claim 3, wherein: the PMOS transistor has a source terminal, a drain terminal and a gate terminal, the NMOS transistor has a source terminal, a drain terminal and a gate terminal, the source terminal of the PMOS transistor is electrically connected to the output terminal, the drain terminal of the PMOS transistor is electrically connected to the drain terminal of the NMOS transistor, and the source terminal of the NMOS transistor is electrically connected to the node.

5. The leaky feedback dynamic D flip-flop of claim 4, wherein: the grid ends of the PMOS transistor and the NMOS transistor are connected in parallel and are electrically connected to a power supply.

6. The leaky feedback dynamic D flip-flop of claim 4, wherein: the grid ends of the PMOS transistor and the NMOS transistor are connected in parallel and are electrically connected to the node.

7. The leaky feedback dynamic D flip-flop of claim 3, wherein: the PMOS transistor has a source terminal, a drain terminal and a gate terminal, the NMOS transistor has a source terminal, a drain terminal and a gate terminal, the source terminal of the NMOS transistor is electrically connected to the output terminal, the drain terminal of the NMOS transistor is electrically connected to the drain terminal of the PMOS transistor, and the source terminal of the PMOS transistor is electrically connected to the node.

8. The leaky feedback dynamic D flip-flop of claim 7, wherein: the grid ends of the PMOS transistor and the NMOS transistor are connected in parallel and are electrically connected to the ground.

9. The leaky feedback dynamic D flip-flop of claim 7, wherein: the grid ends of the PMOS transistor and the NMOS transistor are connected in parallel and are electrically connected to the node.

10. The leaky feedback dynamic D flip-flop of claim 2, wherein: the leakage feedback unit comprises a PMOS transistor, wherein the PMOS transistor is provided with a source end, a drain end and a grid end, the source end of the PMOS transistor is electrically connected to the output end, the drain end of the PMOS transistor is electrically connected to the node, and the grid end of the PMOS transistor is electrically connected to a power supply.

11. The leaky feedback dynamic D flip-flop of claim 2, wherein: the leakage feedback unit comprises an NMOS transistor, wherein the NMOS transistor is provided with a source end, a drain end and a grid end, the drain end of the NMOS transistor is electrically connected to the output end, the source end is electrically connected to the node, and the grid end is electrically connected to the ground.

12. The leaky feedback dynamic D flip-flop of claim 1, wherein: the clock signal comprises a first clock signal and a second clock signal, and the first clock signal and the second clock signal are in opposite phases.

13. The leaky feedback dynamic D flip-flop of claim 1, wherein: the first data transmission unit and/or the second data transmission unit are transmission gates.

14. The leaky feedback dynamic D flip-flop of claim 1, wherein: the first data latch unit and/or the second data latch unit are inverters.

15. A data arithmetic unit comprises a control circuit, an arithmetic circuit and a plurality of leakage feedback dynamic D triggers which are connected in an interconnecting way, wherein the leakage feedback dynamic D triggers are connected in series and/or in parallel; the method is characterized in that: the leakage feedback dynamic D flip-flops of any one of claims 1-14.

16. A chip comprising at least one data arithmetic unit as claimed in claim 15.

17. An computing force board for a computing device comprising at least one chip as recited in claim 16.

18. A computing device comprises a power panel, a control panel, a connecting plate, a radiator and a plurality of computing plates, wherein the control panel is connected with the computing plates through the connecting plate, the radiator is arranged around the computing plates, the power panel is used for providing power for the connecting plate, the control panel, the radiator and the computing plates, and the computing plates are characterized in that: the force computing board is as claimed in claim 17.

Technical Field

The invention relates to a storage device controlled by a clock, in particular to a leakage feedback dynamic D trigger, a data operation unit, a chip, a calculation board and a calculation device applied to large-scale data operation equipment.

Background

The dynamic D trigger has wide application and can be used for registering digital signals. Fig. 1 is a circuit configuration diagram of a conventional dynamic D flip-flop. As shown in fig. 1, the dynamic D flip-flop includes a transmission gate 101, an inverter 102, a transmission gate 103, and an inverter 104 connected in series between an input terminal D and an output terminal Q. The node S0 is formed between the transmission gate 101 and the inverter 102, the node S1 is formed between the transmission gate 103 and the inverter 104, and data is temporarily stored at the node S0 and/or the node S1 through the inverter 102 and the parasitic capacitance of the transistors in the inverter 104. However, node S0 is prone to dynamic leakage, resulting in temporary data loss.

Therefore, how to effectively reduce the dynamic leakage of the leakage feedback dynamic D flip-flop is a problem to be solved.

Disclosure of Invention

In order to solve the above problems, the present invention provides a leakage feedback dynamic D flip-flop, which can effectively compensate the dynamic leakage current of a node, and improve the security and accuracy of data.

In order to achieve the above object, the present invention provides a leakage feedback dynamic D flip-flop, which includes an input terminal for inputting a data; an output terminal for outputting the data; a clock signal terminal for providing a clock signal; a first data transmission unit for transmitting the data under the control of the clock signal; the first data latch unit is used for latching the data transmitted by the first data transmission unit; the second data transmission unit is used for transmitting the data latched by the first data latch unit under the control of the clock signal; the second data latch unit is used for latching the data transmitted by the second data transmission unit; the first data transmission unit, the first data latch unit, the second data transmission unit and the second data latch unit are sequentially connected in series between the input end and the output end, and a node is arranged between the first data transmission unit and the first data latch unit; the leakage current feedback unit is electrically connected between the node and the output end.

In the above leakage feedback dynamic D flip-flop, the leakage feedback unit has a first end, a second end and a control end, the first end is electrically connected to the output end, and the second end is electrically connected to the node.

In the above leakage feedback dynamic D flip-flop, the leakage feedback unit includes a PMOS transistor and an NMOS transistor, and the PMOS transistor and the NMOS transistor are connected in series between the output terminal and the node.

In the above leakage feedback dynamic D flip-flop, the PMOS transistor has a source terminal, a drain terminal and a gate terminal, the NMOS transistor has a source terminal, a drain terminal and a gate terminal, the source terminal of the PMOS transistor is electrically connected to the output terminal, the drain terminal of the PMOS transistor is electrically connected to the drain terminal of the NMOS transistor, and the source terminal of the NMOS transistor is electrically connected to the node.

In the above leakage feedback dynamic D flip-flop, the gate terminals of the PMOS transistor and the NMOS transistor are connected in parallel and electrically connected to a ground.

In the above leakage feedback dynamic D flip-flop, the gate terminals of the PMOS transistor and the NMOS transistor are connected in parallel and electrically connected to the node.

In the above leakage feedback dynamic D flip-flop, the PMOS transistor has a source terminal, a drain terminal and a gate terminal, the NMOS transistor has a source terminal, a drain terminal and a gate terminal, the source terminal of the NMOS transistor is electrically connected to the output terminal, the drain terminal of the NMOS transistor is electrically connected to the drain terminal of the PMOS transistor, and the source terminal of the PMOS transistor is electrically connected to the node.

In the above leakage feedback dynamic D flip-flop, the gate terminals of the PMOS transistor and the NMOS transistor are connected in parallel and electrically connected to a power supply.

In the above leakage feedback dynamic D flip-flop, the gate terminals of the PMOS transistor and the NMOS transistor are connected in parallel and electrically connected to the node.

In the above leakage feedback dynamic D flip-flop, the leakage feedback unit includes a PMOS transistor, the PMOS transistor has a source terminal, a drain terminal and a gate terminal, the source terminal of the PMOS transistor is electrically connected to the output terminal, the drain terminal of the PMOS transistor is electrically connected to the node, and the gate terminal of the PMOS transistor is electrically connected to a power source.

In the above leakage feedback dynamic D flip-flop, the leakage feedback unit includes an NMOS transistor having a source terminal, a drain terminal and a gate terminal, the drain terminal of the NMOS transistor is electrically connected to the output terminal, the source terminal is electrically connected to the node, and the gate terminal is electrically connected to a ground.

In the above leakage feedback dynamic D flip-flop, the clock signal includes a first clock signal and a second clock signal, and the first clock signal and the second clock signal are in opposite phases.

In the above leakage feedback dynamic D flip-flop, the first data transmission unit and/or the second data transmission unit are transmission gates.

In the above leakage feedback dynamic D flip-flop, the first data latch unit and/or the second data latch unit is an inverter.

By using the leakage feedback dynamic D trigger, leakage current can be fed back to the node from the output end, the dynamic leakage current of the node is compensated, the stability of data storage is improved, and the safety and the accuracy of data are further enhanced.

In order to better achieve the above object, the present invention further provides a data operation unit, which includes a control circuit, an operation circuit, and a plurality of leakage feedback dynamic D flip-flops connected in series and/or in parallel; the plurality of leakage feedback dynamic D triggers are any one of the leakage feedback dynamic D triggers.

In order to better achieve the above object, the present invention further provides a chip, wherein the chip comprises at least one data operation unit.

In order to better achieve the above object, the present invention further provides an algorithm board for a computing device, wherein at least one chip as described above is included.

In order to better achieve the above object, the present invention further provides a computing device, which includes a power board, a control board, a connecting board, a heat sink, and a plurality of computing boards, wherein the control board is connected to the computing boards through the connecting board, the heat sink is disposed around the computing boards, and the power board is used to provide power to the connecting board, the control board, the heat sink, and the computing boards are the above computing boards.

The invention is described in detail below with reference to the drawings and specific examples, but the invention is not limited thereto.

Drawings

FIG. 1 is a schematic circuit diagram of a conventional dynamic D flip-flop;

fig. 2 is a schematic circuit structure diagram of a leakage feedback dynamic D flip-flop according to an embodiment of the present invention;

fig. 3 is a schematic circuit diagram of a leakage feedback dynamic D flip-flop according to another embodiment of the present invention;

fig. 4 is a schematic circuit diagram of a leakage feedback dynamic D flip-flop according to another embodiment of the present invention;

fig. 5 is a schematic circuit diagram of a leakage feedback dynamic D flip-flop according to still another embodiment of the present invention;

fig. 6 is a schematic circuit structure diagram of a leakage feedback dynamic D flip-flop according to an expanded embodiment of the present invention;

fig. 7 is a schematic circuit structure diagram of a leakage feedback dynamic D flip-flop according to another embodiment of the present invention;

FIG. 8 is a schematic diagram of a data operation unit according to the present invention;

FIG. 9 is a schematic diagram of a chip according to the present invention;

FIG. 10 is a schematic structural diagram of the force calculating board of the present invention;

FIG. 11 is a schematic diagram of a computing device according to the present invention.

Wherein, the reference numbers:

100: dynamic D flip-flop

101. 103: transmission gate

102. 104: inverter with a capacitor having a capacitor element

200: leakage feedback dynamic D trigger

201: first data transmission unit

202: first data latch unit

203: second data transmission unit

204: second data latch unit

205: leakage feedback unit

201P, 203P, 205P: PMOS transistor

201N, 203N, 205N: NMOS transistor

800: data arithmetic unit

801: control circuit

802: arithmetic circuit

900: chip and method for manufacturing the same

901: control unit

1000: force calculating board

1100: computing device

1101: connecting plate

1102: control panel

1103: heat radiator

1104: power panel

D: input terminal

Q: output end

CKP, CKN: clock signal

S0, S1: node point

Detailed Description

The invention will be described in detail with reference to the following drawings, which are provided for illustration purposes and the like:

certain terms are used throughout the description and following claims to refer to particular components. As one of ordinary skill in the art will appreciate, manufacturers may refer to a component by different names. This specification and the claims that follow do not intend to distinguish between components that differ in name but not function.

In the following description and in the claims, the terms "include" and "comprise" are used in an open-ended fashion, and thus should be interpreted to mean "include, but not limited to. In addition, the term "connected" is intended to encompass any direct or indirect electrical connection. Indirect electrical connection means include connection by other means.