阅读说明：本技术 一种线性充电升压芯片 (Linear charging and boosting chip ) 是由 霍晓强 金楠 崔凤敏 于 2021-09-17 设计创作，主要内容包括：本发明提供一种线性充电升压芯片,包括欠压锁定模块、线性充电模块及升压模块,所述欠压锁定模块用于比较电池电压和第一设定电压,根据比较结果产生充电切换控制信号,并在电池电压不小于第一设定电压时产生升压控制信号；所述线性充电模块受控于所述充电切换控制信号,用于通过输入电压对电池进行涓流充电或恒流充电,并在电池电压达到满充设定值时结束充电；所述升压模块受控于所述升压控制信号,用于对输出电压进行升压操作以使其达到输出设定值。通过本发明提供的线性充电升压芯片,解决了现有蓝牙充电仓存在造成管壳面积浪费及DCDC升压芯片倒灌回线性充电管理芯片的问题。(The invention provides a linear charging boost chip, which comprises an under-voltage locking module, a linear charging module and a boost module, wherein the under-voltage locking module is used for comparing the voltage of a battery with a first set voltage, generating a charging switching control signal according to the comparison result and generating a boost control signal when the voltage of the battery is not less than the first set voltage; the linear charging module is controlled by the charging switching control signal and is used for trickle charging or constant-current charging the battery through input voltage and finishing charging when the voltage of the battery reaches a full charging set value; the boosting module is controlled by the boosting control signal and is used for boosting the output voltage to reach an output set value. The linear charging boost chip provided by the invention solves the problems of tube shell area waste and back-flow of the DCDC boost chip to the linear charging management chip in the existing Bluetooth charging bin.)

1. A linear charging voltage boost chip, characterized in that, the linear charging voltage boost chip includes: an under-voltage locking module, a linear charging module, a boosting module and a working voltage generating module,

the under-voltage locking module is used for comparing the battery voltage with a first set voltage, generating a charging switching control signal according to the comparison result, and generating a boosting control signal when the battery voltage is not less than the first set voltage;

the linear charging module is controlled by the charging switching control signal and is used for trickle charging or constant-current charging the battery through input voltage and finishing charging when the voltage of the battery reaches a full charging set value;

the boosting module is controlled by the boosting control signal and is used for boosting the output voltage to reach an output set value;

the working voltage generation module is controlled by an enable signal and is used for comparing the input voltage with the battery voltage and selecting a larger value of the input voltage and the battery voltage as a first working voltage, comparing the battery voltage with the output voltage and selecting a larger value of the battery voltage and the output voltage as a second working voltage, comparing the internal low voltage with the second working voltage and selecting a larger value of the internal low voltage and the second working voltage as a third working voltage when the enable signal is effective; the first working voltage and the internal low voltage are used as working voltages of the linear charging module, the second working voltage is used as a working voltage of the boosting module, and the third working voltage is used as a working voltage of the under-voltage locking module.

2. The linear charge boost chip of claim 1, wherein the linear charge module comprises: the charge circuit comprises a matching amplifier, a current loop, a full-charge comparator, a voltage loop, a gating switch, a NAND gate, a first diode, a second diode, a first high-voltage NMOS tube, a second high-voltage NMOS tube, a first high-voltage PMOS tube, a second high-voltage PMOS tube, a third high-voltage PMOS tube, a first resistor, a second resistor, a third resistor, a fourth resistor and a fifth resistor, wherein the grid electrode of the first high-voltage PMOS tube is connected with the grid electrode of the second high-voltage PMOS tube and is connected with a grid electrode control signal of a charge P tube, the source electrode of the first high-voltage PMOS tube is connected with the source electrode of the second high-voltage PMOS tube and is connected with the input voltage, the drain electrode of the first high-voltage PMOS tube is connected with the inverting input end of the matching amplifier and the source electrode of the third high-voltage PMOS tube, the drain electrode of the second high-voltage PMOS tube is connected with the non-inverting input end of the matching amplifier and one end of the first resistor and is used as the charge output end of the linear charge module, the output end of the matching amplifier is connected with the grid electrode of the third high-voltage PMOS tube, the drain electrode of the third high-voltage PMOS tube is connected with the in-phase input end of the current loop and the reverse-phase input end of the full-charge comparator and serves as the charging current programming end of the linear charging module, the other end of the first resistor is connected with the in-phase input end of the voltage loop and one end of the second resistor, the reverse-phase input end of the current loop is connected with the common end of the gating switch, the output end of the current loop outputs a charging P tube grid control signal through the first diode, the third resistor, the fourth resistor and the fifth resistor are connected in series between a first reference voltage and the ground, the connection node of the third resistor and the fourth resistor is connected with the first gating end of the gating switch, and the connection node of the fourth resistor and the fifth resistor is connected with the second gating end of the gating switch and the in-phase input end of the full-charge comparator, the output end of the full charge comparator is connected with one input end of the NAND gate, the inverting input end of the voltage ring is connected with a first reference voltage, the output end of the voltage ring outputs another charge P tube grid control signal through the second diode, the other end of the second resistor is connected with the drain electrode of the first high-voltage NMOS tube, the other input end of the NAND gate is connected with the charge switching control signal, the output end of the NAND gate is connected with the grid electrode of the second high-voltage NMOS tube, the source electrode of the first high-voltage NMOS tube is grounded, the grid electrode of the first high-voltage NMOS tube is connected with the grid electrode of the second high-voltage NMOS tube, the source electrode of the second high-voltage NMOS tube is grounded, and the drain electrode of the second high-voltage NMOS tube is used as the charge state output end of the linear charge module; the gating switch is controlled by the charging switching control signal, the substrate of the first high-voltage PMOS tube and the substrate of the second high-voltage PMOS tube are both connected with the first working voltage, and the substrate of the first high-voltage NMOS tube, the substrate of the second high-voltage NMOS tube and the substrate of the third high-voltage PMOS tube are all connected with the source electrodes of the first high-voltage NMOS tube, the second high-voltage NMOS tube and the third high-voltage PMOS tube.

3. The linear charge boost chip of claim 2, wherein the linear charge module further comprises: an input under-voltage comparison unit, an input over-voltage comparison unit and a charging logic control unit,

the input under-voltage comparison unit is used for comparing the input voltage with a second set voltage and generating an input under-voltage signal when the input voltage is smaller than the second set voltage;

the input overvoltage comparing unit is used for comparing the input voltage with a third set voltage and generating an input overvoltage signal when the input voltage is greater than the third set voltage;

the charging logic control unit is used for generating a charging P pipe turn-off signal according to the input undervoltage signal or the input overvoltage signal.

4. The linear charge boost chip of claim 3, wherein the linear charge module further comprises: the non-inverting input end of the port overvoltage comparator is connected with the drain electrode of the third high-voltage PMOS tube, the inverting input end of the port overvoltage comparator is connected with the first reference voltage, and the output end of the port overvoltage comparator is connected with the charging logic control unit and is used for comparing the voltage of the charging current programming end with the first reference voltage and generating a port overvoltage signal when the voltage of the charging current programming end is greater than the first reference voltage; at this time, the charging logic control unit is further configured to generate a charging P-tube turn-off signal according to the port overvoltage signal.

5. The linear charge boost chip of claim 3, wherein the linear charge module further comprises: the battery temperature detection unit is used for detecting the battery temperature, generating a battery high-temperature signal when the battery temperature is higher than a first set battery temperature, and generating a battery low-temperature signal when the battery temperature is lower than a second set battery temperature; at this time, the charging logic control unit is further configured to generate a charging P-tube turn-off signal according to the battery high-temperature signal or the battery low-temperature signal.

6. The linear charge boost chip of claim 3, wherein the linear charge module further comprises: the reverse connection preventing unit is used for generating a reverse connection signal when the battery voltage is negative voltage; at this time, the charging logic control unit is further configured to generate a charging P-tube turn-off signal according to the reverse connection signal.

7. The linear charging boost chip of any one of claims 3-6, wherein when generating the charging P-tube turn-off signal, the charging logic control unit is further configured to generate a device turn-off signal.

8. The linear charge boost chip of claim 1, in which the boost module comprises: the constant turn-off time control circuit comprises a PMOS power tube, an NMOS power tube, an error amplifier, a slope generator, an adder, a PWM comparator, a constant turn-off time generation unit, a boost logic control unit, a sixth resistor and a seventh resistor, wherein the grid electrode of the PMOS power tube is connected with a boost P tube grid electrode control signal, the source electrode of the PMOS power tube is used as the voltage output end of the boost module, the drain electrode of the PMOS power tube is connected with the drain electrode of the NMOS power tube, the source electrode of the NMOS power tube is grounded, the grid electrode of the NMOS power tube is connected with a boost N tube grid electrode control signal, the sixth resistor and the seventh resistor are connected in series between the source electrode of the PMOS power tube and the source electrode of the NMOS power tube, the connection node of the sixth resistor and the seventh resistor is connected with the inverting input end of the error amplifier, the non-inverting input end of the error amplifier is connected with a second reference voltage, and the output end of the error amplifier is connected with the non-inverting input end of the PWM comparator, the inverting input end of the PWM comparator is connected to the output end of the adder, the first input end of the adder is connected to the output end of the slope generator, the second input end of the adder is connected to the reference current, the output end of the PWM comparator is connected to the first input end of the boost logic control unit, the output end of the constant turn-off time generation unit is connected to the second input end of the boost logic control unit, the control end of the boost logic control unit is connected to the boost control signal, the first output end of the boost logic control unit outputs the boost P tube gate control signal, and the second output end of the boost logic control unit outputs the boost N tube gate control signal; the constant turn-off time generation unit is used for starting timing when the PWM comparator generates a boost N tube turn-off signal and generating a boost P tube turn-off signal when the timing time reaches a set time, and the boost logic control unit is used for generating the boost N tube grid control signal according to the boost N tube turn-off signal and generating the boost P tube grid control signal according to the boost P tube turn-off signal; and the substrate of the PMOS power tube is connected with the second working voltage, and the substrate of the NMOS power tube is connected with the source electrode of the NMOS power tube.

9. The linear charge boost chip of claim 8, in which the boost module further comprises: the overcurrent protection/zero-crossing detection unit is used for detecting the current of the voltage output end, generating an overcurrent signal when the current reaches a set peak current and generating a zero-crossing signal when the current reaches a set valley current; at this time, the boost logic control unit is further configured to generate a first turn-off signal according to the overcurrent signal to control the NMOS power transistor to turn off, and generate a second turn-off signal according to the zero-crossing signal to control the PMOS power transistor to turn off.

10. The linear charge boost chip of claim 8, in which the boost module further comprises: the short-circuit protection unit is used for detecting the duration time of the output voltage which is less than or equal to the set short-circuit voltage and generating a short-circuit signal when the duration time is greater than the set short-circuit time; at this time, the boost logic control unit is further configured to generate a total turn-off signal according to the short-circuit signal to control the NMOS power transistor and the PMOS power transistor to turn off.

11. The linear charging boost chip according to any one of claims 8-10, wherein the boost logic control unit is further configured to generate a boost enable signal according to the turn-on and turn-off of the NMOS power transistor and/or the PMOS power transistor.

12. The linear charge-up boost chip of claim 8, wherein said linear charge-up boost chip further comprises: the thermal shutdown module is used for detecting the temperature of the chip when the linear charging boost chip works in a boost mode, generating a boost thermal shutdown signal when the detected temperature is higher than a first set chip temperature, and generating a boost recovery signal when the detected temperature is lower than a second set chip temperature, wherein at the moment, the boost logic control unit is also used for generating a total shutdown signal according to the boost thermal shutdown signal to control the NMOS power tube and the PMOS power tube to be turned off, and generating a total recovery signal according to the boost recovery signal to control the NMOS power tube and the PMOS power tube to be turned on; the thermal shutdown module is further used for detecting the temperature of the chip when the linear charging voltage boosting chip works in a charging mode, and generating a charging thermal shutdown signal to finish charging when the detected temperature is higher than a third set chip temperature.

13. The linear charge-up boost chip of claim 1, wherein the linear charge-up boost chip further comprises: and the internal low voltage generation module is used for linearly stabilizing the input voltage to generate the internal low voltage.

14. The linear charge-up boost chip of claim 1, wherein the linear charge-up boost chip further comprises: the reference voltage generating module is used for generating a first reference voltage and a second reference voltage.

Technical Field

The invention relates to the field of integrated circuit design, in particular to a linear charging boost chip.

Background

The existing Bluetooth charging bin comprises two chips, wherein one chip is a linear charging management chip, and the other chip is a DCDC boost chip; when two chips are used to realize the function of the bluetooth charging bin, even if the two chips are packaged together, the following problems can also exist: one is the waste of the area of the tube shell, and the other is the problem that the DCDC boost chip can flow back to the linear charge management chip.

Disclosure of Invention

In view of the above disadvantages of the prior art, an object of the present invention is to provide a linear charging boost chip, which is used to solve the problems of the existing bluetooth charging chamber that the area of the tube is wasted and the DCDC boost chip flows back to the linear charging management chip.

To achieve the above and other related objects, the present invention provides a linear charge boost chip, including: an under-voltage locking module, a linear charging module and a boosting module,

the under-voltage locking module is used for comparing the battery voltage with a first set voltage, generating a charging switching control signal according to the comparison result, and generating a boosting control signal when the battery voltage is not less than the first set voltage;

the linear charging module is controlled by the charging switching control signal and is used for trickle charging or constant-current charging the battery through input voltage and finishing charging when the voltage of the battery reaches a full charging set value;

the boosting module is controlled by the boosting control signal and is used for boosting the output voltage to reach an output set value.

Optionally, the linear charge boost chip further includes: the working voltage generation module is controlled by the enable signal and is used for comparing the input voltage with the battery voltage and selecting a larger value of the input voltage and the battery voltage as a first working voltage, comparing the battery voltage with the output voltage and selecting a larger value of the battery voltage and the output voltage as a second working voltage, comparing the internal low voltage with the second working voltage and selecting a larger value of the internal low voltage and the second working voltage as a third working voltage when the enable signal is effective; the first working voltage and the internal low voltage are used as working voltages of the linear charging module, the second working voltage is used as a working voltage of the boosting module, and the third working voltage is used as a working voltage of the under-voltage locking module.

Optionally, the linear charging module includes: the charge circuit comprises a matching amplifier, a current loop, a full-charge comparator, a voltage loop, a gating switch, a NAND gate, a first diode, a second diode, a first high-voltage NMOS tube, a second high-voltage NMOS tube, a first high-voltage PMOS tube, a second high-voltage PMOS tube, a third high-voltage PMOS tube, a first resistor, a second resistor, a third resistor, a fourth resistor and a fifth resistor, wherein the grid electrode of the first high-voltage PMOS tube is connected with the grid electrode of the second high-voltage PMOS tube and is connected with a grid electrode control signal of a charge P tube, the source electrode of the first high-voltage PMOS tube is connected with the source electrode of the second high-voltage PMOS tube and is connected with the input voltage, the drain electrode of the first high-voltage PMOS tube is connected with the inverting input end of the matching amplifier and the source electrode of the third high-voltage PMOS tube, the drain electrode of the second high-voltage PMOS tube is connected with the non-inverting input end of the matching amplifier and one end of the first resistor and is used as the charge output end of the linear charge module, the output end of the matching amplifier is connected with the grid electrode of the third high-voltage PMOS tube, the drain electrode of the third high-voltage PMOS tube is connected with the in-phase input end of the current loop and the reverse-phase input end of the full-charge comparator and serves as the charging current programming end of the linear charging module, the other end of the first resistor is connected with the in-phase input end of the voltage loop and one end of the second resistor, the reverse-phase input end of the current loop is connected with the common end of the gating switch, the output end of the current loop outputs a charging P tube grid control signal through the first diode, the third resistor, the fourth resistor and the fifth resistor are connected in series between a first reference voltage and the ground, the connection node of the third resistor and the fourth resistor is connected with the first gating end of the gating switch, and the connection node of the fourth resistor and the fifth resistor is connected with the second gating end of the gating switch and the in-phase input end of the full-charge comparator, the output end of the full charge comparator is connected with one input end of the NAND gate, the inverting input end of the voltage ring is connected with a first reference voltage, the output end of the voltage ring outputs another charge P tube grid control signal through the second diode, the other end of the second resistor is connected with the drain electrode of the first high-voltage NMOS tube, the other input end of the NAND gate is connected with the charge switching control signal, the output end of the NAND gate is connected with the grid electrode of the second high-voltage NMOS tube, the source electrode of the first high-voltage NMOS tube is grounded, the grid electrode of the first high-voltage NMOS tube is connected with the grid electrode of the second high-voltage NMOS tube, the source electrode of the second high-voltage NMOS tube is grounded, and the drain electrode of the second high-voltage NMOS tube is used as the charge state output end of the linear charge module; the gating switch is controlled by the charging switching control signal, the substrate of the first high-voltage PMOS tube and the substrate of the second high-voltage PMOS tube are both connected with the first working voltage, and the substrate of the first high-voltage NMOS tube, the substrate of the second high-voltage NMOS tube and the substrate of the third high-voltage PMOS tube are all connected with the source electrodes of the first high-voltage NMOS tube, the second high-voltage NMOS tube and the third high-voltage PMOS tube.

Optionally, the linear charging module further includes: an input under-voltage comparison unit, an input over-voltage comparison unit and a charging logic control unit,

the input under-voltage comparison unit is used for comparing the input voltage with a second set voltage and generating an input under-voltage signal when the input voltage is smaller than the second set voltage;

the input overvoltage comparing unit is used for comparing the input voltage with a third set voltage and generating an input overvoltage signal when the input voltage is greater than the third set voltage;

the charging logic control unit is used for generating a charging P pipe turn-off signal according to the input undervoltage signal or the input overvoltage signal.

Optionally, the linear charging module further includes: the non-inverting input end of the port overvoltage comparator is connected with the drain electrode of the third high-voltage PMOS tube, the inverting input end of the port overvoltage comparator is connected with the first reference voltage, and the output end of the port overvoltage comparator is connected with the charging logic control unit and is used for comparing the voltage of the charging current programming end with the first reference voltage and generating a port overvoltage signal when the voltage of the charging current programming end is greater than the first reference voltage; at this time, the charging logic control unit is further configured to generate a charging P-tube turn-off signal according to the port overvoltage signal.

Optionally, the linear charging module further includes: the battery temperature detection unit is used for detecting the battery temperature, generating a battery high-temperature signal when the battery temperature is higher than a first set battery temperature, and generating a battery low-temperature signal when the battery temperature is lower than a second set battery temperature; at this time, the charging logic control unit is further configured to generate a charging P-tube turn-off signal according to the battery high-temperature signal or the battery low-temperature signal.

Optionally, the linear charging module further includes: the reverse connection preventing unit is used for generating a reverse connection signal when the battery voltage is negative voltage; at this time, the charging logic control unit is further configured to generate a charging P-tube turn-off signal according to the reverse connection signal.

Optionally, when the charging P-tube turn-off signal is generated, the charging logic control unit is further configured to generate a device turn-off signal.

Optionally, the boost module comprises: the constant turn-off time control circuit comprises a PMOS power tube, an NMOS power tube, an error amplifier, a slope generator, an adder, a PWM comparator, a constant turn-off time generation unit, a boost logic control unit, a sixth resistor and a seventh resistor, wherein the grid electrode of the PMOS power tube is connected with a boost P tube grid electrode control signal, the source electrode of the PMOS power tube is used as the voltage output end of the boost module, the drain electrode of the PMOS power tube is connected with the drain electrode of the NMOS power tube, the source electrode of the NMOS power tube is grounded, the grid electrode of the NMOS power tube is connected with a boost N tube grid electrode control signal, the sixth resistor and the seventh resistor are connected in series between the source electrode of the PMOS power tube and the source electrode of the NMOS power tube, the connection node of the sixth resistor and the seventh resistor is connected with the inverting input end of the error amplifier, the non-inverting input end of the error amplifier is connected with a second reference voltage, and the output end of the error amplifier is connected with the non-inverting input end of the PWM comparator, the inverting input end of the PWM comparator is connected to the output end of the adder, the first input end of the adder is connected to the output end of the slope generator, the second input end of the adder is connected to the reference current, the output end of the PWM comparator is connected to the first input end of the boost logic control unit, the output end of the constant turn-off time generation unit is connected to the second input end of the boost logic control unit, the control end of the boost logic control unit is connected to the boost control signal, the first output end of the boost logic control unit outputs the boost P tube gate control signal, and the second output end of the boost logic control unit outputs the boost N tube gate control signal; the constant turn-off time generation unit is used for starting timing when the PWM comparator generates a boost N tube turn-off signal and generating a boost P tube turn-off signal when the timing time reaches a set time, and the boost logic control unit is used for generating the boost N tube grid control signal according to the boost N tube turn-off signal and generating the boost P tube grid control signal according to the boost P tube turn-off signal; and the substrate of the PMOS power tube is connected with the second working voltage, and the substrate of the NMOS power tube is connected with the source electrode of the NMOS power tube.

Optionally, the boost module further comprises: the overcurrent protection/zero-crossing detection unit is used for detecting the current of the voltage output end, generating an overcurrent signal when the current reaches a set peak current and generating a zero-crossing signal when the current reaches a set valley current; at this time, the boost logic control unit is further configured to generate a first turn-off signal according to the overcurrent signal to control the NMOS power transistor to turn off, and generate a second turn-off signal according to the zero-crossing signal to control the PMOS power transistor to turn off.

Optionally, the boost module further comprises: the short-circuit protection unit is used for detecting the duration time of the output voltage which is less than or equal to the set short-circuit voltage and generating a short-circuit signal when the duration time is greater than the set short-circuit time; at this time, the boost logic control unit is further configured to generate a total turn-off signal according to the short-circuit signal to control the NMOS power transistor and the PMOS power transistor to turn off.

Optionally, the boost logic control unit is further configured to generate a boost enable signal according to turning on and off of the NMOS power transistor and/or the PMOS power transistor.

Optionally, the linear charge boost chip further includes: the thermal shutdown module is used for detecting the temperature of the chip when the linear charging boost chip works in a boost mode, generating a boost thermal shutdown signal when the detected temperature is higher than a first set chip temperature, and generating a boost recovery signal when the detected temperature is lower than a second set chip temperature, wherein at the moment, the boost logic control unit is also used for generating a total shutdown signal according to the boost thermal shutdown signal to control the NMOS power tube and the PMOS power tube to be turned off, and generating a total recovery signal according to the boost recovery signal to control the NMOS power tube and the PMOS power tube to be turned on; the thermal shutdown module is further used for detecting the temperature of the chip when the linear charging voltage boosting chip works in a charging mode, and generating a charging thermal shutdown signal to finish charging when the detected temperature is higher than a third set chip temperature.

Optionally, the linear charge boost chip further includes: and the internal low voltage generation module is used for linearly stabilizing the input voltage to generate the internal low voltage.

Optionally, the linear charge boost chip further includes: the reference voltage generating module is used for generating a first reference voltage and a second reference voltage.

As described above, the linear charging boost chip of the present invention at least includes the under-voltage locking module, the linear charging module and the boost module, and the linear charging function and the boost function are simultaneously realized on one chip, thereby supporting high withstand voltage, having ultra-low working current, realizing area saving and having more excellent performance.

Drawings

Fig. 1 is a schematic circuit diagram of the linear charge boost chip according to the present invention.

Fig. 2 is a peripheral circuit diagram of the linear charge pump chip according to the present invention.

Fig. 3 is a flowchart illustrating the linear charge pump chip according to the present invention in the charge mode.

Fig. 4 is a flow chart of the linear charge pump chip in the boost mode according to the present invention.

Element number description: 100 under-voltage locking module, 200 linear charging module, 201 matching amplifier, 202 current loop, 203 full-charge comparator, 204 voltage loop, 205 input under-voltage comparison unit, 206 input over-voltage comparison unit, 207 charging logic control unit, 208 port over-voltage comparator, 209 battery temperature detection unit, 210 reverse-connection prevention unit, 300 boost module, 301 error amplifier, 302 ramp generator, 303 adder, 304 PWM comparator, 305 constant turn-off time generation unit, 306 boost logic control unit, 307 over-current protection/zero-crossing detection unit, 308 short-circuit protection unit, 400 working voltage generation module, 500 internal low-voltage generation module, 600 thermal turn-off module, 700 reference voltage generation module, 701 primary reference voltage generation unit, 702 secondary reference voltage generation unit.

Detailed Description

The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.

Please refer to fig. 1 to 4. It should be noted that the drawings provided in the present embodiment are only schematic and illustrate the basic idea of the present invention, and although the drawings only show the components related to the present invention and are not drawn according to the number, shape and size of the components in actual implementation, the form, quantity and proportion of the components in actual implementation may be changed arbitrarily, and the layout of the components may be more complicated.

As shown in fig. 1, the present embodiment provides a linear charging boost chip, which is suitable for a charging chamber of a True Wireless (TWS) bluetooth headset, and the linear charging boost chip includes: the under-voltage lockout module 100, the linear charging module 200 and the boost module 300,

the under-voltage locking module 100 is configured to compare the battery voltage VBAT with a first set voltage, generate a charging switching control signal according to the comparison result, and generate a boosting control signal when the battery voltage VBAT is not less than the first set voltage;

the linear charging module 200 is controlled by the charging switching control signal, and is configured to perform trickle charging or constant-current charging on the battery through the input voltage VIN, and terminate charging when the battery voltage VBAT reaches a full charging set value;

the boost module 300 is controlled by the boost control signal and is used for boosting the output voltage VOUT to reach an output set value.

Further, as shown in fig. 1, the linear charge boost chip further includes: the operating voltage generating module 400 is controlled by the enable signal EN and is configured to compare the input voltage VIN with the battery voltage VBAT and select a larger value thereof as the first operating voltage V1, compare the battery voltage VBAT with the output voltage VOUT and select a larger value thereof as the second operating voltage V2, compare the internal low voltage V4 with the second operating voltage V2 and select a larger value thereof as the third operating voltage V3 when the enable signal EN is active; the first operating voltage V1 and the internal low voltage V4 are used as the operating voltages of the linear charging module 200, the second operating voltage V2 is used as the operating voltage of the voltage boost module 300, and the third operating voltage V3 is used as the operating voltage of the under-voltage locking module 100, so as to ensure that each module uses the highest voltage as its operating voltage at any time, thereby ensuring the normal operation of each module.

Accordingly, as shown in fig. 1, the linear charge boost chip further includes: an internal low voltage generation module 500, configured to linearly regulate the input voltage VIN to generate the internal low voltage V4. In this embodiment, the internal low voltage is used to supply power to some devices in the linear charging module 200, so that these devices can be implemented by low voltage devices, and the problem of an excessively large area caused by using high voltage devices is avoided.

Specifically, the under-voltage lockout module 100 determines whether the battery voltage VBAT reaches the first setting voltage (e.g., 2.8V) by a resistor voltage division method, which may be implemented by a voltage division resistor and a comparator.

For the charging mode: when the battery voltage VBAT does not reach the first setting voltage (e.g., 2.8V), the under-voltage locking module 100 generates a charging switching control signal to control the linear charging module 200 to perform trickle charging on the battery; when the battery voltage VBAT reaches the first set voltage (e.g., 2.8V), the under-voltage locking module 100 generates a charging switching control signal to control the linear charging module 200 to perform constant current charging on the battery.

For boost mode: the under-voltage lockout module 100 generates a boost control signal to control the boost module 300 to boost only when the battery voltage VBAT reaches the first set voltage (e.g., 2.8V).

Specifically, as shown in fig. 1, the linear charging module 200 includes: a matching amplifier 201, a current loop 202, a full charge comparator 203, a voltage loop 204, a gate switch S1, a NAND gate NAND, a first diode D1, a second diode D2, a first high voltage NMOS tube HVNM1, a second high voltage NMOS tube HVNM2, a first high voltage PMOS tube HVPM1, a second high voltage PMOS tube HVPM2, a third high voltage PMOS tube HVPM3, a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4 and a fifth resistor R5, a gate of the first high voltage PMOS tube HVPM1 and a gate of the second high voltage PMOS tube HVPM2 are connected to a charge P tube gate control signal, a source of the first high voltage PMOS tube HVPM1 and a source of the second high voltage PMOS tube HVPM2 are connected to the input voltage, a drain of the first high voltage PMOS tube pm1 is connected to an inverting input terminal of the matching amplifier 201 and a source terminal of the third high voltage NMOS tube HVNM 4642, a drain of the first high voltage PMOS tube HVPM2 and a non-phase resistor 1 of the matching PMOS tube, and as a charging output terminal of the linear charging module 200, an output terminal of the matching amplifier 201 is connected to a gate of the third high voltage PMOS transistor HVPM3, a drain of the third high voltage PMOS transistor HVPM3 is connected to a non-inverting input terminal of the current loop 202 and an inverting input terminal of the full charge comparator 203, and is used as a charging current programming terminal of the linear charging module 200, the other terminal of the first resistor R1 is connected to a non-inverting input terminal of the voltage loop 204 and one terminal of the second resistor R2, an inverting input terminal of the current loop 202 is connected to the common terminal of the gate switch S1, an output terminal of the current loop 202 outputs a charging P-transistor gate control signal through the first diode D1, a connection node of the third resistor R3, the fourth resistor R4, and the fifth resistor R5 is connected in series between a first reference voltage REF1 and ground, and a connection node of the third resistor R3 and the fourth resistor R4 is connected to the first gate terminal of the gate switch S1, the connection node of the fourth resistor R4 and the fifth resistor R5 is connected to the second gate terminal of the gate switch S1 and the non-inverting terminal of the full charge comparator 203, the output terminal of the full charge comparator 203 is connected to an input terminal of the NAND gate NAND, the inverting terminal of the voltage ring 204 is connected to the first reference voltage REF1, the output terminal of the voltage ring 204 outputs another charge P-transistor gate control signal through the second diode D2, the other terminal of the second resistor R2 is connected to the drain of the first high voltage NMOS transistor HVNM1, the other terminal of the NAND gate NAND is connected to the charge switching control signal, the output terminal of the NAND gate is connected to the gate of the second high voltage NMOS transistor HVNM2, the source of the first high voltage transistor HVNM1 is grounded, the gate of the first high voltage transistor HVNM1 is connected to the gate of the second high voltage transistor HVNM2, and the source of the second high voltage transistor HVNM2 is grounded, the drain electrode of the second high voltage NMOS transistor HVNM2 is used as the charging state output terminal of the linear charging module 200; the gate switch S1 is controlled by the charge switching control signal, the substrate of the first high-voltage PMOS transistor HVPM1 and the substrate of the second high-voltage PMOS transistor HVPM2 are all connected to the first operating voltage V1, the substrate of the first high-voltage NMOS transistor HVNM1, the substrate of the second high-voltage NMOS transistor HVNM2 and the substrate of the third high-voltage PMOS transistor HVPM3 are all connected to their respective sources, the operating voltage of the current loop 202 and the operating voltage of the voltage loop 204 are all the first operating voltage V1, and the operating voltage of the matching amplifier 201, the operating voltage of the full charge comparator 203 and the operating voltage of the NAND gate are all the internal low-voltage V4. Optionally, the size ratio of the first high-voltage PMOS transistor HVPM1 to the second high-voltage PMOS transistor HVPM2 is 1: 1000, so that the branch current of the second high-voltage PMOS tube HVPM2 is 1000 times of the branch current of the first high-voltage PMOS tube HVPM 1.

The gating switch S1 is controlled by the charging switching control signal, so that the inverting input terminal of the current loop 202 is connected to different voltage values (e.g., 0.2V or 1V) to switch different charging current values, thereby implementing trickle charging or constant current charging; the voltage loop 204 utilizes a first resistor R1 and a second resistor R2 to perform resistance voltage division on the output, and compares the voltage with a first reference voltage REF1 to control the output according to the comparison result, so that the output is stabilized at a full-charge set value (such as 4.2V) based on negative feedback; the full charge comparator 203 is triggered when the charging current drops to a certain value (for example, 1/5 of the charging current under constant current charging) based on that the charging current begins to drop after the battery is fully charged, so that the output end of the charging state is changed into a high-resistance state, and thus, a light-emitting diode externally connected with the port does not emit light, and the charging end is displayed; the matching amplifier 201 enables the drain voltages of the first high-voltage PMOS transistor HVPM1 and the second high-voltage PMOS transistor HVPM2 to be consistent, and therefore the current after being mirrored 1000 times is more accurate. In the embodiment, the larger voltage of the input voltage VIN and the battery voltage VBAT is used as the substrate voltage of the first high-voltage PMOS transistor HVPM1 and the second high-voltage PMOS transistor HVPM2, so that the problem of voltage backflow occurring when the battery voltage VBAT is greater than the input voltage VIN in the first high-voltage PMOS transistor HVPM1 and the second high-voltage PMOS transistor HVPM2 is prevented.

Specifically, as shown in fig. 1, the linear charging module 200 further includes: an under-voltage input comparing unit 205, an over-voltage input comparing unit 206 and a charge logic control unit 207,

the under-voltage input comparing unit 205 is configured to compare the input voltage VIN with a second setting voltage, and generate an under-voltage input signal when the input voltage VIN is smaller than the second setting voltage;

the input overvoltage comparing unit 206 is configured to compare the input voltage VIN with a third setting voltage, and generate an input overvoltage signal when the input voltage VIN is greater than the third setting voltage;

the charging logic control unit 207 is configured to generate a charging P-channel turn-off signal according to the input under-voltage signal or the input over-voltage signal, so as to control the first high-voltage PMOS channel HVPM1 and the second high-voltage PMOS channel HVPM2 to turn off, so that the linear charging module 200 does not operate;

the working voltage of the input under-voltage comparing unit 205, the working voltage of the input over-voltage comparing unit 206, and the working voltage of the charge logic control unit 207 are all the internal low voltage V4.

More specifically, the undervoltage comparing unit 205 determines whether the input voltage VIN reaches the second set voltage (e.g. 3.8V) by a resistor-divider method, which may be implemented by a divider resistor and a comparator. The input over-voltage comparing unit 206 determines whether the input voltage VIN reaches the third setting voltage (e.g. 7.1V) by means of resistance voltage division, which may also be implemented by using a voltage dividing resistor and a comparator.

Specifically, as shown in fig. 1, the linear charging module further includes: a port over-voltage comparator 208 having a non-inverting input terminal connected to the drain of the third high voltage PMOS transistor HVPM3, an inverting input terminal connected to the first reference voltage VREF1, and an output terminal connected to the charge logic control unit 207, for comparing the voltage at the charge current programming terminal with the first reference voltage VREF1, and generating a port over-voltage signal when the voltage at the charge current programming terminal is greater than the first reference voltage VREF 1; at this time, the charging logic control unit 207 is further configured to generate a charging P-transistor turn-off signal according to the port overvoltage signal to control the first high-voltage PMOS transistor HVPM1 and the second high-voltage PMOS transistor HVPM2 to turn off, so that the linear charging module 200 does not operate, and the problem of excessive charging current caused by excessive port voltage is avoided; the working voltage of the port overvoltage comparator 208 is the internal low voltage V4.

Specifically, as shown in fig. 1, the linear charging module further includes: a battery temperature detecting unit 209 for detecting a battery temperature and generating a battery high temperature signal when the battery temperature is higher than a first set battery temperature and generating a battery low temperature signal when the battery temperature is lower than a second set battery temperature; at this time, the charging logic control unit 207 is further configured to generate a charging P-transistor turn-off signal according to the battery high-temperature signal or the battery low-temperature signal, so as to control the first high-voltage PMOS transistor HVPM1 and the second high-voltage PMOS transistor HVPM2 to turn off, so that the linear charging module 200 does not operate; the operating voltage of the battery temperature detecting unit 209 is the first operating voltage V1.

More specifically, the battery temperature detecting unit 209 detects the battery temperature by externally connecting a thermistor near the battery, when the battery temperature rises, the effective resistance of the thermistor becomes low, the corresponding resistor voltage division decreases, and when the resistor voltage division decreases to a certain value (e.g. 30% of the input voltage VIN), a battery high temperature signal is generated to trigger the battery high temperature protection; when the temperature of the battery decreases, the effective resistance value of the thermistor becomes high, the corresponding resistance division voltage increases, and when the resistance division voltage increases to a certain value (for example, 70% of the input voltage VIN), a battery low-temperature signal is generated to trigger the battery low-temperature protection. In practical application, the battery temperature detecting unit 209 may be implemented by using two comparators, wherein a non-inverting input terminal of the high temperature comparator is connected to 30% of the input voltage VIN, an inverting input terminal of the high temperature comparator is externally connected to the thermistor through the temperature detecting terminal, and an output terminal of the high temperature comparator is used for generating a high temperature signal of the battery; at this time, in order to enable the battery temperature detection unit 209 to operate normally, the temperature detection terminal should be connected to an input voltage through an external input resistor. Of course, the battery temperature detecting unit 209 may further include a shielding comparator, wherein the non-inverting input terminal of the shielding comparator is grounded, the inverting input terminal of the shielding comparator is connected to the temperature detecting terminal, and the output terminal of the shielding comparator is connected to the control terminals of the high temperature comparator and the low temperature comparator, so as to shield the high temperature comparator and the low temperature comparator (the output of the battery temperature detecting unit 209 is fixed to a level that does not affect the OFF signal of the device) when the temperature detecting terminal is grounded (instead of being connected to the input voltage through the external input resistor).

Specifically, as shown in fig. 1, the linear charging module further includes: the reverse connection preventing unit 210 is configured to generate a reverse connection signal when the battery voltage is a negative voltage; at this time, the charging logic control unit 207 is further configured to generate a charging P-channel turn-off signal according to the reverse connection signal, so as to control the first high voltage PMOS channel HVPM1 and the second high voltage PMOS channel HVPM2 to turn off, so that the linear charging module 200 does not operate; wherein, the operating voltage of the reverse connection preventing unit 210 is the internal low voltage V4.

More specifically, the reverse connection preventing unit 210 may be implemented by a comparator, a non-inverting input terminal of the comparator is connected to the battery voltage VBAT, an inverting input terminal of the comparator is grounded, and an output terminal of the comparator is used for generating a reverse connection signal; when the battery is reversely connected, the battery voltage VBAT is negative, and the comparator compares the battery voltage VBAT with the ground voltage and generates a reverse connection signal when the battery voltage VBAT is less than the ground voltage.

Specifically, when the charge logic control unit 207 generates the charge P-tube turn-OFF signal, it also generates a device turn-OFF signal OFF to turn OFF the matching amplifier 201, the current loop 202, the full charge comparator 203, and the voltage loop 204, so as to further save the working current in low power consumption; and when the linear charging module 200 further includes at least one of the port overvoltage comparator 208, the battery temperature detection unit 209, and the reverse connection prevention unit 210, the device shutdown signal OFF is further used to shut down at least one of the port overvoltage comparator 208, the battery temperature detection unit 209, and the reverse connection prevention unit 210.

Specifically, as shown in fig. 1, the boosting module 300 includes: a PMOS power tube PMOSFET, an NMOS power tube NMOSFET, an error amplifier 301, a ramp generator 302, an adder 303, a PWM comparator 304, a constant turn-off time generating unit 305, a boost logic control unit 306, a sixth resistor R6 and a seventh resistor R7, wherein the gate of the PMOS power tube PMOSFET is connected with a boost P tube gate control signal, the source of the PMOS power tube PMOSFET is used as the voltage output end of the boost module 300, the drain of the PMOS power tube PMOSFET is connected with the drain of the NMOS power tube NMOSFET, the source of the NMOS power tube NMOSFET is grounded, the gate of the NMOS power tube NMOSFET is connected with a boost N tube gate control signal, the sixth resistor R6 and the seventh resistor R7 are connected in series between the source of the PMOS power tube PMOSFET and the source of the NMOS power tube NMOSFET, the connection node of the sixth resistor R6 and the seventh resistor R7 is connected with the inverting input end of the error amplifier 301, the non-inverting input of the error amplifier 301 is connected to a second reference voltage REF2, the output of the error amplifier 301 is connected to the non-inverting input of the PWM comparator 304, the inverting input of the PWM comparator 304 is connected to the output of the adder 303, a first input of the adder 303 is connected to the output of the ramp generator 302, a second input terminal of the adder 303 is connected to the reference current IREF, an output terminal of the PWM comparator 304 is connected to a first input terminal of the boost logic control unit 306, an output terminal of the constant off-time generating unit 305 is connected to a second input terminal of the boost logic control unit 306, the control end of the boost logic control unit 306 is connected to the boost control signal, the first output end of the boost logic control unit 306 outputs the boost P-transistor gate control signal, a second output end of the boost logic control unit 306 outputs the boost N-tube gate control signal; the constant turn-off time generating unit 305 is configured to start timing when the PWM comparator 304 generates a boost N-transistor turn-off signal and generate a boost P-transistor turn-off signal when the timing time reaches a set time, and the boost logic control unit 306 is configured to generate the boost N-transistor gate control signal according to the boost N-transistor turn-off signal and generate the boost P-transistor gate control signal according to the boost P-transistor turn-off signal; and the substrate of the PMOS power tube PMOSFET is connected with the second working voltage V2, and the substrate of the NMOS power tube NMOSFET is connected with the source electrode of the NMOS power tube NMOSFET. In this embodiment, the constant turn-off time generating unit 305 is adopted to generate a turn-off signal of the boost P-tube, so that the stability of boost is better.

The output voltage VOUT is subjected to resistance voltage division through the sixth resistor R6 and the seventh resistor R7, and the error amplifier 301 performs error amplification on the resistance voltage division and the second reference voltage VREF2 to obtain a compensation voltage VCOMP; the ramp generator 302 generates a current proportional to the inductor current by detecting the inductor current when the NMOS power transistor NMOSFET is turned on, and adds the current to the reference current through an adder 303 to generate a ramp voltage by using the sum of the two currents; the PWM comparator 304 PWM compares the compensation voltage VCOMP with the ramp voltage to generate a boosted N-transistor turn-off signal; after generating the boost N-tube turn-off signal, the constant turn-off time generating unit 305 charges its internal capacitor with a current related to the output voltage VOUT, and generates a boost P-tube turn-off signal when the capacitor voltage reaches the battery voltage VBAT, so that the signal is adaptively related to the duty ratio of the output voltage VOUT and the battery voltage VBAT. It is noted that the reference current is a zero temperature drift current associated with the second reference voltage VREF 2.

Specifically, as shown in fig. 1, the boost module further includes: an overcurrent protection/zero-crossing detection unit 307 for detecting the current at the voltage output terminal and generating an overcurrent signal when it reaches a set peak current (e.g., 1A) and generating a zero-crossing signal when it reaches a set valley current (e.g., 50 mA); at this time, the boost logic control unit 306 is further configured to generate a first turn-off signal according to the over-current signal to control the NMOS power transistor NMOSFET to turn off, and generate a second turn-off signal according to the zero-crossing signal to control the PMOS power transistor PMOSFET to turn off.

Specifically, as shown in fig. 1, the boost module further includes: a short-circuit protection unit 308, configured to detect a duration of the output voltage VOUT being less than or equal to a set short-circuit voltage (e.g., VBAT-0.2V), and generate a short-circuit signal when the duration is greater than the set short-circuit time (e.g., 40 ms); at this time, the boost logic control unit 306 is further configured to generate a total turn-off signal according to the short-circuit signal to control the NMOS power tube NMOSFET and the PMOS power tube PMOSFET to turn off, and of course, may also control one of the NMOS power tube NMOSFET and the PMOS power tube PMOSFET to turn off through the total turn-off signal, which has no influence on this embodiment.

Specifically, the boost logic control unit 306 is further configured to generate a boost enable signal according to the turn-on and turn-off of the NMOS power transistor and/or the PMOS power transistor, so as to turn off the error amplifier, the ramp generator, the PWM comparator, and the constant turn-off time generation unit when at least one of the NMOS power transistor and the PMOS power transistor is turned off, thereby further saving the working current in low power consumption; when the boost module 300 further includes an overcurrent protection/zero-crossing detection unit 307 and/or a short-circuit protection unit 308, the boost enable signal further controls the overcurrent protection/zero-crossing detection unit 307 and/or the short-circuit protection unit 308.

Specifically, as shown in fig. 1, the linear charging boost chip further includes: a thermal shutdown module 600, configured to detect a chip temperature when the linear charging boost chip operates in a boost mode, generate a boost thermal shutdown signal when the detected temperature is greater than a first set chip temperature (e.g., 150 ℃), generate a boost recovery signal when the detected temperature is less than a second set chip temperature (e.g., 130 ℃), and at this time, the boost logic control unit 306 is further configured to generate a total shutdown signal according to the boost thermal shutdown signal to control the NMOS power transistor NMOSFET and the PMOS power transistor PMOSFET to be turned off, and generate a total recovery signal according to the boost recovery signal to turn on the NMOS power transistor NMOSFET and the PMOS power transistor PMOSFET; the thermal shutdown module 600 is further configured to detect a chip temperature when the linear charging boost chip operates in a charging mode, generate a charging thermal shutdown signal when the detected temperature is greater than a third set chip temperature (e.g., 100 ℃), and directly control the first high-voltage PMOS transistor HVPM1 and the second high-voltage PMOS transistor HVPM2 to be turned off through a third diode D3, so as to end charging; wherein the operating voltage of the thermal shutdown module 600 is the third operating voltage V3.

Specifically, as shown in fig. 1, the linear charging boost chip further includes: a reference voltage generating module 700 for generating the first reference voltage VREF1 and the second reference voltage VREF 2.

More specifically, the reference voltage generating module 700 includes: a primary reference voltage generating unit 701 and a secondary reference voltage generating unit 702, the primary reference voltage generating unit 701 being configured to generate a second reference voltage VREF2 with zero temperature drift, the secondary reference voltage generating unit 702 being configured to generate a first reference voltage VREF1 by operational amplification of the second reference voltage VREF 2; the operating voltage of the primary reference voltage generating unit 701 is the third operating voltage, and the operating voltage of the secondary reference voltage generating unit 702 is the internal low voltage V4. In this embodiment, the first reference voltage VREF1 has a stronger resistance voltage dividing capability, so that more accurate resistance voltage division can be obtained after passing through the third resistor R3, the fourth resistor R4 and the fifth resistor R5.

FIG. 2 is a design of a peripheral circuit of the linear charge pump chip of this embodiment when applied, in which a charge current programming terminal (i.e., an ISET pin) is externally connected to a programming resistor R_IsetTo ground, the charging current satisfies formula I_BAT=（V_Iset/R_Iset) 1000, wherein I_BATFor charging current, V_IsetIs the port voltage, R_IsetIs the resistance value of the programming resistor; the input port (namely a VIN pin) is externally connected with at least 1 mu F of bypass capacitor Cin to the ground, and can support 4.25V-16V of input voltage; the charging output end (namely a VBAT pin) is externally connected with the lithium battery pack to the ground, and is also externally connected with a 10uf capacitor C1 to the ground; the drain output end (namely the SW pin) is externally connected with a 2.2uH inductor L to the charging output end; when the temperature detection terminal (namely, the NTC pin) works normally, the temperature detection terminal is connected to the input port through the resistor Rntc _ vin, and is connected to the ground through the thermistor Rntc, and if the temperature detection function is disabled, the temperature detection terminal is connected to the ground through the resistor Rntc _ gnd (for convenience of explanation, both cases are shown in fig. 2, but in practical application, the temperature detection terminal is connected to the input port through the resistor Rntc _ vin or is connected to the ground through the resistor Rntc _ gnd); the charging state output end (namely CHRG pin) is externally connected with a light emitting diode and a resistor Rchrg to the input port, and whether charging is carried out or not is displayed through the on and off of the light emitting diode; the enable terminal (i.e. the EN pin) is usually the same as the voltage of the charging output terminal, and when the enable terminal is connected to the ground, the boost module of the chip is really turned off; the voltage output terminal (i.e., VOUT pin) is externally connected to the output capacitor Cout of 10uf to ground. The linear charging and boosting chip is used as a linear charging and boosting two-in-one chip, structurally realizes that a single chip has the functions of linear charging and boosting, and saves the area of the chip.

Referring to fig. 3 and 4, the operation of the linear charge boost chip in the charge mode and the boost mode will be described in detail with reference to fig. 1 and 2.

For the charging mode (as shown in fig. 3):

1) when the battery voltage VBAT does not reach a first set voltage (such as 2.8V), the linear charging voltage boost chip performs trickle charging on the battery;

2) when the battery voltage VBAT reaches a first set voltage (e.g., 2.8V), the linear charging boost chip performs constant-current charging on the battery, and finally stabilizes the battery voltage VBAT at a full-charge set value (e.g., 4.2V), and ends the charging.

Before charging, the linear charging boost chip also needs to perform input under-voltage detection and input overvoltage detection on an input voltage VIN, perform reverse connection prevention detection on a battery, perform overvoltage detection on the voltage of a charging current programming end and the like, and charge the battery when all detections have no problem; during the charging process, the above detection is also performed.

For boost mode (as shown in fig. 4):

1) judging whether the enable signal is effective and whether the battery voltage VBAT reaches a first set voltage (such as 2.8V) or not, and starting boosting when the enable signal and the battery voltage VBAT meet the first set voltage;

2) controlling the NMOS power tube NMOSFET and the PMOS power tube PMOSFET to be conducted through the boost logic control unit 306 so as to carry out boost operation on the output voltage VOUT;

3) when the output voltage VOUT exceeds the battery voltage VBAT, the error amplifier 301, the ramp generator 302, the adder 303, the PWM comparator 304, the constant off-time generation unit 305, and the boost logic control unit 306 turn on soft-start current limitation, so that the output voltage VOUT is stabilized at an output set value.

Before boosting, the linear charging and boosting chip also needs to perform boosting thermal shutdown triggering judgment; after the soft start current limitation is started, the linear charging boost chip also needs to perform boost thermal shutdown trigger judgment and short-circuit protection judgment, and certainly, overcurrent detection/zero-crossing detection can also be performed.

In summary, the linear charging boost chip of the present invention at least includes the under-voltage locking module, the linear charging module and the boost module, and the linear charging function and the boost function are simultaneously realized on one chip, thereby supporting high withstand voltage, having ultra-low working current, saving area, and having more excellent performance. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.

The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.