阅读说明：本技术 H桥驱动电路、控制方法及驱动电机 (H-bridge driving circuit, control method and driving motor ) 是由 张长洪 袁莹莹 于 2020-04-21 设计创作，主要内容包括：本发明公开了一种H桥驱动电路、控制方法及驱动电机,驱动电路包括两路相同的驱动模块,每路驱动模块均包括串联于第一电源端与接地端之间的上功率管和下功率管,以及第一驱动控制模块和第二驱动控制模块,所述第一驱动控制模块分别与所述上功率管的栅极和源极连接,接收外部控制信号,并根据外部控制信号和所述上功率管的源极电压调节所述上功率管的栅极电压,所述第二驱动模块与所述下功率管的栅极连接,用于控制所述下功率管在所述上功率管的关断状态下导通,其中,在所述上功率管关断状态下,所述上功率管的栅极与源极之间的电压差恒定。该桥驱动电路实现了功率管关断状态下H的安全保护。(The invention discloses an H-bridge driving circuit, a control method and a driving motor, wherein the driving circuit comprises two identical driving modules, each driving module comprises an upper power tube and a lower power tube which are connected in series between a first power end and a ground end, and a first driving control module and a second driving control module, the first driving control module is respectively connected with a grid electrode and a source electrode of the upper power tube, receives an external control signal and adjusts the grid voltage of the upper power tube according to the external control signal and the source electrode voltage of the upper power tube, the second driving module is connected with the grid electrode of the lower power tube and is used for controlling the lower power tube to be conducted in the turn-off state of the upper power tube, and the voltage difference between the grid electrode and the source electrode of the upper power tube is constant in the turn-off state of the upper power tube. The bridge driving circuit realizes the safety protection of the power tube in the off state.)

1. An H-bridge driving circuit comprises two identical driving modules, each driving module comprises an upper power tube and a lower power tube which are connected in series between a first power end and a ground end, a first driving control module for controlling the upper power tube and a second driving control module for controlling the lower power tube, and is characterized in that,

the first drive control module is respectively connected with the grid electrode and the source electrode of the upper power tube, receives an external control signal and adjusts the grid electrode voltage of the upper power tube according to the external control signal and the source electrode voltage of the upper power tube,

the second driving module is connected with the grid electrode of the lower power tube and is used for controlling the lower power tube to be conducted under the off state of the upper power tube,

and under the off state of the upper power tube, the voltage difference between the grid electrode and the source electrode of the upper power tube is constant.

2. The H-bridge driver circuit of claim 1, further comprising:

the clamping module is connected between the grid electrode and the source electrode of the upper power tube and used for clamping the grid electrode voltage of the upper power tube.

3. The H-bridge driver circuit of claim 2, wherein the first drive control module comprises:

the source electrode of the first transistor is connected with a second power supply end, the grid electrode of the first transistor receives a control signal, and the drain electrode of the first transistor is connected with the grid electrode of the upper power tube;

the drain electrode of the second transistor is connected with the grid electrode of the upper power tube, the source electrode of the second transistor is connected with the source electrode of the upper power tube, and the grid electrode of the second transistor receives one of the first charging current, the second charging current, the first discharging current and the second discharging current;

a first capacitor connected between the gate and the source of the second transistor,

the first capacitor is charged and discharged by the first charging current, the second charging current, the first discharging current and the second discharging current, so that on/off control over the second transistor is achieved.

4. The H-bridge driver circuit of claim 3, wherein the first drive control module further comprises:

a first diode having a cathode connected to the gate of the second transistor and an anode connected to the source of the second transistor,

wherein the first diode is a zener diode.

5. The H-bridge driver circuit according to claim 4, wherein the first transistor is a PMOS transistor and the second transistor is an NMOS transistor.

6. The H-bridge driver circuit of claim 5, wherein the first drive control module further comprises:

a third transistor, a source connected to a second power terminal through a first current source, a gate receiving a first driving signal, and a drain connected to a gate of the second transistor;

a fourth transistor, a source connected to the ground terminal through a second current source, a gate receiving the second driving signal, and a drain connected to the gate of the second transistor;

a fifth transistor, a source connected to the second power source terminal through a third current source, a gate receiving the third driving signal, and a drain connected to the gate of the second transistor;

a sixth transistor having a source connected to a ground terminal via a fourth current source, a gate receiving a fourth driving signal, and a drain connected to the gate of the second transistor,

the first current source is used for providing a first charging current, the second current source is used for providing a first discharging current, the third current source is used for providing a second charging current, and the fourth current source is used for providing a second discharging current.

7. The H-bridge driver circuit according to claim 6, wherein when discharging the first capacitor, the third transistor and the fifth transistor are turned off, the fourth transistor is turned on, the first capacitor is discharged by the first discharge current, and the sixth transistor is turned on after the fourth transistor is turned off, the first capacitor is discharged by the second discharge current;

when the first capacitor is charged, the fourth transistor and the sixth transistor are turned off, the third transistor is turned on, the first capacitor is charged by the first charging current, and the fifth transistor is turned on after the third transistor is turned off, and the first capacitor is charged by the second charging current.

8. The H-bridge driving circuit according to claim 7, wherein the first charging current has a magnitude greater than that of the second charging current, and the first discharging current has a magnitude greater than that of the second discharging current.

9. The H-bridge driver circuit of claim 7, wherein the first and second drive signals have an active time substantially less than an inactive time within a cycle,

wherein the third transistor is turned on when the first driving signal is active, and the fourth transistor is turned on when the second driving signal is active.

10. The H-bridge driver circuit according to claim 8, wherein the third transistor and the fifth transistor are PMOS transistors, and the fourth transistor and the sixth transistor are NMOS transistors.

11. The H-bridge driver circuit of claim 2, wherein the clamping module comprises:

the anode of the second diode is connected with the grid of the upper power tube;

a cathode of the third diode is connected with the cathode of the second diode, an anode of the third diode is connected with the source electrode of the upper power tube,

wherein the second diode and the third diode are zener diodes.

12. A control method of an H-bridge drive circuit comprises two identical drive modules, wherein each drive module comprises an upper power tube and a lower power tube which are connected in series between a first power supply end and a ground end, and the control method is characterized by comprising the following steps:

when the upper power tube is conducted, the grid electrode of the upper power tube is disconnected from the source electrode, and the grid electrode voltage of the upper power tube is pulled up;

when the upper power tube is turned off, the grid electrode and the source electrode of the upper power tube are in short circuit, the grid electrode voltage of the upper power tube is adjusted according to the source electrode voltage of the upper power tube,

and a transistor is connected between the grid electrode and the source electrode of the upper power tube.

13. The method of claim 12, wherein electrically disconnecting the gate and the source of the upper power transistor comprises:

instantaneously discharging the grid of the transistor by adopting a first discharge current;

the gate of the transistor is constantly discharged with a second discharge current,

wherein the first discharge current is greater than the second discharge current.

14. The method of claim 12, wherein shorting the gate and the source of the upper power transistor comprises:

instantaneously charging the grid of the transistor by adopting a first charging current;

the gate of the transistor is constantly charged with a second charging current,

wherein the first charging current is greater than the second charging current.

15. A drive motor characterized in that the drive motor is provided with an H-bridge drive circuit according to any one of claims 1 to 11.

Technical Field

The invention relates to the technical field of power electronics, in particular to an H-bridge driving circuit, a control method and a driving motor.

Background

The H-bridge (also called full-bridge) driving circuit is a typical dc motor control circuit, and is composed of two identical circuits through the switching of switches, wherein in each circuit, one of the two power tubes can conduct to the positive electrode to realize pull-up, and the other can conduct to the negative electrode to realize pull-down, or vice versa. The two paths always maintain opposite outputs, so that the polarity of the load can be reversed under the condition of a single power supply. The connection method is added with a middle load, and the drawn shape is like an H word, so that the name of the H bridge is obtained.

The existing driving scheme for H-bridge power transistors is generally direct driving, as shown in fig. 1, fig. 1 shows a circuit structure diagram of an existing H-bridge driving circuit, where each circuit includes an upper power transistor (Mpwr1, Mpwr2) and a lower power transistor (Mpwr3, Mpwr4), and a connection point of the upper power transistor and the lower power transistor corresponds to an output node (OUT1, OUT 2). The transistor M1 and the transistor M2 receive control signals IN1 and IN2, respectively, when the transistor M1 is turned on, the transistor M2 is turned off, the potential of the node a is pulled up to VCP (VCP is a charge pump potential greater than VCC), and the gate-source voltage Vgs of the upper power tube Mpwr1 is greater than the turn-on voltage Vth thereof, that is, the upper power tube Mpwr1 is turned on; when the transistor M1 is turned off and the transistor M2 is turned on, the potential of the node a is pulled down to GND, and the gate-source voltage Vg of the upper power tube Mpwr1 is smaller than the turn-on voltage Vth thereof, i.e., the upper power tube Mpwr1 is turned off. The scheme can realize the switching control of the upper power tube Mpwr1, but has the following defects:

when the motor normally operates, the upper power tube Mpwr2 and the lower power tube Mpwr3 are turned on, the upper power tube Mpwr1 and the lower power tube Mpwr4 are turned off, the winding coil current in the motor is Iload (as shown in the figure), all the power tubes are immediately turned off next, the potential of the node a is pulled down to GND, the first output node OUT1 is raised by the energy in the load inductor of the motor because the current in the inductor cannot suddenly change, namely the load current Iload needs to flow through the body diodes of the upper power tube Mpwr1 and the lower power tube Mpwr4, if the energy stored in the inductor is large enough, the clamp tubes D1 and D2 are not enough to protect the upper power tube Mpwr1, the source of the upper power tube Mpwr1 (i.e., the first output node 1) is raised (the upper limit is VCC + iod), the source grid voltage of the source is larger than the safe voltage vswr 365, and the clamp tube is damaged far away from the upper power tube.

Meanwhile, when the potential of the node a is pulled down to GND, the upper power tube Mpwr1 is turned off, and the first output node OUT1 is short-circuited to VCC, which may cause the source-gate voltage Vsg of the upper power tube Mpwr1 to be much greater than the safety voltage, such as 5.5V, and may cause the upper power tube Mpwr1 to be damaged.

By the driving mode, the clamping tubes D1 and D2 are in a large-current protection state for a long time (when the inductance and the large current are in large load, the follow current process lasts for a period of time) or all the time (in a constant short circuit VCC state), the impact on a common source GND in a chip is very large, and further, the impact on other modules is greatly influenced.

Therefore, there is a need to provide an improved technical solution to overcome the above technical problems in the prior art.

Disclosure of Invention

In order to solve the technical problem, the invention provides an H-bridge driving circuit, a control method and a driving motor, which realize safety protection of an H-bridge power tube in a turn-off state.

The H-bridge driving circuit provided by the invention comprises two identical driving modules, each driving module comprises an upper power tube and a lower power tube which are connected in series between a first power supply end and a ground end, and a first drive control module for controlling the upper power tube and a second drive control module for controlling the lower power tube, it is characterized in that the first drive control module is respectively connected with the grid electrode and the source electrode of the upper power tube and receives external control signals, and adjusting the grid voltage of the upper power tube according to an external control signal and the source voltage of the upper power tube, the second driving module is connected with the grid electrode of the lower power tube and is used for controlling the lower power tube to be conducted under the off state of the upper power tube, and under the off state of the upper power tube, the voltage difference between the grid electrode and the source electrode of the upper power tube is constant.

Preferably, the H-bridge driving circuit further includes: the clamping module is connected between the grid electrode and the source electrode of the upper power tube and used for clamping the grid electrode voltage of the upper power tube.

Preferably, the first drive control module includes: the source electrode of the first transistor is connected with a second power supply end, the grid electrode of the first transistor receives a control signal, and the drain electrode of the first transistor is connected with the grid electrode of the upper power tube; the drain electrode of the second transistor is connected with the grid electrode of the upper power tube, the source electrode of the second transistor is connected with the source electrode of the upper power tube, and the grid electrode of the second transistor receives one of the first charging current, the second charging current, the first discharging current and the second discharging current; and the first capacitor is connected between the grid electrode and the source electrode of the second transistor, wherein the first capacitor is charged and discharged by the first charging current, the second charging current, the first discharging current and the second discharging current so as to realize on/off control of the second transistor.

Preferably, the first drive control module further comprises: and the cathode of the first diode is connected with the grid electrode of the second transistor, and the anode of the first diode is connected with the source electrode of the second transistor, wherein the first diode is a Zener diode.

Preferably, the first transistor is a PMOS transistor, and the second transistor is an NMOS transistor.

Preferably, the first drive control module further comprises: a third transistor, a source connected to a second power terminal through a first current source, a gate receiving a first driving signal, and a drain connected to a gate of the second transistor; a fourth transistor, a source connected to the ground terminal through a second current source, a gate receiving the second driving signal, and a drain connected to the gate of the second transistor; a fifth transistor, a source connected to the second power source terminal through a third current source, a gate receiving the third driving signal, and a drain connected to the gate of the second transistor; and a source of the sixth transistor is connected with a ground terminal through a fourth current source, a gate of the sixth transistor receives a fourth driving signal, and a drain of the sixth transistor is connected with a gate of the second transistor, wherein the first current source is used for providing a first charging current, the second current source is used for providing a first discharging current, the third current source is used for providing a second charging current, and the fourth current source is used for providing a second discharging current.

Preferably, when the first capacitor is discharged, the third transistor and the fifth transistor are turned off, the fourth transistor is turned on, the first capacitor is discharged by the first discharge current, and the sixth transistor is turned on after the fourth transistor is turned off, and the first capacitor is discharged by the second discharge current; when the first capacitor is charged, the fourth transistor and the sixth transistor are turned off, the third transistor is turned on, the first capacitor is charged by the first charging current, and the fifth transistor is turned on after the third transistor is turned off, and the first capacitor is charged by the second charging current.

Preferably, the intensity of the first charging current is greater than the intensity of the second charging current, and the intensity of the first discharging current is greater than the intensity of the second discharging current.

Preferably, the active time of the first driving signal and the second driving signal in one period is much shorter than the inactive time, wherein when the first driving signal is active, the third transistor is turned on, and when the second driving signal is active, the fourth transistor is turned on.

Preferably, the third transistor and the fifth transistor are PMOS transistors, and the fourth transistor and the sixth transistor are NMOS transistors.

Preferably, the clamping module comprises: the anode of the second diode is connected with the grid of the upper power tube; and the cathode of the third diode is connected with the cathode of the second diode, the anode of the third diode is connected with the source electrode of the upper power tube, and the second diode and the third diode are Zener diodes.

According to the control method of the H-bridge drive circuit provided by the invention, the H-bridge drive circuit comprises two identical drive modules, each drive module comprises an upper power tube and a lower power tube which are connected in series between a first power supply end and a ground end, and the control method comprises the following steps: when the upper power tube is conducted, the grid electrode of the upper power tube is disconnected from the source electrode, and the grid electrode voltage of the upper power tube is pulled up; when the upper power tube is turned off, the grid electrode and the source electrode of the upper power tube are in short circuit, and the grid electrode voltage of the upper power tube is adjusted according to the source electrode voltage of the upper power tube, wherein a transistor is connected between the grid electrode and the source electrode of the upper power tube.

Preferably, the step of electrically disconnecting the gate and the source of the upper power tube comprises: instantaneously discharging the grid of the transistor by adopting a first discharge current; and constantly discharging the grid of the transistor by adopting a second discharge current, wherein the first discharge current is larger than the second discharge current.

Preferably, the step of shorting the gate and the source of the upper power transistor comprises: instantaneously charging the grid of the transistor by adopting a first charging current; and constantly charging the grid electrode of the transistor by adopting a second charging current, wherein the first charging current is larger than the second charging current.

According to the driving motor provided by the invention, the H-bridge driving circuit is arranged on the driving motor.

The invention has the beneficial effects that: according to the H-bridge driving circuit, the control method and the driving motor, the driving control module is arranged between the grid electrode and the source electrode of the upper power tube, so that the grid electrode and the source electrode of the power tube are in short circuit in the off state, the grid source voltage of the power tube floats relative to the voltage of the output node, the grid source voltage of the power tube is always constant to 0V no matter how the voltage of the external output node acts, and the safety protection of the power tube in the off state is realized.

The clamping module is arranged between the source electrode and the grid electrode of the upper power tube, the grid electrode voltage of the upper power tube can be clamped, the upper power tube is prevented from being damaged due to overhigh voltage, meanwhile, the upper power tube can be prevented from being conducted mistakenly, and the accuracy of H-bridge driving is improved.

The clamping diode is arranged between the grid electrode and the source electrode of the second transistor, the grid electrode voltage of the second transistor can be clamped, damage to the second transistor due to overhigh voltage is prevented, meanwhile, the second transistor can be prevented from being conducted mistakenly, and the accuracy of driving control over the upper power transistor is improved.

The grid voltage control of the second transistor is realized by adopting a mode of charging and discharging the first capacitor, the accuracy of on-off control of the transistor is ensured, meanwhile, the capacitor is rapidly charged and discharged by a large pulse current instantly when the switch of the switch tube is switched, and in other constant processes, the grid potential of the switch tube is maintained only by a minimum current source, so that the rapid driving of the power tube is realized, and the average power loss of the circuit is reduced.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention, as claimed.

Drawings

The above and other objects, features and advantages of the present invention will become more apparent from the following description of the embodiments of the present invention with reference to the accompanying drawings.

Fig. 1 shows a circuit configuration diagram of an H-bridge driver circuit in the prior art;

fig. 2 is a block diagram illustrating an H-bridge driving circuit according to an embodiment of the present invention;

fig. 3 is a circuit configuration diagram of an H-bridge driver circuit according to an embodiment of the present invention;

fig. 4 is a flow chart illustrating a control method of an H-bridge driver circuit according to an embodiment of the present invention.

Detailed Description

To facilitate an understanding of the invention, the invention will now be described more fully with reference to the accompanying drawings. Preferred embodiments of the present invention are shown in the drawings. The invention may, however, be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The terminology used herein in the description of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention.

The present invention will be described in detail below with reference to the accompanying drawings.

Fig. 2 shows a block diagram of an H-bridge driver circuit according to an embodiment of the present invention.

As shown in fig. 2, in this embodiment, the H-bridge driving circuit includes two identical driving modules, each of which includes an upper power transistor and a lower power transistor connected in series between the first power terminal VCC and the ground terminal (the driving module of the left path includes an upper power transistor Mpwr1 and a lower power transistor Mpwr3, and the driving module of the right path includes an upper power transistor Mpwr2 and a lower power transistor Mpwr 4). Wherein, L is a load such as an equivalent coil of the motor, and two ends of the L are respectively connected with the output nodes OUT1 and OUT2 of the two driving modules.

Herein, only one of the driving modules, such as the driving module of the left one of the driving modules (for detailed description, the driving module of the other driving module (the right one of the driving modules) may refer to the driving module of the left one of the driving modules, and will not be described herein again.

In this embodiment, the driving module of the left path includes an upper power transistor Mpwr1, a lower power transistor Mpwr3, a first driving control module 101 for controlling the upper power transistor Mpwr1, and a second driving control module 102 for controlling the lower power transistor Mpwr 3.

The drain of the upper power transistor Mpwr1 is connected to the first power supply terminal VCC, and the source of the upper power transistor Mpwr1 is connected to the first output node OUT 1.

The drain of the lower power tube Mpwr3 is connected to the first output node OUT1, and the source of the lower power tube Mpwr3 is connected to the ground GND.

In this embodiment, the upper power tubes Mpwr1 and Mpwr2 and the lower power tubes Mpwr3 and Mpwr3 all use NMOS transistors.

The first driving control module 101 is respectively connected with the gate and the source of the upper power tube Mpwr1, receives an external control signal, and adjusts the gate voltage of the upper power tube Mpwr1 according to the external control signal and the source voltage of the upper power tube Mpwr1, and the voltage difference Vgs _ Mpwr1 between the gate and the source of the upper power tube is constant and approximately 0V during the turn-off period of the upper power tube Mpwr 1.

When the upper power tube Mpwr1 is turned off, the first drive control module 101 adjusts the gate voltage of the upper power tube Mpwr1 according to the source voltage of the upper power tube Mpwr1, so that the gate voltage of the upper power tube Mpwr1 floats relative to the source voltage, and the power tube is prevented from being damaged when the source voltage is too high. And the gate-source voltage Vgs _ Mpwr1 of the power tube is constantly smaller than the turn-on threshold voltage Vth _ Mpwr1 of the power tube, so that the safety protection of the power tube in the turn-off state is realized.

The second driving control module 102 is respectively connected to the gate and the source of the lower power tube Mpwr3, receives an external control signal, and adjusts the gate voltage of the lower power tube Mpwr3 according to the external control signal and the source voltage of the lower power tube Mpwr 3. Further, since the source of the lower power transistor Mpwr3 is grounded and the gate-source voltage Vgs _ Mpwr3 thereof is not affected by the voltage at the output node OUT, the second driving control module 102 can directly adjust the gate voltage of the lower power transistor Mpwr3, thereby controlling the lower power transistor Mpwr3 to be turned on in the off state of the upper power transistor Mpwr 1.

Preferably, a clamping module is arranged between the source and the gate of each of the upper power transistor and the lower power transistor, for example, a clamping module 201 is connected between the gate and the source of the upper power transistor Mpwr1, and a clamping module 202 is connected between the gate and the source of the lower power transistor Mpwr3, and is used for clamping the gate voltage of the power transistor, preventing the power transistor from being damaged due to overhigh voltage, and avoiding the power transistor from being turned on by mistake.

In this embodiment, the driving control module is disposed between the source and the gate of the power transistor in the H-bridge driving circuit to adjust the gate voltage of the power transistor according to the external control signal and the source voltage of the power transistor, so that the gate-source voltage of the power transistor floats relative to the voltage of the output node (i.e., the source voltage of the upper power transistor) in the off state, and the gate-source voltage of the power transistor is always constant at 0V no matter how the voltage of the external output node acts, thereby implementing the safety protection in the off state of the power transistor.

Fig. 3 shows a circuit structure diagram of an H-bridge driver circuit according to an embodiment of the present invention.

As shown in fig. 3, in the present embodiment, the first drive control module 101 includes a control unit and a charge and discharge unit. The control unit is connected with the grid electrode and the source electrode of the upper power tube Mpwr1, receives the control signal CLKH and the charging and discharging current, and adjusts the grid-source voltage Vgs _ Mpwr1 of the upper power tube Mpwr1 according to the control signal CLKH and the charging and discharging current. The charging and discharging unit is connected with the control unit, receives a plurality of driving signals (including a first driving signal INH1, a second driving signal INL1, a third driving signal INH2 and a fourth driving signal INL2), and outputs a first charging current and a second charging current or a first discharging current and a second discharging current in a time-sharing manner according to the plurality of driving signals.

The first charging current is larger than the second charging current, and the first discharging current is larger than the second discharging current. Furthermore, the charging and discharging unit outputs a first charging current or a first discharging current instantly (in nanosecond time), and then outputs a second charging current or a second discharging current constantly.

In this embodiment, the control unit includes: a first transistor M11, a second transistor M12, and a first capacitor C11. The source of the first transistor M11 is connected to the second power supply terminal VCP, the gate of the first transistor M11 receives the control signal CLKH, and the drain of the first transistor M11 is connected to the gate of the upper power transistor Mpwr 1. The drain of the second transistor M12 is connected to the gate of the upper power transistor Mpwr1, the source of the second transistor M12 is connected to the source of the upper power transistor Mpwr1, and the gate of the second transistor M12 receives charge and discharge current. The first capacitor C11 is connected between the gate and the source of the second transistor M12, and the charging and discharging current is used for adjusting the gate-source voltage of the second transistor M12 by charging and discharging the first capacitor C11, thereby realizing on/off control of the second transistor M12.

Further, the first transistor M11 is a PMOS transistor, and the second transistor M12 is an NMOS transistor.

When the control signal CLKH controls the first transistor M11 to be turned on, the first capacitor C11 receives a discharge current, the gate-source voltage Vgs _ M12 of the second transistor M12 is smaller than the turn-on threshold voltage Vth _ M12, the second transistor M12 is turned off, at this time, the gate voltage of the upper power tube Mpwr1 is pulled up to the voltage corresponding to the second power supply terminal VCP, the gate-source voltage Vgs _ Mpwr1 of the upper power tube Mpwr1 is larger than the turn-on threshold voltage Vth _ Mpwr1, and the upper power tube Mpwr1 is turned on.

Further, the power supply voltage corresponding to the second power supply terminal VCP is greater than the power supply voltage corresponding to the first power supply terminal VCC. The supply voltage corresponding to the second supply terminal VCP is supplied to the charge pump, for example.

When the control signal CLKH controls the first transistor M11 to turn off, the first capacitor C11 receives a charging current, the gate-source voltage Vgs _ M12 of the second transistor M12 is greater than its turn-on threshold voltage Vth _ M12, the second transistor M12 is turned on, at this time, the gate voltage of the upper power tube Mpwr1 is pulled down to be the same as its source voltage, i.e., the gate-source voltage Vgs _ Mpwr1 of the upper power tube Mpwr1 is equal to 0 (after a steady state, i.e., after the charging and discharging of the corresponding capacitor are completed, there is no current in the second transistor M12 and thus no turn-on voltage drop across the second transistor M12), the gate-source voltage Vgs _ Mpwr1 of the upper power tube Mpwr1 is less than its turn-on threshold voltage Vth _ Mpwr1, and the upper power tube Mpwr1 is turned off.

Based on the above description, in the off state of the upper power transistor Mpwr1 (i.e., during the on period of the second transistor M12), the gate voltage of the upper power transistor Mpwr1 changes in a relatively floating manner with respect to the source voltage thereof (i.e., the voltage at the first output node OUT1 of the H-bridge driver circuit), so that the gate-source voltage Vgs of the upper power transistor Mpwr1 is always constant at 0V regardless of the action of the voltage at the first output node OUT1, thereby achieving the safety protection in the off state of the power transistor.

Further, the control unit also comprises a first diode D11. The first diode D11 is a zener diode, and its cathode is connected to the gate of the second transistor M12, and its anode is connected to the source of the second transistor M12. The first diode D11 can clamp the gate voltage of the second transistor M12, prevent the second transistor M12 from being damaged when the voltage is too high, and prevent the second transistor M12 from being turned on by mistake.

In the charge/discharge unit, the first current source I11, the third transistor M13, the fourth transistor M14 and the second current source I12 are sequentially connected in series between the second power terminal VCP and the ground terminal GND, and a first charge current or a first discharge current is output at a connection node of the third transistor M13 and the fourth transistor M14. The third current source I13, the fifth transistor M15, the sixth transistor M16 and the fourth current source I14 are sequentially connected in series between the second power source terminal VCP and the ground terminal GND, and a connection node of the fifth transistor M15 and the sixth transistor M16 outputs a second charging current or a second discharging current. Further, the gate of the third transistor M13 receives the first driving signal INH1, the gate of the fourth transistor M14 receives the second driving signal INL1, the gate of the fifth transistor M15 receives the third driving signal INH2, and the gate of the sixth transistor M16 receives the fourth driving signal INL 2.

Preferably, the third transistor M13 and the fifth transistor M15 are PMOS transistors, and the fourth transistor M14 and the sixth transistor M16 are NMOS transistors.

In this embodiment, the active time of the first driving signal INH1 and the second driving signal INL1 in one period is much shorter than the inactive time thereof, that is, when the first driving signal INH1 or the second driving signal INL1 controls the corresponding transistor to be turned on, the on time of the transistor is very short, for example, in nanoseconds. Meanwhile, the intensity of the first charging current provided by the first current source I11 is greater than the intensity of the second charging current provided by the third current source I13, and the intensity of the first discharging current provided by the second current source I12 is greater than the intensity of the second discharging current provided by the fourth current source I14, so that the charging and discharging of the instantaneous large current of the first capacitor C11 can be realized.

When the second transistor M12 needs to be turned off, the first driving signal INH1 and the third driving signal INH2 respectively control the third transistor M13 and the fifth transistor M15 to be turned off, meanwhile, the second driving signal INL1 drives the fourth transistor M14 to be turned on for a short time (for example, nanosecond time), and then the first capacitor C11 is instantaneously discharged by the first discharging current provided by the second current source I12, so that the second transistor M12 is turned off quickly. The fourth driving signal INL2 then controls the sixth transistor M16 to be constantly turned on, the second discharging current provided by the fourth current source I14 continuously discharges the first capacitor C11 with a small current, so as to prevent the existence of a fine leakage current of the first capacitor C11, and ensure that the gate-source voltage Vgs _ M12 of the second transistor M12 is less than the turn-on threshold voltage Vth _ M12, so that the second transistor M12 is completely turned off. The first transistor M11 is then turned on by the control signal CLKH, and the gate potential of the upper power transistor Mpwr1 is pulled up, so that the gate-source voltage Vgs _ Mpwr1 of the upper power transistor is greater than the turn-on threshold voltage Vth _ Mpwr1, and the upper power transistor Mpwr1 is turned on.

When the second transistor M12 needs to be turned on, the control signal CLKH controls the first transistor M11 to be turned off, and the second drive signal INL1 and the fourth drive signal INL2 respectively control the fourth transistor M14 and the sixth transistor M16 to be turned off, and at the same time the first drive signal INH1 drives the third transistor M13 to be turned on for a short time (for example, a nanosecond time), and the first charging current provided by the first current source I11 instantaneously charges the first capacitor C11, so that the gate-source voltage Vgs _ M12 of the second transistor M12 is greater than the turn-on threshold voltage Vth _ M12, thereby realizing the fast turn-on of the second transistor M12. The third driving signal INH2 then controls the fifth transistor M15 to be turned on constantly, the second charging current provided by the third current source I13 charges the first capacitor C11 continuously with a small current, so as to prevent the first capacitor C11 from having a small leakage current, and ensure that the gate-source voltage Vgs _ M12 of the second transistor M12 is constantly greater than the turn-on threshold voltage Vth _ M12, so that the second transistor M12 is turned on fully. The source and the gate of the upper power tube Mpwr1 are shorted, that is, the gate-source voltage Vgs _ Mpwr1 is constantly equal to 0V and is smaller than the turn-on threshold voltage Vth _ Mpwr1, and the upper power tube Mpwr1 is turned off. The first transistor M11 is controlled to turn off first and then turn on the second transistor M12, so as to prevent the first transistor M11 and the second transistor M12 from being turned on simultaneously. Similarly, when the upper power transistor Mpwr1 needs to be turned on, the second transistor M12 is controlled to be turned off first, and then the first transistor M11 is controlled to be turned on.

Based on the above description, the gate of the second transistor M12 is driven by the first capacitor C11, the first capacitor C11 is charged and discharged rapidly by large pulse current (first charging current and first discharging current) at the moment of turning on and off, and in other constant processes, only a very small current (second charging current and second discharging current) maintains the potential, so that the rapid driving of the power transistor is realized, and the average power loss is small.

The clamping module 201 includes a second diode D12 and a third diode D13. The second diode D12 and the third diode D13 are zener diodes, an anode of the second diode D12 is connected to the gate of the upper power transistor Mpwr1, a cathode of the second diode D12 is connected to the cathode of the third diode D13, and an anode of the third diode D13 is connected to the source of the upper power transistor Mpwr 1.

In the whole process of H-bridge driving, neither the clamping diodes D12 nor D13 need to be in a clamping state, so the violent action of the external output nodes OUT1 and OUT2 has little influence on the common sources VCP and GND inside the chip, and the isolation between the outside and the inside of the chip is realized.

Further, in one embodiment of the present invention, the second driving control module 102 includes a seventh transistor M21 and an eighth transistor M22. The seventh transistor M21 and the eighth transistor M22 are sequentially connected in series between a third power source terminal Vreg (a low voltage source inside the chip, such as a potential signal generated by the low dropout regulator LDO) and the ground terminal GND, a connection node of the seventh transistor M21 and the eighth transistor M22 is connected to the control terminal of the lower power transistor Mpwr3, and a control terminal of the seventh transistor M21 and a control terminal of the eighth transistor M22 are electrically connected to receive the external control signal CLKL. Further, the seventh transistor M21 is a PMOS transistor, and the eighth transistor M22 is an NMOS transistor.

When the upper power transistor Mpwr1 controlled by the first driving control module 101 is turned on, the external control signal CLKL controls the seventh transistor M21 to be turned off, controls the eighth transistor M22 to be turned on, and further controls the lower power transistor Mpwr3 to be turned off. On the contrary, when the upper power transistor Mpwr1 under the control of the first driving control module 101 is turned off, the external control signal CLKL controls the seventh transistor M21 to be turned on, controls the eighth transistor M22 to be turned off, and further controls the lower power transistor Mpwr3 to be turned on.

In another embodiment of the present invention, since the source of the lower power transistor Mpwr3 is grounded and the gate-source voltage thereof is not affected by the potential of the output node OUT1, the second driving control module 102 of the lower power transistor Mpwr3 is a buffer, and the buffer receives the second control signal and controls the lower power transistor Mpwr3 and the upper power transistor Mpwr1 to be not turned on simultaneously according to the second control signal, so the structure is simple.

Fig. 4 is a flow chart illustrating a control method of an H-bridge driver circuit according to an embodiment of the present invention.

In this embodiment, the circuit structure of the H-bridge driver circuit is as shown in fig. 2 and 3, and as shown in fig. 4, the control method of the H-bridge driver circuit includes the following steps:

in step S01, when the upper power transistor is turned on, the gate and the source of the upper power transistor are electrically disconnected, and the gate voltage of the upper power transistor is pulled up.

In step S02, when the upper power transistor is turned off, the gate and the source of the upper power transistor are shorted, and the gate voltage of the upper power transistor is adjusted according to the source voltage of the upper power transistor.

As can be seen from the above description, a transistor (the second transistor M12) is connected between the gate and the source of the upper power transistor Mpwr1, and by controlling the on and off of the transistor, the short circuit and the disconnection of the electrical connection between the gate and the source of the upper power transistor Mpwr1 can be realized. By the method, the grid-source voltage of the upper power tube Mpwr1 can float relative to the voltage of the output node in the off state, and the safety protection of the upper power tube Mpwr1 in the off state can be further realized.

Further, a capacitor (first capacitor C11) is connected between the gate and the source of the transistor, and on/off control of the transistor can be realized by charging/discharging the capacitor, that is, by charging/discharging the gate of the transistor. Referring to fig. 3, when charging and discharging the capacitor, the capacitor is charged/discharged by the first charging current/first discharging current with high current intensity to rapidly turn on or off the transistor, and further rapidly turn on or off the upper power tube Mpwr; and then the capacitor is constantly charged/discharged by the second charging current/the second discharging current with small current intensity so as to realize constant conduction or disconnection of the transistor and further realize constant conduction or disconnection of the upper power tube Mpwr. By the mode, adverse effects of fine leakage of the capacitor on the on or off state of the upper power tube Mpwr can be prevented, the accuracy of H-bridge driving is improved, and the power tube can be driven quickly on the premise of reducing the average power loss of the circuit.

Based on the same inventive concept, the invention also discloses a driving motor, and the driving motor is provided with the H-bridge driving circuit.

In conclusion, in the off state, the gate-source voltage of the power tube floats relative to the voltage of the output node, and the gate-source voltage of the power tube is always constant to 0V no matter how the voltage of the external output node acts, so that the safety protection of the power tube in the off state is realized. The problems such as motor follow current and short circuit VCC are well solved.

In the whole process of H-bridge driving, the clamping diode does not need to be in a clamping state, the influence of voltage or current change of an external output node on an internal common source is reduced, and external and internal isolation is realized.

The grid electrode of a switching tube (M12) between the grid electrode and the source electrode of the power tube is driven by a capacitor, the capacitor is rapidly charged and discharged through nanosecond-level large pulse current at the moment of switching, and in other constant processes, the grid electrode potential of the switching tube is maintained only through a minimum current source, so that the rapid driving of the power tube is realized, and the average power loss of the circuit is reduced.

It should be noted that, in this document, the contained terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.

Finally, it should be noted that: it should be understood that the above examples are only for clearly illustrating the present invention and are not intended to limit the embodiments. Other variations and modifications will be apparent to persons skilled in the art in light of the above description. And are neither required nor exhaustive of all embodiments. And obvious variations or modifications of the invention may be made without departing from the scope of the invention.