阅读说明：本技术 一种三次谐波混频器电路 (Third harmonic mixer circuit ) 是由 孟范忠 方园 林勇 张贞鹏 吴洪江 郑俊平 卢军廷 王子青 王雨桐 陈艳 薛昊东 于 2019-08-23 设计创作，主要内容包括：本发明公开了一种三次谐波混频器电路,其特征在于,包括：本振信号单元、偏压信号单元、混频单元、中频信号单元和射频信号单元；所述偏压信号单元的输入端用于接收偏压信号,所述偏压信号单元的输出端连接所述本振信号单元的第二输入端；所述本振信号单元的第一输入端用于接收本振信号,所述本振信号单元的输出端用于连接混频单元的输入端；所述射频信号单元的输入端用于接收射频信号；所述混频单元的输入输出端和所述射频信号的输出端共接后连接所述中频信号单元的输入端；所述中频信号单元的输出端输出中频信号。本发明能满足在W及以上频段的混频的使用要求。(The invention discloses a third harmonic mixer circuit, which is characterized by comprising: the device comprises a local oscillation signal unit, a bias signal unit, a mixing unit, an intermediate frequency signal unit and a radio frequency signal unit; the input end of the bias signal unit is used for receiving a bias signal, and the output end of the bias signal unit is connected with the second input end of the local oscillator signal unit; the first input end of the local oscillator signal unit is used for receiving a local oscillator signal, and the output end of the local oscillator signal unit is used for connecting the input end of the frequency mixing unit; the input end of the radio frequency signal unit is used for receiving radio frequency signals; the input and output ends of the frequency mixing unit and the output end of the radio frequency signal are connected with the input end of the intermediate frequency signal unit after being connected together; and the output end of the intermediate frequency signal unit outputs an intermediate frequency signal. The invention can meet the use requirement of frequency mixing in W and above frequency bands.)

1. A third harmonic mixer circuit, comprising: the device comprises a local oscillation signal unit, a bias signal unit, a mixing unit, an intermediate frequency signal unit and a radio frequency signal unit;

the input end of the bias signal unit is used for receiving a bias signal, and the output end of the bias signal unit is connected with the second input end of the local oscillator signal unit; the first input end of the local oscillator signal unit is used for receiving a local oscillator signal, and the output end of the local oscillator signal unit is used for connecting the input end of the frequency mixing unit; the input end of the radio frequency signal unit is used for receiving radio frequency signals; the input and output ends of the frequency mixing unit and the output end of the radio frequency signal unit are connected with the input end of the intermediate frequency signal unit after being connected together; the output end of the intermediate frequency signal unit outputs an intermediate frequency signal;

the local oscillator signal unit superposes the received local oscillator signal and the bias signal and inputs the superposed local oscillator signal and the bias signal to the frequency mixing unit; the radio frequency signal unit transmits the radio frequency signal to the frequency mixing unit; the mixing unit processes the superposed local oscillation signal, the superposed bias signal and the received radio frequency signal to generate an intermediate frequency signal, and the intermediate frequency signal is transmitted to the intermediate frequency signal unit.

2. The third harmonic mixer circuit according to claim 1, wherein the local oscillator signal unit includes a first microstrip line, a capacitor C1, a second microstrip line, a third microstrip line, a fourth microstrip line, and a resistor R1;

the input end of the first microstrip line is the first input end of the local oscillation signal unit, the output end of the first microstrip line is connected with the first end of the capacitor C1, the second end of the capacitor C2 is connected with the input end of the second microstrip line in a common way to form the second input end of the local oscillation signal unit, the output end of the second microstrip line is connected with the input end of the third microstrip line and the input end of the fourth microstrip line respectively, the output end of the third microstrip line is connected with the first end of the resistor R1 in a common way to form the first output end of the local oscillation signal unit, and the output end of the fourth microstrip line is connected with the second end of the resistor R1 in a common way to form the second output end of the local oscillation signal unit.

3. The third harmonic mixer circuit of claim 1 wherein the bias signal unit comprises a resistor R2, a capacitor C2, and an inductor;

the first end of the resistor R2 is the input end of the bias signal unit, the second end of the resistor R2 is respectively connected to the first end of the capacitor C2 and the first end of the inductor, the second end of the capacitor C2 is grounded, and the second end of the inductor is the output end of the bias signal unit.

4. A third harmonic mixer circuit according to claim 1, wherein the mixing unit comprises a first transistor sub-unit, a second transistor sub-unit and a quasi-balanced power division network sub-unit;

the input end of the first transistor unit is the first input end of the frequency mixing unit, the input end of the first transistor unit is connected with the first input end and the first output end of the quasi-balanced power distribution network subunit, the input end of the second transistor subunit is the second input end of the frequency mixing unit, the input end and the output end of the second transistor subunit are connected with the second input end and the second output end of the quasi-balanced power distribution network subunit, and the third input end and the third output end of the quasi-balanced power distribution network subunit are the input end and the output end of the frequency mixing unit.

5. The third harmonic mixer circuit according to claim 4 wherein the first transistor cell comprises a fifth microstrip and a first switch transistor;

the input end of the fifth microstrip line is the input end of the first transistor unit, the output end of the fifth microstrip line is connected with the controlled end of the first switch tube, the high potential end of the first switch tube is the input end and the output end of the first transistor unit, and the low potential end of the first switch tube is grounded;

the second transistor subunit comprises a sixth microstrip line and a second switch tube;

the input end of the sixth microstrip line is the input end of the second transistor subunit, the output end of the sixth microstrip line is connected with the controlled end of the second switch tube, the high-potential end of the second switch tube is the input end and the output end of the second transistor subunit, and the low-potential end of the second switch tube is grounded.

6. A third harmonic mixer circuit according to claim 5 wherein said first switch transistor comprises a first field effect transistor, the gate of said first field effect transistor being the controlled terminal of said first switch transistor, the drain of said first field effect transistor being the high potential terminal of said first switch transistor, the source of said first field effect transistor being the low potential terminal of said first switch transistor;

the second switch tube comprises a second field effect transistor, the grid electrode of the second field effect transistor is the controlled end of the second switch tube, the drain electrode of the second field effect transistor is the high potential end of the second switch tube, and the source electrode of the second field effect transistor is the low potential end of the second switch tube.

7. The third harmonic mixer circuit of claim 4 in which the quasi-balanced power division network sub-unit comprises a seventh microstrip line, an eighth microstrip line, a ninth microstrip line, a tenth microstrip line and an eleventh microstrip line;

the first end of the seventh microstrip line is a first input/output end of the quasi-balanced power division network subunit, the second end of the seventh microstrip line is connected with the first end of the eighth microstrip line, the second end of the eighth microstrip line is respectively connected with the second end of the ninth microstrip line and the first end of the eleventh microstrip line, the first end of the ninth microstrip line is connected with the second end of the tenth microstrip line, the first end of the tenth microstrip line is a second input/output end of the quasi-balanced power division network subunit, and the second end of the eleventh microstrip line is a third input/output end of the quasi-balanced power division network subunit.

8. A third harmonic mixer circuit according to claim 1, characterized in that the intermediate frequency signal unit comprises a twelfth microstrip line, a thirteenth microstrip line and a capacitance C3;

the input end of the twelfth microstrip line is the input end of the intermediate frequency signal unit, the output end of the twelfth microstrip line is respectively connected with the first end of the capacitor C3 and the input end of the thirteenth microstrip line, the second end of the capacitor C3 is grounded, and the output end of the thirteenth microstrip line is the output end of the intermediate frequency signal unit.

9. The third harmonic mixer circuit of claim 1 wherein the radio frequency signal unit comprises a fourteenth microstrip, a fifteenth microstrip, a sixteenth microstrip and a seventeenth microstrip;

the input end of the seventeenth microstrip line is the input end of the radio frequency signal unit, the output end of the seventeenth microstrip line is connected with the input end of the sixteenth microstrip line, the output end of the sixteenth microstrip line is connected with the input end of the fifteenth microstrip line, the output end of the fifteenth microstrip line is connected with the input end of the fourteenth microstrip line, and the output end of the fourteenth microstrip line is the output end of the radio frequency signal unit.

10. The third harmonic mixer circuit of claim 9 wherein the fifteenth microstrip is an edge-coupled microstrip structure and the sixteenth microstrip is an edge-coupled microstrip structure.

Technical Field

The invention relates to the technical field of microwaves, in particular to a third harmonic mixer circuit.

Background

In a wireless transceiving system, a higher carrier frequency is adopted, which is the primary way to realize high-speed communication. As one of the key components of the transceiver, the performance of the high frequency mixer becomes a determining factor for the performance of the transceiver system. Diode-based mixers in the W and above bands, diode mixers have their inherent drawbacks: firstly, the conduction of the diode is driven by a local oscillator signal, and the smaller the conversion loss required by the mixer is, the larger the required diode size is; second, the diode structure is not convenient for monolithic integration.

At present, the structure of the frequency mixer with the diode structure is complex in the frequency band of W and above, and the use requirement cannot be met.

Disclosure of Invention

The embodiment of the invention provides a third harmonic mixer circuit, aiming at solving the problem that the existing mixer cannot meet the use requirement in the frequency band of W and above.

An embodiment of the present invention provides a third harmonic mixer circuit, including:

the device comprises a local oscillation signal unit, a bias signal unit, a mixing unit, an intermediate frequency signal unit and a radio frequency signal unit;

the input end of the bias signal unit is used for receiving a bias signal, and the output end of the bias signal unit is connected with the second input end of the local oscillator signal unit; the first input end of the local oscillator signal unit is used for receiving a local oscillator signal, and the output end of the local oscillator signal unit is used for connecting the input end of the frequency mixing unit; the input end of the radio frequency signal unit is used for receiving radio frequency signals; the input and output ends of the frequency mixing unit and the output end of the radio frequency signal unit are connected with the input end of the intermediate frequency signal unit after being connected together; the output end of the intermediate frequency signal unit outputs an intermediate frequency signal;

the local oscillator signal unit superposes the received local oscillator signal and the bias signal and inputs the superposed local oscillator signal and the bias signal to the frequency mixing unit; the radio frequency signal unit transmits the radio frequency signal to the frequency mixing unit; the mixing unit processes the superposed local oscillation signal, the superposed bias signal and the received radio frequency signal to generate an intermediate frequency signal, and the intermediate frequency signal is transmitted to the intermediate frequency signal unit.

In an embodiment of the present application, the local oscillator signal unit includes a first microstrip line, a capacitor C1, a second microstrip line, a third microstrip line, a fourth microstrip line, and a resistor R1;

the input end of the first microstrip line is the first input end of the local oscillation signal unit, the output end of the first microstrip line is connected with the first end of the capacitor C1, the second end of the capacitor C2 is connected with the input end of the second microstrip line in a common way to form the second input end of the local oscillation signal unit, the output end of the second microstrip line is connected with the input end of the third microstrip line and the input end of the fourth microstrip line respectively, the output end of the third microstrip line is connected with the first end of the resistor R1 in a common way to form the first output end of the local oscillation signal unit, and the output end of the fourth microstrip line is connected with the second end of the resistor R1 in a common way to form the second output end of the local oscillation signal unit.

In an embodiment of the present application, the bias signal unit includes a resistor R2, a capacitor C2, and an inductor;

the first end of the resistor R2 is the input end of the bias signal unit, the second end of the resistor R2 is respectively connected to the first end of the capacitor C2 and the first end of the inductor, the second end of the capacitor C2 is grounded, and the second end of the inductor is the output end of the bias signal unit.

In an embodiment of the present application, the mixing unit includes a first transistor unit, a second transistor subunit, and a quasi-balanced power division network subunit;

the input end of the first transistor unit is the first input end of the frequency mixing unit, the input end of the first transistor unit is connected with the first input end and the first output end of the quasi-balanced power distribution network subunit, the input end of the second transistor subunit is the second input end of the frequency mixing unit, the input end and the output end of the second transistor subunit are connected with the second input end and the second output end of the quasi-balanced power distribution network subunit, and the third input end and the third output end of the quasi-balanced power distribution network subunit are the input end and the output end of the frequency mixing unit.

In an embodiment of the present application, the first transistor tube unit includes a fifth microstrip line and a first switch tube;

the input end of the fifth microstrip line is the input end of the first transistor unit, the output end of the fifth microstrip line is connected with the controlled end of the first switch tube, the high potential end of the first switch tube is the input end and the output end of the first transistor unit, and the low potential end of the first switch tube is grounded;

the second transistor subunit comprises a sixth microstrip line and a second switch tube;

the input end of the sixth microstrip line is the input end of the second transistor subunit, the output end of the sixth microstrip line is connected with the controlled end of the second switch tube, the high-potential end of the second switch tube is the input end and the output end of the second transistor subunit, and the low-potential end of the second switch tube is grounded.

In an embodiment of the present application, the first switch tube includes a first field effect transistor, a gate of the first field effect transistor is a controlled terminal of the first switch tube, a drain of the first field effect transistor is a high potential terminal of the first switch tube, and a source of the first field effect transistor is a low potential terminal of the first switch tube;

the second switch tube comprises a second field effect transistor, the grid electrode of the second field effect transistor is the controlled end of the second switch tube, the drain electrode of the second field effect transistor is the high potential end of the second switch tube, and the source electrode of the second field effect transistor is the low potential end of the second switch tube.

In an embodiment of the present application, the quasi-balanced power division network sub-unit includes a seventh microstrip line, an eighth microstrip line, a ninth microstrip line, a tenth microstrip line, and an eleventh microstrip line;

the first end of the seventh microstrip line is a first input/output end of the quasi-balanced power division network subunit, the second end of the seventh microstrip line is connected with the first end of the eighth microstrip line, the second end of the eighth microstrip line is respectively connected with the second end of the ninth microstrip line and the first end of the eleventh microstrip line, the first end of the ninth microstrip line is connected with the second end of the tenth microstrip line, the first end of the tenth microstrip line is a second input/output end of the quasi-balanced power division network subunit, and the second end of the eleventh microstrip line is a third input/output end of the quasi-balanced power division network subunit.

In an embodiment of the present application, the intermediate frequency signal unit includes a twelfth microstrip line, a thirteenth microstrip line, and a capacitor C3;

the input end of the twelfth microstrip line is the input end of the intermediate frequency signal unit, the output end of the twelfth microstrip line is respectively connected with the first end of the capacitor C3 and the input end of the thirteenth microstrip line, the second end of the capacitor C3 is grounded, and the output end of the thirteenth microstrip line is the output end of the intermediate frequency signal unit.

In an embodiment of the present application, the radio frequency signal unit includes a fourteenth microstrip line, a fifteenth microstrip line, a sixteenth microstrip line, and a seventeenth microstrip line;

the input end of the seventeenth microstrip line is the input end of the radio frequency signal unit, the output end of the seventeenth microstrip line is connected with the input end of the sixteenth microstrip line, the output end of the sixteenth microstrip line is connected with the input end of the fifteenth microstrip line, the output end of the fifteenth microstrip line is connected with the input end of the fourteenth microstrip line, and the output end of the fourteenth microstrip line is the output end of the radio frequency signal unit.

In an embodiment of the present application, the fifteenth microstrip line is an edge-coupled microstrip structure, and the sixteenth microstrip line is an edge-coupled microstrip structure.

The invention inputs the received local oscillation signal and the bias signal to the frequency mixing unit after overlapping by arranging the local oscillation signal unit; the radio frequency signal unit transmits a radio frequency signal to the frequency mixing unit; the mixing unit processes the superposed local oscillation signal, bias signal and received radio frequency signal to generate intermediate frequency signal, which can meet the use requirement of mixing frequency in W and above frequency band.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other drawings can be obtained according to these drawings without inventive labor.

Fig. 1 is a schematic diagram of a third harmonic mixer circuit according to an embodiment of the present invention;

fig. 2 is a circuit connection diagram of a third harmonic mixer circuit according to an embodiment of the present invention.

Detailed Description

In order to make the technical solution better understood by those skilled in the art, the technical solution in the embodiment of the present invention will be clearly described below with reference to the drawings in the embodiment of the present invention, and it is obvious that the described embodiment is a part of the embodiment of the present invention, and not a whole embodiment. All other embodiments obtained by a person of ordinary skill in the art based on the embodiments in the present disclosure without any creative effort shall fall within the protection scope of the present disclosure.

The terms "include" and any other variations in the description and claims of this document and the above-described figures, mean "including but not limited to", and are intended to cover non-exclusive inclusions. Furthermore, the terms "first" and "second," etc. are used to distinguish between different objects and are not used to describe a particular order.

Implementations of the present invention are described in detail below with reference to the following detailed drawings:

fig. 1-2 illustrate a third harmonic mixer circuit according to an embodiment of the present invention, and for convenience of illustration, only the parts related to the embodiment of the present invention are shown, and detailed as follows:

as shown in fig. 1, a third harmonic mixer circuit according to an embodiment of the present invention includes a local oscillator signal unit 120, a bias signal unit 110, a mixing unit 130, an intermediate frequency signal unit 140, and a radio frequency signal unit 150;

the input end of the bias signal unit 110 is configured to receive a bias signal, and the output end of the bias signal unit 110 is connected to the second input end of the local oscillator signal unit 120; a first input end of the local oscillator signal unit 120 is configured to receive a local oscillator signal, and an output end of the local oscillator signal unit 120 is configured to be connected to an input end of the frequency mixing unit 130; the input end of the rf signal unit 150 is configured to receive an rf signal; the input and output ends of the frequency mixing unit 130 and the output end of the radio frequency signal unit are connected to the input end of the intermediate frequency signal unit 140 after being connected together; the output end of the intermediate frequency signal unit 140 outputs an intermediate frequency signal;

the local oscillator signal unit 120 superimposes the received local oscillator signal and the bias signal and inputs the superimposed local oscillator signal and the superimposed bias signal to the frequency mixing unit 130; the rf signal unit 150 transmits the rf signal to the frequency mixing unit 130; the mixing unit 130 processes the superimposed local oscillation signal, the bias signal, and the received radio frequency signal to generate the intermediate frequency signal, and transmits the intermediate frequency signal to the intermediate frequency signal unit 140.

In this embodiment, in the design of the present invention, in order to implement high-efficiency frequency mixing for third harmonic, the matching design at the local oscillator port focuses on low reflection and low-loss transmission of the local oscillator signal, so as to reduce the local oscillator power required by frequency mixing; and the drain port matches the optimal impedance to the third harmonic of the local oscillator and the frequency band where the radio frequency is located, so that optimal frequency mixing is realized. The selection of the intermediate frequency signal extraction port gives consideration to intermediate frequency bandwidth and intermediate frequency loss.

Matching structure designs can be generally divided into lumped element matching and discrete element matching. However, the parasitic effect of the lumped component is quite serious in the W band, so that the radio frequency port of the invention adopts a discrete matching mode, the local oscillator port adopts a matching mode combining discrete matching and lumped matching, and the intermediate frequency port mainly adopts a lumped matching mode.

In this embodiment, the input local oscillator signal "power division" is input to the gates of two identical field effect transistors, the radio frequency signal is also input to the drains of the field effect transistors in the same manner, and the field effect transistors are used as nonlinear devices to implement frequency mixing. The quasi-balanced circuit structure is more beneficial to impedance conversion between the radio frequency and local oscillator ports and the drain electrode and the grid electrode of the field effect transistor on the one hand, and on the other hand, the balance resistance between two branches of the grid electrode absorbs echo signals to a certain extent, so that the circuit structure is more balanced. The drain port is designed with a duplex filter circuit for separating the intermediate frequency signal and the radio frequency signal. In addition, in the circuit, the grid bias voltage Vg biases the device in a quasi-pinch-off region, drain voltage is not applied, and current is hardly consumed.

As shown in fig. 2, in the embodiment of the present invention, the local oscillator signal unit 120 includes a first microstrip line M1, a capacitor C1, a second microstrip line M2, a third microstrip line M3, a fourth microstrip line M4, and a resistor R1;

the input end of the first microstrip line M1 is the first input end of the local oscillator signal unit 120, the output end of the first microstrip line M1 is connected to the first end of the capacitor C1, the second end of the capacitor C2 is connected to the input end of the second microstrip line M2 in common to form the second input end of the local oscillator signal unit 120, the output end of the second microstrip line M2 is connected to the input ends of the third microstrip subunit M3 and the fourth microstrip line M4, the output end of the third microstrip line M3 is connected to the first end of the resistor R1 in common to form the first output end of the local oscillator signal unit 120, and the output end of the fourth microstrip line M4 is connected to the second end of the resistor R1 in common to form the second output end of the local oscillator signal unit 120.

In this embodiment, the output terminal of the local oscillator signal unit 120 includes a first output terminal and a second output terminal.

In the present embodiment, the first microstrip line M1, the second microstrip line M2, the third microstrip line M3, and the fourth microstrip line M4 may be microstrip line structures, and are not limited to one microstrip line, and may be structures formed by connecting a plurality of microstrip lines in series or in parallel.

In the present embodiment, the first microstrip line M1 implements port matching with the local oscillation signal input port. The capacitor C1 is a dc blocking capacitor. The second microstrip line M2, the third microstrip line M3, and the fourth microstrip line M4 form a power division network of the local oscillation signal unit 120. Resistor R1 is a balanced resistor.

As shown in fig. 2, in the embodiment of the present invention, the bias signal unit 110 includes a resistor R2, a capacitor C2, and an inductor L1;

a first end of the resistor R2 is an input end of the bias signal unit 110, a second end of the resistor R2 is respectively connected to a first end of the capacitor C2 and a first end of the inductor L1, a second end of the capacitor C2 is grounded, and a second end of the inductor L1 is an output end of the bias signal unit 110.

In the embodiment, the circuit formed by the resistor R2, the capacitor C2 and the inductor L1 is used for inputting the gate supply voltage into the rf signal port, and good rf-dc isolation can be achieved.

In the present embodiment, the inductor L1 and the capacitor C2 form a dc filter circuit, the inductor L1 may be replaced by a λ/4 wavelength microstrip line, and the resistor R2 is a gate supply voltage upper limit resistor.

As shown in fig. 2, in the embodiment of the present invention, the mixing unit 130 includes a first transistor unit 131, a second transistor subunit 132, and a quasi-balanced power division network subunit 133;

an input end of the first transistor unit 131 is a first input end of the frequency mixing unit 130, an input end and an output end of the first transistor unit 131 are connected to a first input end and a first output end of the quasi-balanced power division network subunit 133, an input end of the second transistor subunit 132 is a second input end of the frequency mixing unit 130, an input end and an output end of the second transistor subunit 132 are connected to a second input end and a second output end of the quasi-balanced power division network subunit 133, and a third input end and a third output end of the quasi-balanced power division network subunit 133 are input ends and output ends of the frequency mixing unit 130.

As shown in fig. 2, in the embodiment of the present invention, the first transistor tube unit 131 includes a fifth microstrip line M5 and a first switch tube;

the input end of the fifth microstrip line M5 is the input end of the first transistor unit 131, the output end of the fifth microstrip line M5 is connected to the controlled end of the first switch tube, the high potential end of the first switch tube is the input end and the output end of the first transistor unit, and the low potential end of the first switch tube is grounded;

the second transistor subunit 132 includes a sixth microstrip line M6 and a second switch tube;

the input end of the sixth microstrip line M6 is the input end of the second transistor subunit, the output end of the sixth microstrip line M6 is connected to the controlled end of the second switch tube, the high potential end of the second switch tube is the input and output end of the second transistor subunit, and the low potential end of the second switch tube is grounded.

In this embodiment, both the fifth microstrip line M5 and the sixth microstrip line M6 may be microstrip line structures, and are not limited to one microstrip line, and may be structures formed by connecting a plurality of microstrip lines in series or in parallel.

The fifth microstrip line M5 and the sixth microstrip line M6 complete impedance matching between the gate of the field effect transistor and the power dividing network.

As shown in fig. 2, in the embodiment of the present invention, the first switch transistor includes a first FET1, a gate of the first FET1 is a controlled terminal of the first switch transistor, a drain of the first FET1 is a high potential terminal of the first switch transistor, and a source of the first FET1 is a low potential terminal of the first switch transistor;

the second switch tube comprises a second FET2, the gate of the second FET2 is the controlled terminal of the second switch tube, the drain of the second FET2 is the high potential terminal of the second switch tube, and the source of the second FET2 is the low potential terminal of the second switch tube.

In this embodiment, the field effect transistor is used as a nonlinear element instead of a diode, and monolithic integration with an active circuit such as an amplifier, an oscillator, and a switch can be achieved, so that the whole rf front-end circuit can be miniaturized.

As shown in fig. 2, in the embodiment of the present invention, the quasi-balanced power dividing network unit 133 includes a seventh microstrip line M7, an eighth microstrip line M8, a ninth microstrip line M9, a tenth microstrip line M10, and an eleventh microstrip line M11;

a first end of the seventh microstrip line M7 is a first input/output end of the quasi-balanced power division network subunit 133, a second end of the seventh microstrip line M7 is connected to a first end of the eighth microstrip line M8, a second end of the eighth microstrip line M8 is connected to a second end of the ninth microstrip line M9 and a first end of the eleventh microstrip line M11, respectively, a first end of the ninth microstrip line M9 is connected to a second end of the tenth microstrip line M10, a first end of the tenth microstrip line M10 is a second input/output end of the quasi-balanced power division network subunit 133, and a second end of the eleventh microstrip line M11 is a third input/output end of the quasi-balanced power division network subunit 133.

In the present embodiment, the seventh microstrip line M7, the eighth microstrip line M8, the ninth microstrip line M9, and the tenth microstrip line M10 may all be microstrip line structures. The seventh microstrip line M7, the eighth microstrip line M8, the ninth microstrip line M9, and the tenth microstrip line M10 form a quasi-balanced power division network of the drain of the field effect transistor.

In the present embodiment, the first and second ends of the 5 microstrip lines, i.e., the seventh microstrip line M7, the eighth microstrip line M8, the ninth microstrip line M9, the tenth microstrip line M10 and the eleventh microstrip line M11, are input/output ports.

In this embodiment, the eleventh microstrip line M11 may be a microstrip line structure, and the eleventh microstrip line M11 implements impedance matching between the if signal unit 140 and the rf signal unit 150 and the drain quasi-balanced power splitting network.

As shown in fig. 2, in the embodiment of the present invention, the intermediate frequency signal unit 140 includes a twelfth microstrip line M12, a thirteenth microstrip line M13 and a capacitor C3;

an input end of the twelfth microstrip line M12 is an input end of the intermediate-frequency signal unit 140, an output end of the twelfth microstrip line M12 is respectively connected to the first end of the capacitor C3 and the input end of the thirteenth microstrip line M13, a second end of the capacitor C3 is grounded, and an output end of the thirteenth microstrip line M13 is an output end of the intermediate-frequency signal unit 140.

In the present embodiment, both the twelfth microstrip line M12 and the thirteenth microstrip line M13 may be microstrip line structures. The twelfth microstrip line M12 and the capacitor C3 form an LC low-pass filter network, so that the radio frequency signal is suppressed while the extraction of the intermediate frequency signal is realized. The thirteenth microstrip line M13 realizes impedance matching of the output port of the intermediate frequency signal unit 140.

In this embodiment, the capacitor C3 can be changed to an open stub, so as to obtain a wider intermediate frequency bandwidth, but relatively cause a higher intermediate frequency loss

As shown in fig. 2, in the embodiment of the present invention, the radio frequency signal unit 150 includes a fourteenth microstrip line M14, a fifteenth microstrip line M15, a sixteenth microstrip line M16 and a seventeenth microstrip line M17;

the input end of the seventeenth microstrip line M17 is the input end of the radio frequency signal unit 150, the output end of the seventeenth microstrip line M17 is connected to the input end of the sixteenth microstrip line M16, the output end of the sixteenth microstrip line M16 is connected to the input end of the fifteenth microstrip line M15, the output end of the fifteenth microstrip line M15 is connected to the input end of the fourteenth microstrip line M14, and the output end of the fourteenth microstrip line M14 is the output end of the radio frequency signal unit 150.

In the present embodiment, the seventeenth microstrip line M17 implements impedance matching of the input port of the radio frequency signal unit 150.

As shown in fig. 2, in the embodiment of the present invention, the intermediate frequency signal unit 140 and the radio frequency signal unit 150 jointly form an intermediate frequency and radio frequency double-tap network, which realizes the separation of the radio frequency and the intermediate frequency signals and the impedance matching of the respective ports.

As shown in fig. 2, in the embodiment of the present invention, the fifteenth microstrip line M15 is an edge-coupled microstrip structure, and the sixteenth microstrip line M16 is an edge-coupled microstrip structure.

In this embodiment, the fifteenth microstrip line M15 and the sixteenth microstrip line M16 both adopt edge-coupled microstrip structures, so as to implement band-pass filtering at the rf port, on one hand, radio frequency can be passed through and intermediate frequency can be suppressed, and on the other hand, ac and dc can be passed through the rf port.

When the high-power local oscillation signal VLO is superposed on the grid voltage, the drain-source conductance gds of the field effect transistor is modulated by the local oscillation signal and contains local oscillation frequency and each subharmonic component thereof; when a small rf signal VRF is input to the drain of the fet, the ac current output from the drain may be represented as ids ═ VRF × gds, and the rf frequency is directly multiplied by the lo fundamental frequency and each subharmonic frequency, thereby achieving mixing.

The above-mentioned embodiments are only used for illustrating the technical solutions of the present invention, and not for limiting the same; although the present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and such modifications or substitutions do not depart from the spirit and scope of the corresponding technical solutions of the embodiments of the present invention.