阅读说明：本技术 用于容错以太网时间同步的方法和设备 (Method and apparatus for fault tolerant ethernet time synchronization ) 是由 S.萨米 P.韦努戈帕尔 于 2021-03-30 设计创作，主要内容包括：本申请总体涉及在存在链路故障时的网络定时同步,包括设备和方法。在各个实施例中,一种方法包括：生成时间同步信号；将时间同步信号通过第一链路从第一交换机传输到第二交换机并且通过第二链路从第一交换机传输到第三交换机；检测第一链路的链路故障；以及响应于链路故障,通过第三链路将时间同步信号从第二交换机传输到第三交换机。(The present application relates generally to network timing synchronization in the presence of link failures, including devices and methods. In various embodiments, a method comprises: generating a time synchronization signal; transmitting a time synchronization signal from the first switch to the second switch over the first link and from the first switch to the third switch over the second link; detecting a link failure of a first link; and transmitting the time synchronization signal from the second switch to the third switch over the third link in response to the link failure.)

1. A method for providing fault tolerant network time synchronization in a motor vehicle communication network, comprising:

-generating a time synchronization signal;

-transmitting a time synchronization signal from the first switch to the second switch over the first link and from the first switch to the third switch over the second link;

-detecting a link failure of the second link; and

-transmitting a time synchronization signal from the second switch to the third switch over the third link in response to the link failure.

2. The method of claim 1, wherein the link failure is detected in response to a third switch not receiving a time synchronization signal over a second link.

3. The method of claim 2, wherein the link failure is detected in response to the third switch not receiving a time synchronization signal over the second link for a plurality of time synchronization intervals.

4. The method of claim 1, wherein the second switch is operable to enable a primary port in response to the link failure.

5. The method of claim 1, wherein the third switch is operable to couple a time synchronization signal from the second switch to an edge node, and wherein the edge node is operable to synchronize clocks in response to the time synchronization signal.

6. The method of claim 1, wherein the time synchronization signal is generated by an edge node designated as a grandparent.

7. The method of claim 1, wherein the time synchronization signal is generated by a radar controller coupled to the first switch, and wherein a first radar sensor is coupled to the second switch and a second radar sensor is coupled to the third switch.

8. The method of claim 1, further operable to generate subsequent frames with timestamps for determining latency between the first switch and a second switch.

9. The method of claim 1, further comprising a fourth switch operable to receive a time synchronization signal from the third switch.

10. An apparatus, comprising:

-a first network node comprising a first switch for transmitting a first time synchronization signal;

-a second network node comprising a second switch for receiving the first time synchronization signal from the first switch and transmitting the second time synchronization signal to a third switch; and

-a third network node comprising a third switch for receiving the first time synchronization signal from the first switch and the second time synchronization signal from the second switch, the third node further operative to synchronize the internal clock to the first synchronization signal in response to receiving the first time synchronization signal and to synchronize the internal clock to the second synchronization signal in response to not receiving the first time synchronization signal.

Technical Field

The subject matter of the present disclosure relates generally to data distribution in motor vehicles, and more particularly, to methods and apparatus for providing fault tolerant ethernet timing in a multi-time domain system in the presence of one or more hardware link failures.

Background

Modern vehicles include many systems and subsystems for vehicle control, vehicle system monitoring, and passenger comfort. As vehicle subsystems increase in complexity, such as the deployment and performance of Advanced Driver Assistance Systems (ADAS), the need for reliable inter-subsystem communication and monitoring will also increase. Communication between vehicle subsystems has been used to allow sensor data to be shared between vehicle subsystems, thereby reducing the occurrence of redundant duplicate sensors. Such communication between vehicle subsystems is traditionally handled by a Controller Area Network (CAN) bus. Problems can arise because many vehicle subsystems have controllers and other components that generate and employ their own timing structures and time domains, making communication between the vehicle subsystems problematic. The CAN bus requires excessive clock and bit synchronization, which greatly limits the data rate of the CAN bus in advanced applications.

To address the data rate limitations of the Can bus, ethernet is deployed as a vehicle communication system as vehicle control systems expand to higher levels of autonomous driving, thereby increasing the need for fault tolerant time synchronization methods over ethernet. IEEE has defined a standard (802.1AS) for multiple time domains over ethernet, but does not define a protocol that enables fault tolerance in the presence of link or hardware failures. It is desirable to provide a configuration with multiple time domains and algorithms to preserve a common time base without any time jumps when there are one or more hardware or link failures. It is desirable to address these problems and overcome the associated limitations in order to address the timing issues presented by the ethernet protocol in a vehicular environment while overcoming the above-mentioned problems.

Disclosure of Invention

Object detection methods and systems and associated control logic for providing vehicle sensing and control systems, methods of manufacturing and operating such systems, and motor vehicles equipped with on-board sensors and control systems are disclosed herein. By way of example, and not limitation, various embodiments of the network timing configuration techniques disclosed herein are presented.

In one embodiment, a method for providing fault tolerant network time synchronization in a motor vehicle communication network includes: generating a time synchronization signal; transmitting a time synchronization signal from the first switch to the second switch over the first link and from the first switch to the third switch over the second link; detecting a link failure of a first link; and transmitting the time synchronization signal from the second switch to the third switch over the third link in response to the link failure.

According to various embodiments, a link failure is detected in response to the third switch not receiving the time synchronization signal over the second link.

According to various embodiments, a link failure is detected in response to the third switch not receiving a time synchronization signal over the second link for a plurality of time synchronization intervals.

According to various embodiments, the second switch is operable to enable the primary port in response to a link failure.

According to various embodiments, the third switch is operable to couple the time synchronisation signal from the second switch to the edge node and wherein the edge node is operable to synchronise the clock in response to the time synchronisation signal.

According to various embodiments, the time synchronization signal is generated by an edge node designated as a grandparent (grandmaster).

According to various embodiments, the time synchronization signal is generated by a radar controller coupled to the first switch, and wherein the first radar sensor is coupled to the second switch and the second radar sensor is coupled to the third switch.

According to various embodiments, the method may be operable to generate subsequent frames with timestamps for determining the latency between the first switch and the second switch.

According to various embodiments, the fourth switch is operable to receive the time synchronization signal from the third switch.

According to another embodiment, an apparatus comprises: a first network node comprising a first switch for transmitting a first time synchronization signal; a second network node comprising a second switch to receive the first time synchronization signal from the first switch and to transmit a second time synchronization signal to a third switch; and a third network node comprising a third switch for receiving the first time synchronisation signal from the first switch and the second time synchronisation signal from the second switch, the third node further being operative to synchronise the internal clock to the first synchronisation signal in response to receiving the first time synchronisation signal and to synchronise the internal clock to the second synchronisation signal in response to not receiving the first time synchronisation signal.

According to various embodiments, the internal clock is synchronized to the second time synchronization signal in response to detection of a link failure between the first switch and the third switch.

According to various embodiments, the internal clock is synchronized to the second time synchronization signal in response to detection of a link failure between the first switch and the third switch, and wherein the link failure is determined in response to the third switch not receiving the first time synchronization signal for a plurality of time synchronization intervals.

According to various embodiments, the first network node is designated as a grandparent.

According to various embodiments, the third switch is operable to redefine the port role from the slave port to the master port in response to the link failure.

According to various embodiments including a fourth switch, the third switch is operable to transmit the second time synchronization signal to the fourth switch in response to a link failure.

According to various embodiments, the first network node is a lidar controller and the third network node is a lidar sensor.

According to various embodiments, the second network node is operable to enable the primary port in response to a link failure.

According to various embodiments, the first node is operable to generate a subsequent frame indicating the first latency, and in response to the first latency and the second latency, the second node is operable to update the subsequent node.

According to another embodiment, a vehicle network comprises: a vehicle controller having a first network switch and a grandparent clock, wherein the vehicle controller is operable to generate a first time synchronization frame in response to the grandparent clock and to couple a first time synchronization from the first network switch to a second network switch via a first data link and to couple the first time synchronization from the first network switch to a third network switch via a second data link; a first vehicle sensor having a second network switch configured for receiving the first time sync frame via the first data link, for generating a second time sync frame in response to the first time sync frame and for transmitting the second time sync frame to a third network switch via a third data link; and a second vehicle sensor having a third network switch and an internal clock, wherein the second vehicle sensor is operable to synchronize the internal clock with the grandparent clock according to the first time synchronization signal in response to receiving the first time synchronization frame, the second vehicle sensor is further operable to synchronize the internal clock with the master clock according to the second time synchronization signal in response to not receiving the first time synchronization frame.

According to various embodiments, the second vehicle sensor is operable to synchronize the internal clock with the grandparent clock according to the second time synchronization signal in response to not receiving the first time synchronization frame within the plurality of time synchronization intervals.

The above advantages and other advantages and features of the present disclosure will become apparent from the following detailed description of the preferred embodiments when taken in conjunction with the accompanying drawings.

Drawings

Exemplary embodiments will hereinafter be described in conjunction with the following drawing figures, wherein like numerals denote like elements, and wherein:

FIG. 1 illustrates an exemplary application of the method and apparatus for fault tolerant Ethernet time synchronization in a motor vehicle according to an embodiment of the present disclosure;

FIG. 2 shows a block diagram illustrating an exemplary system for fault tolerant Ethernet time synchronization in a motor vehicle, in accordance with an embodiment of the present disclosure;

FIG. 3 sets forth a flow chart illustrating an exemplary method for fault tolerant Ethernet time synchronization according to embodiments of the present disclosure;

FIG. 4 sets forth a block diagram illustrating another exemplary system for fault tolerant Ethernet time synchronization in a motor vehicle according to embodiments of the present disclosure; and

fig. 5 sets forth a flow chart illustrating a further exemplary method for fault tolerant ethernet time synchronization according to embodiments of the present disclosure.

The exemplifications set out herein illustrate preferred embodiments of the invention, and such exemplifications are not to be construed as limiting the scope of the invention in any manner.

Detailed Description

The following detailed description is merely exemplary in nature and is not intended to limit the disclosure or the application and uses thereof. Furthermore, there is no intention to be bound by any theory presented in the preceding description or the following detailed description. For example, communication networks and communication network protocols have particular application for use on vehicles. However, as will be understood by those skilled in the art, the network configurations and methods described herein may have other applications in systems outside of a vehicle.

Turning now to fig. 1, a diagram of a system 100 representing an exemplary application of the method and apparatus for fault tolerant ethernet time synchronization in a motor vehicle 105 is shown, in accordance with an embodiment of the present disclosure. Exemplary system 100 includes a video controller 115 coupled to first camera 110 and second camera 175, a lidar controller 125 coupled to first lidar transceiver 130 and second lidar transceiver 120, a radar controller 145 coupled to first radar transceiver 140 and second radar 150, a processor 160, a user interface 165, a vehicle controller 155, and a trailer interface 170.

In the exemplary embodiment, lidar controller 125, video controller 115, and radar controller 145 are each operable to receive and process data from their respective sensors. The video controller 115 is operable to receive images from the first camera 110 and the second camera 175 to process the images to generate image data for generating a map of objects surrounding the vehicle 105. Lidar controller 125 is operable to receive direction and range data from each of first lidar transceiver 130 and second lidar transceiver 120. Similarly, the radar controller 145 is operable to receive direction and range data from each of the first radar transceiver 140 and the second radar 150. The image data, lidar data, and radar data may be combined using sensor fusion techniques or the like to generate a three-dimensional object map of the area surrounding the vehicle 105. The three-dimensional map may then be coordinated with a high-definition road map received via wireless transmission and stored in memory.

The processor 160 may use a three-dimensional object map, a high-definition road map, vehicle sensor data, and user data received as input to an ADAS algorithm (such as adaptive cruise control, lane centering operations, autonomous lane changes, obstacle avoidance, etc.) through the user interface 165. In response to the ADAS algorithm, processor 160 may then generate control signals to couple to vehicle controller 155 in order to control vehicle operation. For example, the vehicle controller 155 may generate a steering control signal coupled to a steering controller, a throttle control signal coupled to a throttle controller, and a brake control signal coupled to a brake controller.

Timing is an important aspect of each controller 155 and processor 160 in order to coordinate data. For example, if the radar, lidar and image data cannot be accurately provided to processor 160 to provide accurate control signals to vehicle controller 155, then such data is not useful. Furthermore, in a vehicular environment, it is critical that this timing data and the associated inter-system communications be accurately communicated in the presence of a system failure or communication channel failure. To address this issue, the exemplary system provides a timed start protocol to avoid time jumps by employing an agreed protocol that takes into account multiple time domains and multiple fault conditions. This time synchronization in the presence of faults enables fault operation applications that rely on the concept of global time, such as class 4 autonomous vehicles.

In the exemplary embodiment, system 100 is operable to employ a communication bus 190 in which each controller is coupled to two other controllers in a ring configuration. Data sent over the network may be unidirectional or bidirectional. Multiple clock trees may be used to form multiple time domains. An exemplary startup protocol may be used to select the time domain in the normal operating mode and in all failure modes to ensure consistency between all endpoints in the system regardless of failure mode. In an exemplary embodiment, the start-up protocol may be used for multiple Grand masters while ensuring that there is no time jump in case the Grand masters fail at run-time. The startup protocol may be used to switch between multiple clock trees (multiple time domains) when there is a failure to ensure that there are no time jumps in failure mode.

The system 100 is operable to provide a protocol to provide time synchronization for a plurality of systems in a plurality of time domains in a normal mode and a failure mode. In this example, an end node within the first time domain may be selected as a grandparent for providing a root timing reference to the first time domain. The end node having the grandparent is operable to periodically transmit synchronization information to a clock residing within the first time domain. The end node having the grandparent is further operable to transmit a subsequent frame that is used to track the transmission time of each node in the network. Using the subsequent frame, the node may utilize the synchronization frame and the subsequent frame to synchronize with the grandparent. In addition, systems with a clock in the first time domain can then relay the exact time to other time domains to which they are also connected. The exemplary system may then ensure consistency among all endpoints in the system regardless of failure modes.

In exemplary system 100, video controller 115, lidar controller 125, radar controller 145, processor 160, and vehicle controller 155 may be configured to form a time domain. In the normal mode, processor 160 may be selected to have the grandparent clock and may be operable to transmit synchronization packets to other nodes in the time domain in response to the grandparent clock. In this example, processor 160 has a master port and radar controller 145 has a slave port. Radar controller 145 transmits the time synchronization signal through the master port to the slave port at lidar controller 125, lidar controller 125 transmits the time synchronization signal through the master port to the slave port at video controller 115, and video controller 115 transmits the time synchronization signal through the master port to the slave port at vehicle controller 155. Each node within the time domain is operable to time synchronize with the synchronization frame received from its respective master port and discard the other time frames received.

In the event of a link failure, a node in the time domain may stop receiving synchronization frames from the designated node master port via its slave port. For example, if there is a link failure between lidar controller 125 and video controller 115, the video controller will stop receiving synchronization frames from lidar controller 125. Further, the video controller 115 will stop generating the synchronization signal to be transmitted, and thus the vehicle controller 155 will stop receiving the synchronization signal from the video controller 115. In response to not receiving many synchronization signals from the designated node, the node may determine that a failure mode exists and resort to replacing the designated node master port. In this example, the processor 160 would then become transmitting a synchronization signal to the vehicle controller 155, and the vehicle controller 155 would transmit a synchronization signal to the video controller 115. In the failure mode, the video controller 115 then synchronizes its clock to the synchronized frame and subsequent frames received from the vehicle controller 155. Likewise, the vehicle controller 155 synchronizes its clock to the synchronization frame and the subsequent frames received from the processor 160.

In this exemplary time domain, each node will only need one replacement node to receive the time synchronization signal when a failure mode is detected. For example, in the exemplary time domain, lidar controller 125 will synchronize with the synchronization frame from radar controller 145 unless there is a link failure between processor 160 and radar controller 145 or between radar controller 145 and lidar controller 125. In the event of any other link failure, lidar controller 125 will still receive a synchronization frame from radar controller 145. If lidar controller 125 stops receiving synchronization frames from radar controller 145, lidar controller 125 will then switch to video controller 155 as the master.

Turning now to fig. 2, a block diagram depicting an exemplary system 200 for fault tolerant ethernet time synchronization in a motor vehicle is shown. In the exemplary embodiment, system 200 may include an ethernet protocol network constructed in a ring configuration. An exemplary network may include switches S1220, S2240, S3260, S4270 and edge nodes or endpoints E1210, E2230, E3250, E4280. In some configurations, the switches S1220, S2240, S3260, S4270 may be integrated with the edge nodes E1210, E2230, E3250, E4280. For example, the lidar sensor may be an edge node in a network with an integrated switch. During normal operation, E1210 may be designated as the grandparent clock, while S1220 is the slave of E1210. S1220 is the master of S2240 and S3260, E2230 is the slave of S2240, and E3250 is the slave of S3260. In this exemplary embodiment, S4270 is then the slave of S2240, and the link between S3260 and S5 is disabled for clock synchronization purposes.

A link failure may be detected in response to the edge node not receiving an expected synchronization packet from the primary node. For example, if a link failure occurs between S1220 and S3260, E3250 will no longer receive synchronization packets from E1210. E3250 will then switch to the alternate configuration or domain because S4270 will then become the alternate master for S3260 and E2230 will receive the synchronization packet from E4280. When a link failure occurs between S1220 and S3260, S3260 becomes the slave of S4270, and the link between S1220 and S3260 is disabled. Likewise, when a link failure occurs between S1220 and S2240, S4270 becomes the slave of S3260, and S2240 becomes the slave of S4270, the link between S1220 and S2240 is disabled. If a link failure occurs between S2240 and S4270, S3260 becomes the master of S4270, and S1220 is the master of S2240 and S3260, and the link between S2240 and S4270 is disabled. For each possible link failure, a node that did not receive a synchronization packet will switch to an alternate master node.

To accommodate link failures or grandparent runtime failures that would isolate a designated grandparent node, a multiple grandparent startup protocol is provided to ensure that there are no time hops. To avoid these problems, a secondary grandparent is assigned for each time domain. On startup, the secondary grandfather will start its own clock. The secondary grandfather is operable to attempt to receive a synchronization frame from the primary grandfather over the ordinary master node. The secondary grandparent is operable to attempt to receive a synchronization frame from the alternate master node if the synchronization frame is not received by the ordinary master node. The secondary grandparent is operable to generate and transmit a synchronization packet as the primary grandparent in response to its own clock if a synchronization frame is not received from the alternate primary node within a predetermined period of time. The secondary grandparent is operable to synchronize its own clock to the grandparent's clock if a synchronization frame is received from the grandparent at startup. If a link failure occurs later and no more synchronization packets are received from the grandparent through either the ordinary master node or the alternate master node, the secondary grandparent will generate a synchronization frame from its own previous synchronization clock and transmit the synchronization frame over the time domain network. The startup protocol ensures that there are no time jumps in failure mode because the secondary grandparent clock is synchronized to the primary grandparent.

Turning now to fig. 3, a flow diagram is shown illustrating an exemplary method 300 for fault tolerant ethernet time synchronization in a motor vehicle. In the exemplary embodiment, the edge node is operable to perform exemplary method 300. The exemplary method 300 may first operate to initialize 310 an internal clock. After initialization of the internal clock, the method is next operable to operate according to the timing of the internal clock at 320. For example, an exemplary edge node may be a radar controller operable to execute a vehicle radar algorithm. The radar controller may be further operable to cascade its internal clock via a synchronization signal to the radar sensor, thereby forming another time domain with the radar sensor.

The method is next operable to determine whether a synchronization signal has been received from the primary grandparent node, at 330. If a synchronization signal has been received from the primary grandparent node, method 300 may next operate to synchronize the internal clock at 340 and return to operating with the internal clock at 320. If a synchronization signal has not been received from the primary grandparent node for a predetermined number of clock cycles (such as eight clock cycles), the method 300 may operate to determine whether a synchronization signal has been received from the switching portion of the alternate primary edge node at 350. If a synchronization signal has been received from the surrogate master at 350, the method 300 may operate to synchronize the internal clock to the synchronization signal from the surrogate master at 340 and return to operating with the internal clock at 320. In an exemplary embodiment, the surrogate master may become the master, while the previous master may become the surrogate master, depending on design criteria. Alternatively, the surrogate master may remain the surrogate master and the edge node continues to check for synchronization signals from the surrogate master before synchronizing to the synchronization signals from the surrogate master.

If a synchronization signal is received at 350 for a slave replacement master, the method 300 may next operate to determine at 360 whether the current edge node running the method has been designated as a replacement grandparent. If the current edge node is not designated as a replacement grandparent at 360, the method 300 is operable to generate an error signal indicative of loss of synchronization at 380 and couple the error signal to a system controller, vehicle controller, or other supervisory controller. The method may then return to operating with the current clock at 320. Alternatively, in response to loss of synchronization, the current node may be turned off 390, enter a standby state, or enter an alternate operational state.

If the current node is determined to be an alternate grandparent at 360, the method 300 may be operable to generate and transmit 370 a synchronization signal to the other nodes via the Ethernet network. The method may further generate a subsequent frame indicating the accumulated propagation delay, etc. After transmission 370 of the synchronization signal, the method may then return to operating with the current clock at 320.

Turning now to fig. 4, a block diagram illustrating an exemplary system 400 for fault tolerant ethernet time synchronization in a motor vehicle network is shown. Exemplary system 400 may include a first network node 410 and a first switch 415, a second network node 420 and a second switch 425, and a third network node 430 and a third switch 435. The first network switch may be coupled to the second network switch via a first link 475. The first network switch 415 may be coupled to a third network switch by a second link 480. Second network switch 425 may be coupled to third network switch 435 via third link 485.

In an exemplary embodiment, the first network node 410 coupled to the first switch 415 is configured to generate and transmit a first time synchronization signal in response to a first clock internal to the first network node 410. The first switch 415 may be integrated into the first network node and configured to transmit data over the ethernet network through the master port and receive data from the ethernet network through the slave port. These ports are configurable and may switch from master to slave or vice versa in response to network link failures, control signals from the first network node 410, and the like. In an exemplary embodiment, the first clock may be designated as a grandparent clock to serve as a timing reference for all nodes having the time domain of the ethernet network. The first network node 410 may be further configured to generate a subsequent frame indicative of a first delay caused by the processing of the first time synchronization signal by the first switch 415, and the second network node 420 may be operable to update the subsequent node in response to the first latency and a second latency caused by the processing of the first time synchronization signal by the second switch 425.

The second network node 420 comprising the second switch 425 may be configured for receiving the first time synchronization signal from the first switch 415 and for transmitting the second time synchronization signal to the third switch 435. In an exemplary application, the first network node 410 may be a lidar controller and the second network node 420 may be a lidar sensor. In response to a network link failure, the second network node 420 may enable the primary port in response to the link failure.

In the exemplary embodiment, a third network node 430 that includes a third switch 435 is configured to receive a first time synchronization signal from first switch 415 and a second time synchronization signal from second switch 425. The third network node 430 may be further operable to synchronize the third node internal clock to the first synchronization signal in response to receiving the first time synchronization signal from the first switch 415 via the second link 480. The third network node 430 may be further operable to synchronize the internal clock to the second synchronization signal in response to not receiving the first time synchronization signal from the first switch 415 over the second link 480. In an exemplary embodiment, the internal clock may be synchronized to the second time synchronization signal in response to detection of a link failure between the first switch 415 and the third switch 435, wherein the link failure is determined in response to the third switch 435 not receiving the first time synchronization signal for a plurality of time synchronization intervals. In an exemplary application, the third switch 435 is operable to redefine the port role from the slave port to the master port in response to a link failure. The exemplary system can further include a fourth switch, wherein the third switch 435 is operable to transmit the second time synchronization signal to the fourth switch in response to the link failure.

In an exemplary embodiment, the exemplary system 400 may be a vehicle communication network including a vehicle controller having a first network switch and a grandparent clock, wherein the vehicle controller is operable to generate a first time synchronization frame in response to the grandparent clock and to couple the first time synchronization from the first network switch to a second network switch over a first data link and to couple the first time synchronization from the first network switch to a third network switch over a second data link. The example system 400 also includes a first vehicle sensor having a second network switch configured to receive the first time sync frame via a first data link, configured to generate a second time sync frame in response to the first time sync frame and transmit the second time sync frame to a third network switch over a third data link. The example system 400 also includes a second vehicle sensor having a third network switch and an internal clock, wherein the second vehicle sensor is operable to synchronize the internal clock with the grandparent clock according to the first time synchronization signal in response to receiving the first time synchronization frame, and synchronize the internal clock with the grandparent clock according to the second time synchronization signal in response to not receiving the first time synchronization frame. In addition, the second vehicle sensor may be configured to synchronize the internal clock with the grandparent clock according to the second time synchronization signal in response to not receiving the first time synchronization frame within the plurality of time synchronization intervals.

Turning now to fig. 5, a block diagram is shown illustrating an exemplary method 500 for fault tolerant ethernet time synchronization during a grandparent fault in a motor vehicle. The exemplary method is first operable to generate 510 a time synchronization signal to synchronize a plurality of nodes in a multi-time domain network configuration. The time synchronization signal may be generated by an edge node designated as a grandparent. For example, the time synchronization signal may be generated by a radar controller coupled to the first radar sensor and the second radar sensor. In an exemplary embodiment, each radar sensor may be an edge node having an integrated switching node with at least one port configured as a slave mode. The method may be further operable to generate subsequent frames with timestamps for determining latencies accumulated during propagation through the one or more switching nodes and end nodes.

The method may transmit 520 a time synchronization signal from the first switch to the second switch via the first link and from the first switch to the third switch via the second link. In an exemplary embodiment, there may be a third link between the second switch and the third switch that is disabled for network synchronization purposes.

The method is next operable for detecting 530 a link failure of the second link, the link failure being detected in response to the third switch not receiving the time synchronization signal via the second link. In an exemplary embodiment, the link failure may be detected in response to the third switch not receiving the time synchronization signal via the second link for a plurality of time synchronization intervals.

In response to detecting the link failure, the method 500 is then configured to transmit 540 the time synchronization signal from the second switch to the third switch via the third link. The second switch may enable the master port in response to the link failure, wherein the port has been previously configured as a slave port. The third switch may receive the time synchronization signal from the second switch and then couple the time synchronization signal to the edge node. In response, the edge node may synchronize the internal clock in response to the time synchronization signal. Additionally, the example system may include a fourth switch operable to receive a time synchronization signal from the third switch. In this exemplary embodiment, the third switch may enable the master port to transmit the time synchronization signal to the fourth switch.

It should be emphasized that many variations and modifications may be made to the embodiments described herein, and the elements thereof should be understood to be in other acceptable examples. All such modifications and variations are intended to be included herein within the scope of this disclosure and protected by the following claims. Further, any steps described herein may be performed concurrently or in a different order than the steps sequenced herein. Moreover, it should be apparent that the features and attributes of the specific embodiments disclosed herein may be combined in different ways to form additional embodiments, all of which fall within the scope of the present disclosure.

Conditional language, such as "may," "might," "for example," and the like, as used herein, unless expressly stated otherwise or understood in the context of such usage, is generally intended to convey that certain embodiments include, but not certain features, elements, and/or states. Thus, such conditional language is not generally intended to imply that features, elements, and/or states are in any way required for one or more embodiments or that one or more embodiments necessarily include logic for determining, with or without author input or prompting, whether such features, elements, and/or states are included or are to be performed in any particular embodiment.

Further, the following terminology may be used herein. The singular forms "a", "an" and "the" include plural referents unless the context clearly dictates otherwise. Thus, for example, a reference to an item includes a reference to one or more items. The term "that" means one, two or more, and generally applies to the selection of some or all of the numbers. The term "plurality" means one or more. The terms "about" or "approximately" mean that the quantity, dimensions, size, formulation, parameters, shape, and other characteristics need not be exact, but may be approximate and/or larger or smaller as desired, reflecting acceptable tolerances, conversion factors, rounding off, measurement error and the like, and other factors known to those of skill in the art. The term "substantially" means that the recited characteristic, parameter, or value need not be achieved exactly, but that deviations or variations, including, for example, tolerances, measurement error, measurement accuracy limitations, and other factors known to those skilled in the art, may occur in amounts that do not preclude the effect that the characteristic is intended to provide.

The processes, methods or algorithms disclosed herein may be delivered to/performed by a processing device, controller or computer, which may comprise any conventional programmable or dedicated electronic control unit. Similarly, the processes, methods or algorithms may be stored as data and instructions executable by a controller or computer in a variety of forms including, but not limited to, information permanently stored on non-writable storage media such as ROM devices and information alterably stored on writable storage media such as floppy diskettes, magnetic tapes, CDs, RAM devices and other magnetic and optical media. A process, method, or algorithm may also be implemented in a software executable object. Alternatively, the processes, methods or algorithms may be embodied in whole or in part using suitable hardware components such as Application Specific Integrated Circuits (ASICs), Field Programmable Gate Arrays (FPGAs), state machines, controllers or other hardware components or devices, or a combination of hardware, software and firmware components. Such example devices may be onboard a vehicle as part of a vehicle computing system or located off-board and in remote communication with devices on one or more vehicles.

While exemplary embodiments are described above, it is not intended that these embodiments describe all possible forms encompassed by the claims. The words used in the specification are words of description rather than limitation, and it is understood that various changes may be made without departing from the spirit and scope of the disclosure. As previously noted, features of the various embodiments may be combined to form other exemplary aspects of the disclosure that may not be explicitly described or illustrated. Although various embodiments may be described as providing advantages or being preferred over other embodiments or over prior art implementations with respect to one or more desired features, those of ordinary skill in the art will recognize that one or more features or characteristics may be compromised to achieve desired overall system attributes, which depend on the particular application and implementation. These attributes may include, but are not limited to, cost, strength, durability, life cycle cost, marketability, appearance, packaging, size, workability, weight, manufacturability, ease of assembly, and the like. As such, embodiments described as less desirable than other embodiments or prior art implementations with respect to one or more features are outside the scope of the present disclosure and may be desirable for particular applications.