阅读说明：本技术 基于EtherCAT的通信处理方法、装置和处理器 (Communication processing method, device and processor based on EtherCAT ) 是由 黄哲 钟成堡 王剑 林钰棋 周海亮 于 2021-07-20 设计创作，主要内容包括：本发明公开了一种基于EtherCAT的通信处理方法、装置和处理器,基于EtherCAT的通信处理方法包括：获取从站的第一通信信息,第一通信信息包括从站时钟信息；获取主站的FPGA的时钟信息作为参考时钟信息；根据参考时钟信息和从站时钟信息,计算时钟补偿信息；向从站发送第二通信信息,第二通信信息包括时钟补偿信息。本发明的基于EtherCAT的通信处理方法解决了现有技术中的EtherCAT网络在应用于不同场景时的实时性难以保证的问题。(The invention discloses a communication processing method, a device and a processor based on EtherCAT, wherein the communication processing method based on EtherCAT comprises the following steps: acquiring first communication information of a slave station, wherein the first communication information comprises slave station clock information; acquiring clock information of an FPGA of a master station as reference clock information; calculating clock compensation information according to the reference clock information and the slave station clock information; and transmitting second communication information to the slave station, the second communication information including the clock compensation information. The communication processing method based on the EtherCAT solves the problem that the real-time performance of the EtherCAT network in the prior art is difficult to guarantee when the EtherCAT network is applied to different scenes.)

1. A communication processing method based on EtherCAT is characterized by comprising the following steps:

acquiring first communication information of a slave station, wherein the first communication information comprises slave station clock information;

acquiring clock information of an FPGA of a master station as reference clock information;

calculating clock compensation information according to the reference clock information and the slave station clock information;

transmitting second communication information to the slave station, the second communication information including the clock compensation information.

2. The EtherCAT-based communication processing method according to claim 1, wherein calculating clock compensation information from the reference clock information and the slave clock information includes:

and controlling the FPGA to calculate clock compensation information according to the reference clock information and the slave station clock information.

3. The EtherCAT-based communication processing method according to claim 1, wherein calculating clock compensation information from the reference clock information and the slave clock information includes:

and calculating clock delay information and clock offset information of each slave station relative to a master station according to the reference clock information and the slave station clock information, wherein the clock compensation information comprises the clock delay information and the clock offset information.

4. The EtherCAT-based communication processing method according to claim 1, wherein acquiring first communication information of a slave station, the first communication information including slave station clock information, comprises:

receiving communication data from the secondary station;

and analyzing the communication data to obtain the first communication information.

5. The EtherCAT-based communication processing method according to any of claims 1-4, wherein prior to sending the second communication information to the secondary station, the EtherCAT-based communication processing method further comprises:

acquiring target control information processed by an operating system unit;

and encapsulating the target control information and the clock compensation information to obtain the second communication information.

6. The EtherCAT-based communication processing method according to claim 5, wherein the first communication information further includes control parameter information, and before acquiring the target control information processed by the operating system unit, the EtherCAT-based communication processing method further includes:

controlling an operating system unit of the master station to acquire the control parameter information;

and controlling the operating system unit to calculate the target control information according to the control parameter information.

7. The EtherCAT-based communication processing method according to claim 6,

after the control operating system unit calculates the target control information according to the control parameter information, the communication processing method based on EtherCAT further includes: controlling the target control information to be stored in a memory unit of the master station;

the acquiring of the target control information processed by the operating system unit includes: and acquiring the target control information from the memory unit.

8. An EtherCAT-based communication processing apparatus, comprising:

the first obtaining module is used for obtaining first communication information of a slave station, wherein the first communication information comprises slave station clock information;

the second acquisition module is used for acquiring clock information of the FPGA of the master station as reference clock information;

the first calculation module is used for calculating clock compensation information according to the reference clock information and the slave station clock information;

a sending module, configured to send second communication information to the slave station, where the second communication information includes the clock compensation information.

9. A non-volatile storage medium, comprising a stored program, wherein when the program runs, a device in which the non-volatile storage medium is located is controlled to execute the EtherCAT-based communication processing method according to any one of claims 1 to 7.

10. A processor, configured to execute a program, wherein the program executes the EtherCAT-based communication processing method according to any one of claims 1 to 7.

11. An EtherCAT master station apparatus comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements the EtherCAT-based communication processing method according to any one of claims 1 to 7 when executing the computer program.

Technical Field

The invention relates to the field of Ethernet communication control, in particular to a communication processing method, a communication processing device and a communication processing processor based on EtherCAT.

Background

In the conventional EtherCAT network, generally, the first slave station supporting distributed synchronization is used as a reference clock to perform distributed synchronization on each subsequent slave station. By adopting the mode, when the master station is applied to different scenes, the slave stations can be different, and the accuracy of clocks of the slave station systems when the master station is applied to various scenes cannot be ensured, so that the real-time performance is difficult to ensure when the EtherCAT network is applied to different scenes.

In view of the above problems, no effective solution has been proposed.

The above information disclosed in the background section is only for enhancement of understanding of the background of the technology described herein. The background art may therefore contain certain information that does not form the known prior art to those skilled in the art.

Disclosure of Invention

The embodiment of the invention provides a communication processing method, a device and a processor based on EtherCAT, which are used for at least solving the problem that the real-time performance of an EtherCAT network in the prior art is difficult to guarantee when the EtherCAT network is applied to different scenes.

In order to achieve the above object, according to a first aspect of the embodiments of the present invention, there is provided an EtherCAT-based communication processing method, including: acquiring first communication information of a slave station, wherein the first communication information comprises slave station clock information; acquiring clock information of an FPGA of a master station as reference clock information; calculating clock compensation information according to the reference clock information and the slave station clock information; and transmitting second communication information to the slave station, the second communication information including the clock compensation information.

Further, calculating clock compensation information based on the reference clock information and the slave clock information, comprising: and controlling the FPGA to calculate clock compensation information according to the reference clock information and the slave station clock information.

Further, calculating clock compensation information based on the reference clock information and the slave clock information, comprising: and calculating clock delay information and clock offset information of each slave station relative to the master station according to the reference clock information and the slave station clock information, wherein the clock compensation information comprises the clock delay information and the clock offset information.

Further, acquiring first communication information of the slave station, wherein the first communication information comprises slave station clock information, and the method comprises the following steps: receiving communication data from a slave station; and analyzing the communication data to obtain first communication information.

Further, before sending the second communication information to the slave station, the communication processing method based on EtherCAT further includes: acquiring target control information processed by an operating system unit; and encapsulating the target control information and the clock compensation information to obtain second communication information.

Further, the first communication information further includes control parameter information, and before acquiring the target control information processed by the operating system unit, the communication processing method based on EtherCAT further includes: an operating system unit of a control master station acquires control parameter information; and the control operation system unit calculates target control information according to the control parameter information.

Further, after the control operating system unit calculates the target control information according to the control parameter information, the communication processing method based on EtherCAT further includes: controlling to store the target control information to a memory unit of the master station; the acquiring of the target control information processed by the operating system unit includes: and acquiring target control information from the memory unit.

According to a second aspect of the embodiments of the present invention, there is provided an EtherCAT-based communication processing apparatus, including: the first obtaining module is used for obtaining first communication information of the slave station, and the first communication information comprises slave station clock information; the second acquisition module is used for acquiring clock information of the FPGA of the master station as reference clock information; the first calculation module is used for calculating clock compensation information according to the reference clock information and the slave station clock information; and the sending module is used for sending second communication information to the slave station, wherein the second communication information comprises clock compensation information.

According to a third aspect of the embodiments of the present invention, a nonvolatile storage medium is provided, where the nonvolatile storage medium includes a stored program, and when the program runs, a device where the nonvolatile storage medium is located is controlled to execute the above communication processing method based on EtherCAT.

According to a fourth aspect of the embodiments of the present invention, there is provided a processor, where the processor is configured to execute a program, where the program executes the above communication processing method based on EtherCAT.

According to a fifth aspect of the embodiments of the present invention, there is provided an EtherCAT master station apparatus, including a memory, a processor, and a computer program stored in the memory and executable on the processor, where the processor implements the above-described EtherCAT-based communication processing method when executing the computer program.

The communication processing method based on EtherCAT applying the technical scheme of the invention comprises the following steps: acquiring first communication information of a slave station, wherein the first communication information comprises slave station clock information; acquiring clock information of an FPGA of a master station as reference clock information; calculating clock compensation information according to the reference clock information and the slave station clock information; and transmitting second communication information to the slave station, the second communication information including the clock compensation information. Like this, the clock information of the FPGA of the main website is used as reference clock information, because FPGA has the advantage that the real-time is good, no matter under what kind of scene the main website is applied to, no matter how the slave station changes, a reliable reference clock information can be provided, thereby can send out more accurate clock compensation information to each slave station, guarantee the accuracy of slave station clock, the main website possesses reliable reference clock, more environment of easier adaptation, the problem that the real-time nature of the etherCAT network among the prior art when being applied to different scenes is difficult to guarantee is solved. By adopting the communication processing method based on the EtherCAT, which is based on the scheme, the reference clock of the slave station is not relied on, the unified clock can effectively avoid the risk of error of the slave station clock, and the real-time performance of the whole EtherCAT network is improved.

Drawings

The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this application, illustrate embodiment(s) of the invention and together with the description serve to explain the invention without limiting the invention. In the drawings:

fig. 1 is a schematic flow chart of an alternative embodiment of an EtherCAT-based communication processing method according to the present invention;

fig. 2 is a schematic diagram of an alternative embodiment of an EtherCAT-based communication processing apparatus according to the present invention;

fig. 3 is a schematic diagram of an EtherCAT master station apparatus according to an embodiment of the invention;

wherein the figures include the following reference numerals:

1. a master station; 11. an operating system unit; 12. an FPGA; 121. a communication unit; 122. a verification unit; 123. a data processing unit; 124. a timer unit; 13. an ECAT network port; 14. a memory unit; 2. and (4) a secondary station.

Detailed Description

It should be noted that the embodiments and features of the embodiments in the present application may be combined with each other without conflict. The present application will be described in detail below with reference to the embodiments with reference to the attached drawings.

In order to make the technical solutions of the present invention better understood, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

It should be noted that the terms "first," "second," and the like in the description and claims of the present invention and in the drawings described above are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used is interchangeable under appropriate circumstances such that the embodiments of the invention described herein are capable of operation in sequences other than those illustrated or described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed, but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.

It will be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" another element, it can be directly on the other element or intervening elements may also be present. Also, in the specification and claims, when an element is described as being "connected" to another element, the element may be "directly connected" to the other element or "connected" to the other element through a third element.

Fig. 1 is a communication processing method based on EtherCAT according to an embodiment of the present invention, as shown in fig. 1, the method includes the following steps:

step S102, acquiring first communication information of a slave station, wherein the first communication information comprises slave station clock information;

step S104, acquiring clock information of the FPGA of the master station as reference clock information;

step S106, calculating clock compensation information according to the reference clock information and the slave station clock information;

step S108, second communication information is sent to the slave station, and the second communication information comprises clock compensation information.

The communication processing method based on the EtherCAT adopting the scheme comprises the following steps: acquiring first communication information of a slave station, wherein the first communication information comprises slave station clock information; acquiring clock information of an FPGA of a master station as reference clock information; calculating clock compensation information according to the reference clock information and the slave station clock information; and transmitting second communication information to the slave station, the second communication information including the clock compensation information. Like this, the clock information of the FPGA of the main website is used as reference clock information, because FPGA has the advantage that the real-time is good, no matter under what kind of scene the main website is applied to, no matter how the slave station changes, a reliable reference clock information can be provided, thereby can send out more accurate clock compensation information to each slave station, guarantee the accuracy of slave station clock, the main website possesses reliable reference clock, more environment of easier adaptation, the problem that the real-time nature of the etherCAT network among the prior art when being applied to different scenes is difficult to guarantee is solved. By adopting the communication processing method based on the EtherCAT, which is based on the scheme, the reference clock of the slave station is not relied on, the unified clock can effectively avoid the risk of error of the slave station clock, and the real-time performance of the whole EtherCAT network is improved.

Specifically, calculating clock compensation information from reference clock information and slave clock information includes: and controlling the FPGA to calculate clock compensation information according to the reference clock information and the slave station clock information. The clock compensation information is calculated by adopting the FPGA according to the reference clock information and the slave station clock information, so that the FPGA completes the calculation of the clock compensation information, the performance occupation of an operating system unit of the master station is saved, the FPGA can have more calculation power to complete other calculation work (for example, the calculation of relevant parameters of the multi-joint motor is better performed), and the information processing capacity of the master station is improved.

In this embodiment, in order to better perform clock compensation and improve the real-time performance of the EtherCAT network, the calculating of the clock compensation information according to the reference clock information and the slave station clock information includes: and calculating clock delay information and clock offset information of each slave station relative to the master station according to the reference clock information and the slave station clock information, wherein the clock compensation information comprises the clock delay information and the clock offset information.

Specifically, acquiring first communication information of a slave station, wherein the first communication information comprises slave station clock information, and the method comprises the following steps: receiving communication data from a slave station; and analyzing the communication data to obtain first communication information.

Before sending the second communication information to the slave station, the communication processing method based on EtherCAT further comprises the following steps: acquiring target control information processed by an operating system unit; and encapsulating the target control information and the clock compensation information to obtain second communication information. By encapsulating the target control information and the clock compensation information and sending the target control information and the clock compensation information together, the slave station clock can be synchronously corrected when the slave station is controlled, and the real-time performance of the EtherCAT network is improved.

Specifically, the first communication information further includes control parameter information, and before acquiring the target control information processed by the operating system unit, the communication processing method based on EtherCAT further includes: an operating system unit of a control master station acquires control parameter information; and the control operation system unit calculates target control information according to the control parameter information. That is to say, the calculation process of the target control information is completed in the operating system unit, and the calculation of the clock compensation information is completed in the FPGA, so that the calculation occupation of the operating system unit is reduced, and the operating system unit is favorable for better completing the calculation of the target control information.

After the control operating system unit calculates the target control information according to the control parameter information, the communication processing method based on EtherCAT further includes: controlling to store the target control information to a memory unit of the master station; the acquiring of the target control information processed by the operating system unit includes: and acquiring target control information from the memory unit. After the calculation of the target control information is completed, the operating system unit stores the target control information in the memory unit, and when the target control information and the clock compensation information are encapsulated, the target control information is acquired from the memory unit, so that the memory occupation of the operating system unit can be avoided, the operating system unit can have the capability of processing the next batch of data more timely, and the EtherCAT network is ensured to have better use effect.

According to a second aspect of the embodiments of the present invention, there is provided an EtherCAT-based communication processing apparatus, including: the first obtaining module is used for obtaining first communication information of the slave station, and the first communication information comprises slave station clock information; the second acquisition module is used for acquiring clock information of the FPGA of the master station as reference clock information; the first calculation module is used for calculating clock compensation information according to the reference clock information and the slave station clock information; and the sending module is used for sending second communication information to the slave station, wherein the second communication information comprises clock compensation information.

The first calculation module includes a control sub-module: and the control submodule is used for controlling the FPGA to calculate clock compensation information according to the reference clock information and the slave station clock information.

The first calculation module is used for calculating clock delay information and clock offset information of each slave station relative to the master station according to the reference clock information and the slave station clock information, and the clock compensation information comprises the clock delay information and the clock offset information.

The first acquisition module comprises a receiving submodule and an analysis submodule: the receiving submodule is used for receiving communication data from the slave station; the analysis submodule is used for analyzing the communication data to obtain first communication information.

Before sending the second communication information to the slave station, the communication processing method based on EtherCAT further comprises a third obtaining module and an encapsulating module: the third acquisition module is used for acquiring the target control information processed by the operating system unit; the encapsulation module is used for encapsulating the target control information and the clock compensation information to obtain second communication information.

The first communication information further comprises control parameter information, and before the target control information processed by the operating system unit is acquired, the communication processing method based on the EtherCAT further comprises a first control module and a second calculation module: the first control module is used for controlling an operating system unit of the master station to acquire control parameter information; the second calculation module is used for controlling the operation system unit to calculate target control information according to the control parameter information.

After the control operating system unit calculates the target control information according to the control parameter information, the communication processing method based on the EtherCAT further comprises a second control module: the second control module is used for controlling the memory unit for storing the target control information to the master station; the third obtaining module is used for obtaining the target control information from the memory unit.

In addition, the embodiment of the invention also provides a nonvolatile storage medium, the nonvolatile storage medium includes a stored program, and when the program runs, the device where the nonvolatile storage medium is located is controlled to execute the communication processing method based on EtherCAT.

The embodiment of the invention further provides a processor, wherein the processor is used for running the program, and the communication processing method based on the EtherCAT is executed when the program runs.

Finally, the embodiment of the invention also provides an EtherCAT master station device, which comprises a memory, a processor and a computer program stored in the memory and capable of running on the processor, wherein the processor implements the communication processing method based on EtherCAT when executing the computer program.

Fig. 3 is a schematic diagram of an EtherCAT master station apparatus according to an embodiment of the present invention, in which a master station 1 and a slave station 2 are shown, where the master station 1 includes an operating system unit 11, an FPGA12, an ECAT portal 13, and a memory unit 14, and the FPGA12 unit specifically includes a communication unit 121, a verification unit 122, a data processing unit 123, and a timer unit 124. Hereinafter, a communication processing method based on EtherCAT will be described with reference to this embodiment:

after each initialization process of the master station 1 is completed, the master station 1 selects an FPGA12 clock as a reference clock of the EtherCAT network, the FPGA12 is used for processing timing transceiving and calculating transmission delay, and the clock of the operating system unit 11 is used for maintaining normal operation of the operating system unit 11. The master station 1 is activated and enters the PDO communication phase, taking as an example the receipt of the slave station 2 signal by ECAT port 13, and the resulting communication datagram is delivered to communication unit 121, communication unit 121 having the purpose of obtaining and storing the operable datagram, after being verified by the verification unit 122, the data processing unit 123 parses the datagram, obtains the first communication information, and reports the obtained slave station clock information to the timer unit 124 by means of key value pair, stores the control parameter information (key information such as control word and parameter value) of the datagram to the memory unit 14, and sends a signal to inform the operating system unit 11 to fetch the control parameter information from the memory unit 14, after the operating system unit 11 calculates through an algorithm, the obtained target control information is stored back in the memory unit 14, and the operating system unit 11 sends a signal for retrieving the target control information from the memory unit 14 to the FPGA 12. The clock of the timer unit 124 is used as a reference clock, the clock delay and the clock offset of each slave station 2 relative to the master station 1 are calculated to obtain clock compensation information, the calculation result is sent back to the data processing unit 123, then the data processing unit 123 packages the target control information from the memory unit 14 and the clock compensation information from the timer unit 124 into a data frame, the data frame is checked whether the error occurs through the checking unit 122, if the error occurs, the data frame is discarded, the data processing unit 123 sends back the data frame to request retransmission, if the check occurs, the data frame is sent out periodically (for example, the period is 0.1ms) through the communication unit 121 and the ECAT network port 13, the time of the current transmission is recorded, a buffer is polled, the slave station is returned after the EtherCAT data frame is analyzed and completed, the slave station is received, and the next cycle is performed.

The above-mentioned serial numbers of the embodiments of the present invention are merely for description and do not represent the merits of the embodiments. Moreover, the steps illustrated in the flowcharts of the figures may be performed in a computer system such as a set of computer-executable instructions, and while a logical order is illustrated in the flowcharts, in some cases, the steps illustrated or described may be performed in an order different than here.

In the above embodiments of the present invention, the descriptions of the respective embodiments have respective emphasis, and for parts that are not described in detail in a certain embodiment, reference may be made to related descriptions of other embodiments.

In the embodiments provided in the present application, it should be understood that the disclosed technology can be implemented in other ways. The above-described embodiments of the apparatus are merely illustrative, and for example, the division of the units may be a logical division, and in actual implementation, there may be another division, for example, multiple units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, units or modules, and may be in an electrical or other form.

The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.

In addition, functional units in the embodiments of the present invention may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit. The integrated unit can be realized in a form of hardware, and can also be realized in a form of a software functional unit.

The integrated unit, if implemented in the form of a software functional unit and sold or used as a stand-alone product, may be stored in a computer readable storage medium. Based on such understanding, the technical solution of the present invention may be embodied in the form of a software product, which is stored in a storage medium and includes instructions for causing a computer device (which may be a personal computer, a server, or a network device) to execute all or part of the steps of the method according to the embodiments of the present invention. And the aforementioned storage medium includes: a U-disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a removable hard disk, a magnetic or optical disk, and other various media capable of storing program codes.

The foregoing is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, various modifications and decorations can be made without departing from the principle of the present invention, and these modifications and decorations should also be regarded as the protection scope of the present invention.