阅读说明：本技术 信号传输设备和驱动设备 (Signal transmission device and driving device ) 是由 蘭明文 于 2019-07-15 设计创作，主要内容包括：一种信号传输设备,具有脉冲发生器、RS F/F电路和检测器,当PWM信号的状态改变时,发生器产生置位脉冲信号和/或复位脉冲信号。在产生置位脉冲信号之后,发生器在经过从产生置位脉冲信号算起的预定时间周期之后连续地产生下一脉冲信号。发生器根据选择器信号对算到首次传输下一脉冲信号的时间的预定时间周期进行调节。检测器基于从RS F/F电路接收到置位脉冲信号或复位脉冲信号的时间起算,到首次接收到下一脉冲信号的时间的预定时间周期,对选择器信号的状态进行检测。(A signal transmission apparatus has a pulse generator that generates a set pulse signal and/or a reset pulse signal when the state of a PWM signal changes, an RS F/F circuit, and a detector. After the set pulse signal is generated, the generator continuously generates a next pulse signal after a predetermined period of time from the generation of the set pulse signal has elapsed. The generator adjusts the predetermined time period calculated to the time at which the next pulse signal is first transmitted in accordance with the selector signal. The detector detects the state of the selector signal based on a predetermined time period from the time when the RS F/F circuit receives the set pulse signal or the reset pulse signal to the time when the next pulse signal is first received.)

1. A signal transmission device comprising a pulse generator (10), an output circuit (16) and a detector (18), wherein,

the pulse generator (10) includes a first output terminal and a second output terminal, the pulse generator receiving a first signal having a high voltage level or a low voltage level, the pulse generator generating a set pulse signal based on a voltage level change of the first signal from the high voltage level to the low voltage level and transmitting the set pulse signal via the first output terminal, the pulse generator generating a reset pulse signal based on the voltage level change of the first signal from the low voltage level to the high voltage level and transmitting the reset pulse signal via the second output terminal,

the output circuit having a first input terminal, a second input terminal, and a third output terminal,

the output circuit transmits a first output signal corresponding to the high voltage level of the first signal via the third output terminal when the first input terminal receives the set pulse signal transmitted from the pulse generator,

the output circuit transmits a second output signal corresponding to the low voltage level of the first signal via the third output terminal when the second input terminal receives the reset pulse signal transmitted from the pulse generator,

wherein the content of the first and second substances,

the pulse generator generates and transmits at least one next pulse signal after a predetermined period of time from a time when the set pulse signal or the reset pulse signal is transmitted when the voltage level of the first signal changes,

the pulse generator receives a second signal having a plurality of voltage levels and changes the predetermined time period from a time when the set pulse signal or the reset pulse signal is transmitted to a time when the next pulse signal is first transmitted according to the second signal,

the detector detects the state of the second signal based on the predetermined time period from the time when the set pulse signal is received at the first input terminal to the time when the next pulse signal is first received at the first input terminal, or based on the time period from the time when the reset pulse signal is received at the second input terminal to the time when the next pulse signal is first received at the second input terminal.

2. The signal transmission apparatus of claim 1,

the pulse generator generates a plurality of next pulse signals and transmits the plurality of next pulse signals as the next pulse signals.

3. The signal transmission apparatus of claim 2,

the pulse generator changes the predetermined time period from a time when the set pulse signal or the reset pulse signal is first transmitted to a time when the plurality of next pulse signals are first transmitted based on the state of the second signal,

the pulse generator generates the plurality of next pulse signals having a constant time interval regardless of the state of the second signal.

4. The signal transmission apparatus of claim 2,

the pulse generator generates the plurality of next pulse signals having different frequencies corresponding to each of the voltage levels of the second signal, and changes the predetermined time period from a time when the set pulse signal or the reset pulse signal is first transmitted to the time when the plurality of next pulse signals is first transmitted, corresponding to each of the voltage levels of the second signal.

5. The signal transmission apparatus of any one of claims 1 to 4,

the pulse generator generates a plurality of set pulse signals or a plurality of reset pulse signals in a time period shorter than the predetermined time period, and transmits the plurality of set pulse signals as the set pulse signals or the plurality of reset pulse signals as the reset pulse signals.

6. A driving apparatus (1) that drives a plurality of semiconductor switching elements (24a, 24b) includes a pulse generator (10), an output circuit (16), a detector (18), a switching circuit (20), and a plurality of drivers (22a, 22b), wherein,

the pulse generator (10) includes a first output terminal and a second output terminal, the pulse generator receiving a PWM signal having a high voltage level or a low voltage level, the pulse generator generating a set pulse signal based on a voltage level change of the PWM signal from the high voltage level to the low voltage level and transmitting the set pulse signal via the first output terminal, the pulse generator generating a reset pulse signal based on the voltage level change of the PWM signal from the low voltage level to the high voltage level and transmitting the reset pulse signal via the second output terminal,

the output circuit includes a first input terminal, a second input terminal, and a third output terminal, the output circuit transmitting a first output signal corresponding to the high voltage level of the PWM signal via the third output terminal when the first input terminal receives the set pulse signal transmitted from the pulse generator,

the output circuit transmits a second output signal corresponding to a low voltage level of the PWM signal via a third output terminal when the second input terminal receives the reset pulse signal transmitted from the pulse generator,

the plurality of drivers arranged respectively corresponding to the plurality of semiconductor switching elements, transmitting a drive signal to each of the semiconductor switching elements in accordance with the first output signal and the second output signal transmitted from the output terminal of the output circuit,

the switching circuit switches connections between the output terminals of the output circuit and the plurality of drivers,

wherein the content of the first and second substances,

the pulse generator generates and transmits at least one next pulse signal after a predetermined time interval from a time when the set pulse signal or the reset pulse signal is transmitted when the voltage level of the PWM signal is changed,

the pulse generator receives a selector signal whose state has a plurality of voltage levels corresponding to the plurality of semiconductor switching elements, and changes the predetermined time interval from a time at which the set pulse signal or the reset pulse signal is transmitted to a time at which the next pulse signal is first transmitted according to the state of the selector signal,

the detector detects the state of the selector signal based on a predetermined time period from a time when the set pulse signal is received by the first input terminal to a time when the next pulse signal is first received by the first input terminal, or based on a time period from a time when the reset pulse signal is received by the second input terminal to a time when the next pulse signal is first received by the second input terminal,

the detector instructs the switching circuit to connect the output terminal of the output circuit to one of the plurality of drivers based on a detection result thereof so as to drive one of the plurality of semiconductor switching elements.

7. The drive apparatus as recited in claim 6,

the pulse generator generates a plurality of next pulse signals and transmits the plurality of next pulse signals as the next pulse signals.

8. The drive apparatus as recited in claim 7,

the pulse generator changes the predetermined time period from a time when the set pulse signal or the reset pulse signal is first transmitted to a time when the plurality of next pulse signals are first transmitted based on the state of the selector signal,

the pulse generator generates the plurality of next pulse signals with a constant time interval regardless of the state of the selector signal.

9. The drive apparatus as recited in claim 7,

the pulse generator generates the plurality of next pulse signals having different frequencies corresponding to each of the voltage levels of the selector signal, and changes the predetermined time period from a time when the set pulse signal or the reset pulse signal is first transmitted to a time when the plurality of next pulse signals is first transmitted, corresponding to each of the voltage levels of the selector signal.

10. The drive apparatus according to any one of claims 6 to 9,

the pulse generator generates a plurality of set pulse signals or a plurality of reset pulse signals in a time period shorter than the predetermined time period, and transmits the plurality of set pulse signals as the set pulse signals or the plurality of reset pulse signals as the reset pulse signals.

11. The drive apparatus according to any one of claims 6 to 9,

the driving device drives the plurality of semiconductor switching elements composed of one of an IGBT, a SiC MOSFET, and a combination of the IGBT and the SiC MOSFET.

Technical Field

The present disclosure relates to a signal transmission device and a driving device equipped with the signal transmission device that drives a semiconductor switch.

Background

For example, patent document 1, japanese patent laid-open No. 2007-6048 discloses a power semiconductor apparatus equipped with a power apparatus, a high-voltage side driver, and a low-voltage side driver. The power devices include a high-voltage side power device and a low-voltage side power device connected in series. The high-voltage-side driver drives the high-voltage-side power device, and the low-voltage-side driver drives the low-voltage-side power device.

The high voltage side driver has a pulse generator. When the high voltage side driver receives a high voltage side signal transmitted from an external electronic control unit including a microcomputer, the pulse generator generates two types of signals, an on signal and an off signal in a pulse form according to the received high voltage side signal, such as a pulse width modulation signal (PWM signal).

When the gate terminal of each level shifter transistor receives the on signal and the off signal transmitted from the pulse generator, a high voltage is supplied to the drain terminal of each level shifter transistor, which is connected to the set signal input terminal and the reset signal input terminal of the flip-flop circuit through an inverter.

An output terminal of the flip-flop circuit is connected to a gate terminal of each of a PMOS transistor and an NMOS transistor as a high-voltage-side drive element. A drain terminal of each of the PMOS transistor and the NMOS transistor is connected to a gate terminal of the high-voltage-side power device.

Semiconductor switching elements connected in parallel as power devices may be used to allow a large current to flow and reduce switching loss. The semiconductor switching elements connected in parallel are usually turned on at the same time, or some of the semiconductor switching elements are turned on depending on the magnitude of the current flowing therein.

In order to selectively drive each semiconductor switching element, the related art uses a driving device provided to each semiconductor switching element, the total number of parts increases and the manufacturing cost thereof increases. This problem also becomes more significant when the signal transmission device has a circuit structure that transmits between circuit blocks operating at different voltages using a set pulse signal and a reset pulse signal (e.g., an on signal and an off signal generated by a pulse generator).

Disclosure of Invention

Therefore, it is desirable to provide a signal transmission device that transmits a first signal having a high voltage level and a low voltage level by using a set pulse signal and a reset pulse signal while suppressing an increase in the total number of components therein, and a driving device equipped with the signal transmission device that drives a semiconductor switching element.

According to one aspect of the present disclosure, a signal transmission device is provided having a pulse generator, an output circuit, and a detector. The pulse generator has a first output terminal and a second output terminal. The pulse generator receives a first signal having a high voltage level or a low voltage level. The pulse generator generates a set pulse signal based on a voltage level change of the first signal from a high voltage level to a low voltage level. The pulse generator transmits a set pulse signal via the first output terminal. The pulse generator generates a reset pulse signal based on a voltage level change from a low voltage level to a high voltage level of the first signal, and transmits the reset pulse signal via the second output terminal. The output circuit has a first input terminal, a second input terminal, and a third output terminal. When the first input terminal receives the set pulse signal transmitted from the pulse generator, the output circuit transmits a first output signal corresponding to a high voltage level of the first signal via the third output terminal. When the second input terminal receives the reset pulse signal transmitted from the pulse generator, the output circuit transmits a second output signal corresponding to the low voltage level of the first signal via the third output terminal. The pulse generator generates and transmits at least one next pulse signal after a predetermined period of time from a time when the set pulse signal or the reset pulse signal is transmitted when the voltage level of the first signal changes. The pulse generator receives a second signal that varies between a plurality of voltage levels and varies in accordance with the second signal. The predetermined time period is counted from the time when the set pulse signal or the reset pulse signal is transmitted to the time when the next pulse signal is transmitted for the first time. The detector detects the state of the second signal based on a predetermined time period from a time when the set pulse signal is received by the first input terminal to a time when the next pulse signal is first received by the first input terminal, or based on a time period from a time when the reset pulse signal is received by the second input terminal to a time when the next pulse signal is first received by the second input terminal.

Therefore, in the signal transmission device having the foregoing structure, when the set pulse signal is received via the first input terminal thereof, the output circuit enters a state of transmitting a high voltage level output signal corresponding to the high voltage level of the first signal. Further, when receiving the reset pulse signal via the second input terminal thereof, the output circuit enters a state of transmitting an output signal of a low voltage level corresponding to the low voltage level of the first signal. That is, in the signal transmission device, the first signal is transmitted to the output circuit via the pulse generator, which generates and transmits the set pulse signal or the reset pulse signal in accordance with a change in the voltage level of the first signal. The output circuit generates and transmits an output signal according to a voltage level of the first signal.

Further, in the signal transmission device having the foregoing structure, the pulse generator transmits the set pulse signal or the reset pulse signal when the voltage level of the first signal changes. In addition, the pulse generator generates and transmits at least one next pulse signal after a predetermined period of time from the time of transmitting the set pulse signal or the reset pulse signal has elapsed.

Further, the pulse generator changes a predetermined time period from a time when the set pulse signal or the reset pulse signal is transmitted to a time when a next pulse signal is first transmitted, based on the second signal having the plurality of voltage states. Therefore, this configuration makes it possible for the detector to correctly detect the voltage state of the second signal based on a time period from when the output circuit receives the set pulse signal via the first input terminal to when the output circuit receives the next set pulse signal via the first input terminal, or a time period from when the output circuit receives the reset pulse signal via the second input terminal to when the output circuit receives the next reset pulse signal via the second input terminal. This configuration makes it possible to reliably transmit the second signal to the detector via the pulse generator.

According to another aspect of the present disclosure, there is provided a driving apparatus having a signal transmission apparatus having a pulse generator, an output circuit, a detector, a switching circuit, and a plurality of drivers. The driving device drives the plurality of semiconductor switching elements.

The pulse generator has a first output terminal and a second output terminal. The pulse generator receives a pulse width modulated signal (PWM signal) having a high voltage level or a low voltage level. The pulse generator generates a set pulse signal based on a voltage level change of the PWM signal from a high voltage level to a low voltage level, and transmits the set pulse signal via the first output terminal. The pulse generator generates a reset pulse signal based on a voltage level change of the PWM signal from a low voltage level to a high voltage level, and transmits the reset pulse signal via the second output terminal. The output circuit has a first input terminal, a second input terminal, and a third output terminal. When the first input terminal receives the set pulse signal transmitted from the pulse generator, the output circuit transmits a first output signal corresponding to a high voltage level of the PWM signal via the third output terminal. When the second input terminal receives the reset pulse signal transmitted from the pulse generator, the output circuit transmits a second output signal corresponding to a low voltage level of the PWM signal via the third output terminal. A plurality of drivers, which are arranged corresponding to the plurality of semiconductor switching elements, respectively, transmit a driving signal to each semiconductor element in accordance with a first output signal and a second output signal transmitted from an output terminal of an output circuit. The switching circuit switches connection between the output terminal of the output circuit and the plurality of drivers. The pulse generator generates and transmits at least one next pulse signal after a predetermined period of time from a time when the set pulse signal or the reset pulse signal is transmitted when the voltage level of the PWM signal changes has elapsed. The pulse generator receives the selector signal. The received selector signal has a plurality of voltage levels respectively corresponding to the plurality of semiconductor switching elements. The pulse generator changes a predetermined time period from a time when the set pulse signal or the reset pulse signal is transmitted to a time when a next pulse signal is first transmitted, based on a state of the received selector signal. The detector detects the state of the selector signal based on a predetermined time period from a time when the set pulse signal is received by the first input terminal to a time when the next pulse signal is first received by the first input terminal, or based on a time period from a time when the reset pulse signal is received by the second input terminal to a time when the next pulse signal is first received by the second input terminal. The detector instructs the switching circuit to connect the output terminal of the output circuit to one of the plurality of drivers based on the detection result thereof so as to drive one of the plurality of semiconductor switching elements.

The drive device is equipped with the signal transmission device having the foregoing structure. The driving device transmits the PWM signal to an output circuit, for example, an RS flip-flop circuit, and to a detector.

The detector instructs the switching circuit to transmit an output signal of the output circuit to a driver for driving the semiconductor switching element as a driving target in accordance with a voltage state of the selector signal. Therefore, the driving device reliably transmits the output signal to the semiconductor switching element as the driving target. In addition, the driving apparatus is provided with a common circuit configuration that generates and transmits a plurality of output signals to a plurality of drivers arranged corresponding to the respective semiconductor switching elements. This makes it possible to suppress an increase in the total number of circuit elements forming the driver device, and to reduce the manufacturing cost of the driver device.

Drawings

Preferred, non-limiting embodiments of the present invention will be described, by way of example, with reference to the accompanying drawings, in which:

fig. 1 is a block diagram illustrating a structure of a driving apparatus equipped with a signal transmission apparatus according to an exemplary embodiment of the present disclosure;

fig. 2 is a timing chart showing waveforms of signals in a section forming the driving apparatus shown in fig. 1;

fig. 3 is a block diagram showing a structure of each of the pulse generator and the phase indicator in the driving apparatus shown in fig. 1;

fig. 4A is a diagram showing signal waveforms explaining the operation of a rising edge detector and a falling edge detector in the pulse generator shown in fig. 3;

FIG. 4B is a signal waveform for the operation of the first continuous pulse generator and the second continuous pulse generator in the pulse generator shown in FIG. 3;

fig. 5 is a diagram showing a partial structure of a modification of the driving apparatus according to the exemplary embodiment shown in fig. 1;

fig. 6 is a timing chart showing signal waveforms in the components forming the driving apparatus shown in fig. 5.

Detailed Description

Hereinafter, various embodiments of the present invention will be described with reference to the accompanying drawings. In the following description of the various embodiments, like reference numerals or numerals designate like or equivalent elements throughout the several views.

Exemplary embodiments

A description will be given of a driving device equipped with a signal transmission device according to an exemplary embodiment of the present disclosure, with reference to fig. 1 to 4A and 4B.

Fig. 1 is a block diagram showing the structure of a drive device 1 equipped with a signal transmission device according to an exemplary embodiment of the present disclosure.

As shown in fig. 1, the driving device 1 has a structure to selectively drive one of the first semiconductor switching element 24a and the second semiconductor switching element 24 b. The first semiconductor switching element 24a and the second semiconductor switching element 24b are connected in parallel.

Fig. 2 is a timing chart showing waveforms of various signals in the components forming the driving apparatus 1 shown in fig. 1. These signals will be described in detail later.

The first semiconductor switching element 24a and the second semiconductor switching element 24b function as a high-voltage side power device to drive an inductive load, such as an induction motor. Preferably, a high-voltage insulated gate bipolar transistor (high-voltage IGBT) and a silicon carbide metal oxide field effect transistor (SiC MOSFET) are used as each of the first semiconductor switching element 24a and the second semiconductor switching element 24b, respectively. Further, an IGBT and a SiCMOSFET having the same characteristics or different characteristics may be used. For example, an IGBT may be used as one of the first semiconductor switching element 24a and the second semiconductor switching element 24b, and a SiC MOSFET may be used as the other semiconductor switching element.

As shown in fig. 1, the driving apparatus 1 has a pulse generator 10, a phase indicator 12, a first level shifter 14a, a second level shifter 14b, an RS flip-flop circuit 16, a phase detector 18, a switching circuit 20, a first driver 22a, and a second driver 22 b. The RS flip-flop circuit 16 corresponds to an output circuit.

In the structure of the drive device 1 shown in fig. 1, the phase indicator 12 receives a selector signal transmitted from an external microcomputer (not shown). The selector signal selects one of the first semiconductor switching element 24a and the second semiconductor switching element 24 b. Through the description of the exemplary embodiments, this selector signal corresponds to the second signal.

The pulse generator 10 receives a pulse width modulation signal (PWM signal) transmitted from an external microcomputer (not shown). The PWM signal selects one of the first semiconductor switching element 24a and the second semiconductor switching element 24b as a driving target. Through the description of the exemplary embodiment, this PWM signal corresponds to the first signal.

The pulse generator 10 may incorporate a phase indicator 12. In this configuration, the pulse generator 10 receives the selector signal (as the second signal) and the PWM signal (as the first signal).

In the structure of the driving device 1 shown in fig. 1, the pulse generator 10 receives a PWM signal. As shown in fig. 2, when the received PWM signal switches from a low level to a high level, the pulse generator 10 generates a set pulse signal at the time of the rising edge. The pulse generator 10 transmits the generated set pulse signal to the first level shifter 14a through the first output terminal of the pulse generator 10. Further, as shown in fig. 2, when the received PWM signal is switched from a high level to a low level, the pulse generator 10 generates a reset pulse signal at the falling edge timing. The pulse generator 10 transmits the generated reset pulse signal to the second level shifter 14b through the second output terminal of the pulse generator 10.

As shown in fig. 2, the pulse generator 10 is configured to generate a next set pulse signal and a next reset pulse signal during a predetermined period after the set pulse signal and the reset pulse signal are output. As shown in fig. 2, the pulse generator 10 generates and transmits the next rest pulse signal and the next reset pulse signal every predetermined period T until the level of the PWM signal is switched.

As shown in fig. 2, the pulse generator 10 is configured to generate and output the set pulse signal and the reset pulse signal a plurality of times (e.g., seven times) until the next set pulse signal and the next reset pulse signal are transmitted for the first time. The reason why the set pulse signal and the reset pulse signal are transmitted a plurality of times is that the state of the RS flip-flop circuit 16 is reliably switched according to the plurality of set pulse signals and reset pulse signals.

An external microcomputer (not shown) transmits a selector signal to the driver device 1 according to the exemplary embodiment to drive one of the first semiconductor switching element 24a and the second semiconductor switching element 24 b. For example, the external microcomputer generates and transmits a selector signal of a low voltage level to select the first semiconductor switching element 24a, and generates and transmits a selector signal of a high voltage level to drive the second semiconductor switching element 24 b.

As shown in fig. 1, the phase indicator 12 receives a selector signal transmitted from an external microcomputer (not shown). The phase commander 12 generates a phase command signal according to the voltage level of the received selector signal. The phase instruction signal indicates a phase (i.e., a time interval) from a start time at which the set pulse signal and the reset pulse signal are generated and transmitted for the first time to a start time at which the next set pulse signal and the next reset pulse signal are generated and transmitted for the first time. The phase indicator 12 transmits the generated phase instruction signal to the pulse generator 10.

As shown in fig. 2, when the received selector signal has a low voltage level, the phase indicator 12 generates a phase command signal instructing the pulse generator 10 to use a phase (i.e., a time interval) corresponding to half T/2 (see fig. 2) of the output period T of the next pulse signal, where the phase (i.e., the time interval) is counted from the start time T1 (see fig. 2) when the set pulse signal is transmitted to the start time T2 (see fig. 2) when the next set pulse signal is transmitted, and the phase (i.e., the time interval) is counted from the start time T3 (see fig. 2) when the reset pulse signal is transmitted to the start time T4 (see fig. 2) when the next reset pulse signal is transmitted. The phase indicator 12 transmits the generated phase instruction signal to the pulse generator 10.

On the other hand, when the received selector signal has a high voltage level, the phase indicator 12 generates a phase command signal instructing the pulse generator 10 to use a phase (i.e., a time interval) corresponding to the entire output period T of the next pulse signal, wherein the phase (i.e., the time interval) is counted from the start time T5 (see fig. 2) when the set pulse signal is transmitted to the start time T6 (see fig. 2) when the next set pulse signal is transmitted, and the phase (i.e., the time interval) is counted from the start time T7 (see fig. 2) when the reset pulse signal is transmitted to the start time T8 (see fig. 2) when the next reset pulse signal is transmitted. The phase indicator 12 transmits the generated phase instruction signal to the pulse generator 10.

In the structure of the drive apparatus 1 shown in fig. 1, the pulse generator 10 is configured to adjust the phase (i.e., time interval) from the start time t1, t5 when the set pulse signal is transmitted to the start time t2, t6 when the next set pulse signal is transmitted, and to adjust the phase (i.e., time interval) from the start time t3, t7 when the reset pulse signal is transmitted to the start time t4, t8 when the next reset pulse signal is transmitted, in accordance with the phase command signal transmitted from the phase indicator 12.

As a result, a time interval indicating a phase from a start time when the set pulse signal is transmitted to a start time when the next set pulse signal is transmitted and indicating a phase from a start time when the reset pulse signal is transmitted to a start time when the next reset pulse signal is transmitted is adjusted according to a voltage level of the selector signal transmitted from an external microcomputer (not shown).

A description will be given of the structure and behavior of each of the pulse generator 10 and the phase indicator 12 with reference to fig. 3.

Fig. 3 is a block diagram showing the structure of each of the pulse generator 10 and the phase indicator 12 in the driving apparatus 1 shown in fig. 1. As shown in fig. 3, the pulse generator 10 has a rising edge detector 30 and a falling edge detector 31.

Fig. 4A is a diagram showing output waveforms of the rising edge detector 30 and the falling edge detector 31 in the pulse generator 10 shown in fig. 1. Fig. 4B is a diagram showing output waveforms of the first continuous pulse generator 44 and the second continuous pulse generator 45 in the pulse generator 10 shown in fig. 1.

As shown in fig. 4A, the rising edge detector 30 generates a set pulse signal when detecting a rising edge of the PWM signal. The falling edge detector 31 generates a reset pulse signal when detecting a falling edge of the PWM signal.

The rising edge detector 30 transmits the set pulse signal to the first level shifter 14a through the or circuit 32. Or circuit 32 is an or gate that is a digital logic gate.

The falling edge detector 31 transmits a reset pulse signal to the second level shifter 14b through the or circuit 33.

Or circuit 32 corresponds to a first output terminal of pulse generator 10, or circuit 33 corresponds to a second output terminal of pulse generator 10.

As shown in fig. 3, the rising edge detector 30 also transmits a set pulse signal to the or circuit 34. Similarly, the falling edge detector 31 also transmits a reset pulse signal to the or circuit 34. The or circuit 34 is an or gate or circuit 34 that is a digital logic gate that transmits a pulse signal upon receiving a set pulse signal or a reset pulse signal. That is, the or circuit 34 transmits the pulse signal to one input terminal of the and circuit 35 and one input terminal of the and circuit 36 in the phase indicator 12. Each of the and circuit 35 and the and circuit 36 is an and gate that is a digital logic gate.

As shown in fig. 3, the other input terminal of the and circuit 35 receives a selector signal. The other input terminal 36a of the and circuit 36 is an inverting input terminal. The inverting input terminal 36a of the and circuit 36 receives the selector signal. Therefore, when the selector signal has a high voltage level (high), the pulse signal transmitted from the or circuit 34 passes through the and circuit 35. On the other hand, when the selector signal has a low voltage level (low), the pulse signal transmitted from the or circuit 34 flows through the and circuit 36.

When the pulse signal transmitted from the or circuit 34 flows through the and circuit 35, the T delay circuit 37 receives the pulse signal transmitted from the and circuit 35. When the period T elapses after the pulse signal is received, the T delay circuit 37 starts transmitting the T-delayed pulse signal.

On the other hand, when the pulse signal transmitted from the or circuit 34 has passed through the and circuit 36, the T/2 delay circuit 38 receives the pulse signal transmitted from the and circuit 36. When the period T/2 (half of the period T) elapses after the pulse signal is received, the T/2 delay circuit 38 starts transmission of the T/2 delayed pulse signal.

The T delayed pulse signal transmitted from the T delay circuit 37 and the T/2 delayed pulse signal transmitted from the T/2 delay circuit 38 correspond to the phase command signal.

The or circuit 39 receives the T delayed pulse signal transmitted from the T delay circuit 37 and the T/2 delayed pulse signal transmitted from the T/2 delay circuit 38. Or circuit 39 is also an or gate that is a digital logic gate.

When receiving the delayed pulse signal transmitted from one of the T delay circuit 37 and the T/2 delay circuit 38, the or circuit 39 transmits the received delayed pulse signal to one input terminal of the and circuit 40 and one input terminal of the and circuit 41. Each of the and circuit 40 and the and circuit 41 is an and gate that is a digital logic gate.

As shown in fig. 3, the other input terminal of the and circuit 40 receives the PWM signal. The other input terminal 41a of the and circuit 41 is an inverting input terminal. The inverting input terminal 41a of the and circuit 41 also receives the PWM signal.

Therefore, when receiving the PWM signal of the high voltage level (high), the and circuit 40 allows the delayed pulse signal transmitted from the or circuit 39 to be transmitted to the first flip-flop circuit 42 via the and circuit 40.

On the other hand, when receiving the PWM signal of the low voltage level (low), the and circuit 41 allows the delayed pulse signal transmitted from the or circuit 39 to be transmitted to the first flip-flop circuit 42 via the and circuit 40.

As shown in fig. 3, each of the first flip-flop circuit 42 and the second flip-flop circuit 43 has a set input terminal S, a reset input terminal R, and an output terminal Q.

The set input terminal S of the first flip-flop circuit 42 receives the delayed pulse signal transmitted from the and circuit 40. The set input terminal S of the second flip-flop circuit 43 receives the delayed pulse signal transmitted from the and circuit 41.

When receiving the delayed pulse signal via the set input terminal S, each of the first flip-flop circuit 42 and the second flip-flop circuit 43 transmits a high-voltage output signal (high) via its output terminal Q.

When receiving the pulse signal via the reset input terminal R, each of the first flip-flop circuit 42 and the second flip-flop circuit 43 transmits a low-voltage output signal (low) via its output terminal Q.

The reset input terminal R of the first flip-flop circuit 42 receives the output signal of the falling edge detector 31. The reset input terminal R of the second flip-flop circuit 43 receives the output signal of the rising edge detector 30.

As shown in fig. 3, the first continuous pulse generator 44 is connected to the output terminal Q of the first flip-flop circuit 42, and the second continuous pulse generator 45 is connected to the output terminal Q of the second flip-flop circuit 43.

As shown in fig. 4A, each of the first continuous pulse generator 44 and the second continuous pulse generator 45 continuously generates a pulse signal at each interval of the period T during a period in which the output terminals Q of the first flip-flop circuit 42 and the second flip-flop circuit 43 transmit a high-level output signal.

When the output signal is switched from the high voltage level to the low voltage level via the output terminal Q, each of the first continuous pulse generator 44 and the second continuous pulse generator 45 stops generating and transmitting the pulse signal.

When receiving the output signal transmitted from the first continuous pulse generator 44, the or circuit 32 generates a next set pulse signal and transmits the next set pulse signal to the first level shifter 14 a.

On the other hand, when receiving the output signal transmitted from the second continuous pulse generator 45, the or circuit 33 generates a next set pulse signal and transmits the next set pulse signal to the second level shifter 14 b.

In the driver device 1 according to the exemplary embodiment in which the pulse generator 10 and the phase indicator 12 have the aforementioned structures, when the rising edge detector 30 detects the rising edge of the PWM signal and transmits the set pulse signal, the first continuous pulse generator 44 continuously generates a pulse signal during the period T and transmits the pulse signal as the next set pulse signal. The first continuous pulse generator 44 transmits the next set pulse signal to the first level shifter 14a through the or circuit 32.

The phase representing the time interval from the start time when the set pulse signal is first generated and transmitted to the start time when the next set pulse signal is first generated and transmitted is changed, i.e., changed to one of the period T and the half period T/2, according to the delayed pulse signal transmitted from the phase indicator 12.

When the falling edge detector 31 transmits the reset pulse signal due to the detection of the falling edge of the PWM signal, the first flip-flop circuit 42 is reset. Therefore, when the first continuous pulse generator 44 receives the low-voltage output signal transmitted from the first flip-flop circuit 42, the first continuous pulse generator 44 stops continuously transmitting the set pulse signal to the first level shifter 14a via the or circuit 32.

In addition, when the falling edge detector 31 transmits the reset pulse signal due to the detection of the falling edge of the PWM signal, the second continuous pulse generator 45 continuously generates a pulse signal via the or circuit 33 and transmits the pulse signal to the second level shifter 14b as the next reset pulse signal.

The phase, which represents the time interval from the start time when the reset pulse signal is first generated and transmitted to the start time when the next reset pulse signal is first generated and transmitted, changes according to the delayed pulse signal transmitted from the phase indicator 12.

When the rising edge detector 30 transmits the set pulse signal due to the detection of the rising edge of the PWM signal, the second flip-flop circuit 43 is reset. Therefore, when the second continuous pulse generator 45 receives the low-voltage output signal transmitted from the second flip-flop circuit 43, the second continuous pulse generator 45 stops continuously transmitting the reset pulse signal to the second level shifter 14b via the or circuit 33.

The phase indicator 12 transmits the delayed pulse signal to the and circuit 40 and the and circuit 41 in the pulse generator 10 as a phase command signal corresponding to the voltage level of the selector signal. The pulse generator 10 adjusts a phase indicating a time interval from a start time of first generating and transmitting the set pulse signal to a start time of first generating and transmitting the next set pulse signal in accordance with the delayed pulse signal transmitted from the phase indicator 12 in a phase range between a phase T indicating a time interval from the start time of first generating and transmitting the set pulse signal to the start time of first generating and transmitting the next set pulse signal and a phase indicating a time interval from the start time of first generating and transmitting the reset pulse signal to the start time of first generating and transmitting the next reset pulse signal.

That is, when the selector signal has a high voltage level (high), the pulse generator 10 adjusts the phase corresponding to the period T. On the other hand, when the selector signal has a low voltage level (low), the pulse generator 10 adjusts the phase corresponding to the half period T/2.

A description will now be given of the structure of another component in the drive apparatus 1 according to the exemplary embodiment, with reference to fig. 1 and 2.

Each of the first and second level shifters 14a and 14b transfers a set pulse signal, a reset pulse signal, a next set pulse signal, and a next reset pulse signal between circuit blocks operating at different power supply voltages. That is, the pulse generator 10 and the phase indicator 12 belong to a circuit block that operates at a relatively low power supply voltage. On the other hand, the RS flip-flop circuit 16, the phase detector 18, the switching circuit 20, the first driver 22a, and the second driver 22b belong to a circuit block that operates at a relatively high power supply voltage.

Each of the first level shifter 14a and the second level shifter 14b is equipped with a level shifter transistor and an inverter. The gate terminal of the level shifter transistor in each of the first and second level shifters 14a and 14b receives the set pulse signal, the reset pulse signal, the next set pulse signal, and the next reset pulse signal transmitted from the pulse generator 10.

A gate terminal of the level shifter transistor in each of the first and second level shifters 14a and 14b receives a high voltage, and is connected to a set input terminal S (as a first input terminal) of the RS flip-flop circuit 16 and a reset input terminal R (as a second input terminal) of the RS flip-flop circuit 16 via an inverter (not shown).

Therefore, when the level shifter transistor in the first level shifter 14a is turned on by the voltage level of the set pulse signal, the set input terminal S of the RS flip-flop circuit 16 receives the set pulse signal having a pulse shape. As shown in fig. 2, this makes it possible to allow the output terminal Q of the RS flip-flop circuit 16 to transmit a high-voltage output signal (high) of a high voltage level corresponding to the PWM signal.

Since the pulse generator 10 transmits the next set pulse signal after transmitting the set pulse signal, the set input terminal S of the RS flip-flop circuit 16 receives the next set pulse signal. However, since the RS flip-flop circuit 16 has already entered a state of transmitting a high-voltage output signal via its output terminal Q, receiving the next set pulse signal does not affect the state of the RS flip-flop circuit 16. However, when the RS flip-flop circuit 16 has entered a state of not transmitting a high-voltage output signal, receiving the next set pulse signal turns on the flip-flop circuit 16 to transmit the high-voltage output signal via the output terminal Q.

On the other hand, when the level shifter transistor in the second level shifter 14b is turned on by the voltage level of the reset pulse signal, the reset input terminal R of the RS flip-flop circuit 16 receives the pulse signal having a pulse shape. As shown in fig. 2, this makes it possible to allow the output terminal Q of the RS flip-flop circuit 16 to transmit a low-voltage output signal (low) corresponding to the low-voltage level of the PWM signal.

Similarly to the previously described next set pulse signal, since the pulse generator 10 transmits the next reset pulse signal after transmitting the reset pulse signal, the reset input terminal R of the RS flip-flop circuit 16 receives the next reset pulse signal. However, since the RS flip-flop circuit 16 has already entered a state in which a low-voltage output signal is transmitted via its output terminal Q, receiving the next reset pulse signal does not affect the state of the RS flip-flop circuit 16. However, when the RS flip-flop circuit 16 enters a state where a low-voltage output signal is not transmitted, receiving the next set pulse signal turns on the flip-flop circuit 16 to transmit a high-voltage output signal via the output terminal Q.

As described previously, the RS flip-flop circuit 16 transmits the output signal approximately in synchronization with the change in the voltage level of the PWM signal received by the drive device 1.

It is acceptable that the voltage level of the PWM signal received by the drive device 1 is equal to the voltage level or the inverted voltage level of the output signal of the RS flip-flop circuit 16.

As shown in fig. 1, the phase detector 18 also receives an output signal of the set input terminal S transmitted from the first level shifter 14a to the RS flip-flop circuit 16 and an output signal of the reset input signal R transmitted from the second level shifter 14b to the second level shifter 14 b.

When the set pulse signal and the next set pulse signal are received, the phase detector 18 detects whether the phase, which represents the time interval from the start time when the set pulse signal is first generated and transmitted to the start time when the next set pulse signal is first generated and transmitted, corresponds to the period T of the next set pulse signal or the half period T/2 of the next set pulse signal, as described above.

Further, when receiving the reset pulse signal and the next reset pulse signal, the phase detector 18 detects whether or not the phase, which represents the time interval from the start time when the set reset pulse signal is first generated and transmitted to the start time when the next reset pulse signal is first generated and transmitted as described above, corresponds to the period T of the next set pulse signal or the half period T/2 of the next set pulse signal.

The phase detector 18 generates a switching signal to switch the connection state of the switching circuit 20 so that one of the first semiconductor switching element 24a and the second semiconductor switching element 24b, which is selected based on the detection result of the phase detector 18, receives the output signal transmitted from the RS flip-flop circuit 16. The phase detector 18 has a latch circuit to hold the detection result.

Upon receiving the set pulse signal and the reset pulse signal, phase detector 18 generates a switching signal and transmits the switching to switching circuit 20.

For example, in the structure and behavior of the driving device 1 shown in fig. 1 and 2, the phase detector 18 transmits the switching signal to the switching circuit 20 so that the second driver 22b receives the output signal transmitted from the RS flip-flop circuit 16 at the timing when the phase detector 18 receives the next set pulse signal or the next reset pulse signal after the phase of the time interval from the start time of the first generation and transmission of the set pulse signal and the reset pulse signal to the start time of the first generation and transmission of the next set pulse signal and the next reset pulse signal becomes corresponding to the period T of the next pulse signal (i.e., the next set pulse signal or the next reset pulse signal). This control makes it possible to perform PWM driving of the second semiconductor switching element 24b in accordance with the output signal of the RS flip-flop circuit 16.

On the other hand, the phase detector 18 transmits the switching signal to the switching circuit 20 so that the first driver 22a receives the output signal transmitted from the RS flip-flop circuit 16 at the timing when the phase detector 18 receives the next set pulse signal or the next reset pulse signal after the phase of the time interval from the start time of the first generation and transmission of the set pulse signal and the reset pulse signal to the start time of the first generation and transmission of the next set pulse signal and the next reset pulse signal becomes corresponding to the half period T/2 of the next pulse signal. This control makes it possible to perform PWM driving of the first semiconductor switching element 24a based on the output signal of the RS flip-flop circuit 16.

The switching circuit 20 switches transmission of the output signal of the RS flip-flop circuit 16 between the first driver 22a and the second driver 22 b.

For example, the first driver 22a has a PMOS transistor and an NMOS transistor. The PMOS transistor is a driving element arranged between the high voltage side of the power supply and the gate terminal of the first semiconductor switching element 24 a. The NMOS transistor is a driving element arranged between the low voltage side of the power supply and the gate terminal of the first semiconductor switching element 24 a.

The RS flip-flop circuit 16 transmits an output signal of a high voltage level (high) to the first driver 22a via the switching circuit 20. When receiving the output signal of the high voltage level (high) transmitted from the RS flip-flop circuit 16, the PMOS transistor in the first driver 22a is turned on, and the NMOS transistor is turned off in the first driver 22 a. This state of the first driver 22a supplies a high voltage to the gate terminal of the first semiconductor switching element 24 a. Thereby, the first semiconductor switching element 24a is turned on.

On the other hand, the RS flip-flop circuit 16 transmits an output signal of a low voltage level (low) to the first driver 22a via the switching circuit 20. When receiving the output signal of the low voltage level (low) transmitted from the RS flip-flop circuit 16, the PMOS transistor in the first driver 22a is turned off, and the NMOS transistor is turned on in the first driver 22 a. This state of the first driver 22a supplies a low voltage to the gate terminal of the first semiconductor switching element 24 a. Thereby, the first semiconductor switching element 24a is turned off. This state of the first driver 22a supplies a low voltage to the gate terminal of the first semiconductor switching element 24 a. Thereby, the first semiconductor switching element 24a is turned off. As described above, the first semiconductor switching element 24a is turned on/off based on the output signal of the RS flip-flop circuit 16.

Since the second driver 22b has the same configuration as the first driver 22a, when the phase detector 18 switches the output signal of the RS flip-flop circuit 16 to the second driver 22b, the second semiconductor switching element 24b is determined based on the output signal of the RS flip-flop circuit 16.

Now, technical features and effects of the driving apparatus 1 according to the exemplary embodiment will be described.

In the structure of the driving device 1 according to the foregoing exemplary embodiment, when receiving the set pulse signal via the set input terminal S thereof, the RS flip-flop circuit 16 transmits the high voltage level of the output signal corresponding to the high voltage level of the PWM signal. On the other hand, when receiving the reset pulse signal via its reset input terminal R, the RS flip-flop circuit 16 transmits a low voltage level of the output signal corresponding to the low voltage level of the PWM signal. That is, after the driving apparatus 1 receives the PWM signal, the PWM signal is transmitted to the RS flip-flop circuit 16 via the pulse generator 10, the first level shifter 14a, and the second level shifter 14 b. The RS flip-flop circuit 16 changes its output signal in synchronization with the level change of the PWM signal. That is, the RS flip-flop circuit 16 transmits an output signal corresponding to the voltage level of the received PWM signal.

In the structure of the driving device 1 according to the foregoing exemplary embodiment, the pulse generator 10 transmits the set pulse signal or the reset pulse signal according to the switching time of the voltage level of the received PWM signal. Further, the pulse generator 10 transmits the next set pulse signal or the next reset pulse signal. In this case, the pulse generator 10 adjusts, i.e., changes, the predetermined time period, which represents the length of time from the start time of first transmitting the set pulse signal or the reset pulse signal to the start time of first transmitting the next set pulse signal or the next reset pulse signal, according to the selection signal that changes the high voltage level (high level) or the low voltage level (low level).

In the structure of the driving device 1 according to the foregoing exemplary embodiment, when the selector signal has a high voltage level (high), the pulse generator 10 first transmits the next pulse signal after a lapse of a time period corresponding to the period T of the next pulse signal from the time when the set pulse signal or the reset pulse signal is transmitted.

Further, when the selector signal has a low voltage level (low), the pulse generator 10 first transmits the next pulse signal after a time period has elapsed, wherein the time period corresponds to a half period T/2 of the next pulse signal from the time when the set pulse signal or the reset pulse signal is transmitted.

Therefore, this structure allows the phase detector 18 to detect the state (high voltage level or low voltage level) of the selector signal from the time when the set pulse signal is received from the set input terminal S of the RS flip-flop circuit 16 to the time when the next set pulse signal is first received, or from the time when the reset pulse signal is received from the reset input terminal R of the RS flip-flop circuit 16 to the time when the next reset pulse signal is first received. This structure makes it possible to transmit the selector signal to the phase detector 18 via the pulse generator 10, the first level shifter 14a, and the second level shifter 14 b.

As shown in fig. 2, the phase detector 18 cannot detect a change in the voltage level of the selector signal until the set pulse signal and the first next set pulse signal are received or until the reset pulse signal and the first next reset pulse signal are received.

In other words, a delayed time period occurs that depends on the timing of the change in the voltage level of the PWM signal until the phase detector 18 receives the selector signal.

Since the driving device 1 according to the exemplary embodiment switches the first semiconductor switching element 24a and the second semiconductor switching element 24b using the selector signal, a transmission delay may occur.

As described in detail previously, the driving device 1 according to the exemplary embodiment reliably transmits the selector signal to the switching circuit 20 to select and drive the first semiconductor switching element 24a and the second semiconductor switching element 24b according to the time period counted from the time of transmitting the set pulse signal or the reset pulse signal to the time of first transmitting the next set pulse signal or the next reset pulse signal. This control allows the circuit to have the same structure so as to transmit the output signal to the first driver 22a and the second driver 22b to drive the first semiconductor switching element 24a and the second semiconductor switching element 24 b. In other words, the improved structure of the driving device 1 can avoid the use of different circuit structures for transmitting control signals to each of the first driver 22a and the second driver 22b in order to drive the first semiconductor switching element 24a and the second semiconductor switching element 24 b. This structure can suppress an increase in the total number of circuit components forming the drive device 1 and avoid an increase in the manufacturing cost of the drive device 1.

Other modifications

A description will be given of various modifications of the drive apparatus 1 according to the exemplary embodiment with reference to fig. 5 and 6.

Fig. 5 is a diagram showing a partial structure of a modification of the display driving device 1 according to the exemplary embodiment shown in fig. 1. Fig. 6 is a timing chart showing signal waveforms in components constituting a modification of the driving apparatus shown in fig. 5.

As described previously, the driving device 1 according to the exemplary embodiment has a structure of selecting one of the first semiconductor switching element 24a and the second semiconductor switching element 24 b. However, the inventive concept is not limited by the exemplary embodiments. For example, as shown in fig. 5 and 6, one of the switching elements 24a, for example, the first semiconductor switching element 24a may be always turned on/off according to the voltage level of the PWM signal, and the other switching element, for example, the second semiconductor switching element 24b may be turned on/off according to the combination of the selector signal and the PWM signal.

In the modification of the driving apparatus shown in fig. 5, the first driver 22a is directly connected to the output terminal Q of the RS flip-flop circuit 16 without via the switching circuit 20. That is, the first driver 22a always drives, i.e., turns on/off, the first semiconductor switching element 24a in accordance with the output signal of the RS flip-flop circuit 16, and it switches in synchronization with the voltage level of the PWM signal.

On the other hand, the second driver 22b is connected to the output terminal Q of the RS flip-flop circuit 16 via the switching circuit 20. The switching state of the switching circuit 20 is switched based on the switching signal transmitted from the phase detector 18. For example, when the phase detector 18 transmits a selector signal of a high voltage level (high), the switching circuit 20 is turned on, and the output terminal Q of the RS flip-flop circuit 16 is connected to the second driver 22b via the switching circuit 20. On the other hand, when the phase detector 18 transmits the selector signal of the low voltage level (low), the switching circuit 20 is not turned on, and the output terminal Q of the RS flip-flop circuit 16 is not connected to the second driver 22b via the switching circuit 20. The second driver 22b does not drive the second semiconductor switching element 24 b.

Further, the driving device 1 may have a structural variation in which the first semiconductor switching element 24a and the second semiconductor switching element 24b are simultaneously driven in addition to a structure of selectively driving one of the first semiconductor switching element 24a and the second semiconductor switching element 24 b. This structure uses selector signals of three voltage states and uses phases (i.e., time intervals) having three states, for example, T/3, 2T/3, and T, where the phase represents a time period from a start time of transmitting a set pulse signal or a reset pulse signal to a time of first transmitting a next set pulse signal or a next reset pulse signal. In addition, the switching circuit is configured to switch the three switch states. In the first switching state, the output signal of the RS flip-flop circuit 16 is transmitted to the first drive circuit 22a so as to drive the first semiconductor switching element 24 a. In the second switching state, the output signal of the RS flip-flop circuit 16 is transmitted to the second drive circuit 22b so as to drive the second semiconductor switching element 24 b. In the third switching state, the output signal of the RS flip-flop circuit 16 is transmitted to the first drive circuit 22a and the second drive circuit 22b so as to drive the first semiconductor switching element 24a and the second semiconductor switching element 24b at the same time. The phase detector 18 detects to which phase (i.e., one of T/3, 2T/3, T) the phase corresponds, wherein the phase represents a time period from a start time of transmitting the set pulse signal or the reset pulse signal to a time of first transmitting the next set pulse signal or the next reset pulse signal. The phase detector 18 selects one of the first switching state, the second switching state, and the third switching state according to the detection result.

The driving device may also have a structure in which three semiconductor switching elements are arranged in parallel, one of them is selectively driven, and a combination thereof is simultaneously driven.

In the structure of the drive device 1 described above, the pulse generator 10 changes the phase from the time when the set pulse signal or the reset pulse signal is first transmitted to the time when the next set pulse signal or the next reset pulse signal is first transmitted, in accordance with the phase instruction signal transmitted from the phase indicator 12. Further, the drive device 1 uses a constant value of each period T of the next pulse signal, that is, a period of the next set pulse signal and a period of the next reset pulse signal, regardless of the voltage state of the selector signal.

However, the concept of the present invention is not limited thereto. For example, it is acceptable that the pulse generator 10 generates and transmits the next pulse signal as long as the pulse generator 10 changes the phase, i.e., the time interval from the time when the set pulse signal or the reset pulse signal is first transmitted to the time when the next set pulse signal or the next reset pulse signal is first transmitted.

For example, the pulse generator 10 may generate a plurality of pulse signals having different frequencies corresponding to each state of the selector signal, and may vary a time period from a time when the set pulse signal or the reset pulse signal is first transmitted to a time when the next set pulse signal or the next reset pulse signal is first transmitted according to the generated pulse signals having different frequencies.

The pulse generator 10 may also generate and transmit only one pulse signal as the next pulse signal.

In the structure of the driving device according to the foregoing exemplary embodiment, the signal transmission device is incorporated in the driving device, and the signal transmission device generates and transmits the PWM signal and the selector signal to the circuit blocks such as the first semiconductor switching element 24a and the second semiconductor switching element 24b driven by different power supply voltages.

However, the concept of the present invention is not limited thereto. For example, the signal transmission device may generate and transmit control signals for other controls in addition to transmitting the PWM signal and the selector signal. That is, in a structure in which the pulse generator 10 generates and transmits a first signal between circuit blocks having a high voltage level or a low voltage level and used for driving by different power supply voltages to the circuit blocks via the RS flip-flop circuit 16, the pulse generator 10 may transmit a second signal varying in a plurality of voltage levels according to a time interval calculated from a time when a set pulse signal or a reset pulse signal is first transmitted to a time when a next set pulse signal or a next reset pulse signal is first transmitted

While specific embodiments of the invention have been described in detail, it will be appreciated by those skilled in the art that various modifications and alternatives to those details could be developed in light of the overall teachings of the disclosure. Accordingly, the particular arrangements disclosed are meant to be illustrative only and not limiting as to the scope of the invention which is to be given the full breadth of the claims appended and any and all equivalents thereof.