阅读说明：本技术 电子装置和半导体封装结构的制造方法 (Electronic device and manufacturing method of semiconductor packaging structure ) 是由 方绪南 陈建庆 于 2019-06-04 设计创作，主要内容包括：一种电子装置包括绝缘层、金属层和至少一个电连接元件。所述绝缘层具有顶面和与所述顶面相对的底面,并且界定开口,所述开口延伸于所述顶面和所述底面之间。所述金属层设置于所述绝缘层的所述开口中,并且具有顶面和与所述顶面相对的底面。所述金属层的所述底面与所述绝缘层的所述底面实质上共平面。所述电连接元件通过晶种层附接到所述金属层的所述底面。(electronic devices include an insulating layer having a top surface and a bottom surface opposite the top surface and defining an opening extending between the top surface and the bottom surface, a metal layer disposed in the opening of the insulating layer and having a top surface and a bottom surface opposite the top surface.)

The manufacturing method of the semiconductor packaging structure of kinds includes:

(a) providing a carrier having an th surface and defining a plurality of openings on the th surface;

(b) forming a conductive material in the opening of the carrier;

(c) forming a wiring structure on the carrier and the conductive material;

(d) electrically connecting at least semiconductor dies to the wiring structure;

(e) forming a package to cover the at least semiconductor dies, and

(f) removing the carrier.

2. The method of claim 1, wherein after step (a), the method further comprises:

(a1) forming a release layer in the opening and on the th surface of the carrier.

3. The method of claim 2, wherein after step (f), the method further comprises:

(g) and removing the release layer.

4. The method of claim 1, wherein in step (b), the conductive material is formed by printing or plating.

5. The method of claim 4, wherein after step (a), the method further comprises:

(a1) forming a seed layer in the opening and on the th surface of the carrier.

6. The method of claim 5, wherein after step (f), the method further comprises:

(g) removing the seed layer.

7. The method of claim 4, wherein in step (b), the conductive material is formed by printing; and after step (b), the method further comprises:

(b1) forming a seed layer on the conductive material and on the th surface of the carrier.

8. The method of claim 7, wherein step (c) comprises:

(c1) forming an insulating layer on the seed layer;

(c2) removing portions of the insulating layer to form a plurality of openings, the openings exposing portions of the seed layer; and

(c3) forming a metal layer in the opening of the insulating layer and on the exposed portion of the seed layer.

9. The method of claim 7, wherein after step (f), the method further comprises:

(g) removing portions of the seed layer not covered by the conductive material.

10. The method of claim 1, wherein in step (a), the gaps between the openings of the carrier are less than 50 μ ι η and the aspect ratio of the openings is greater than or equal to 1.

11. The method of claim 1, wherein after step (b), the method further comprises:

(b1) disposing a solid core sphere in the conductive material in the opening of the carrier.

12. The method of claim 1, wherein after step (f), the method further comprises:

(g) and reflowing the conductive material.

An electronic device of , comprising:

an insulating layer having a top surface and a bottom surface opposite the top surface and defining an opening extending between the top surface and the bottom surface;

a metal layer disposed in the opening of the insulating layer and having a top surface and a bottom surface opposite the top surface, wherein the bottom surface of the metal layer is substantially coplanar with the bottom surface of the insulating layer; and

at least electrical connection elements attached to the bottom surface of the metal layer by a seed layer.

14. The electronic device of claim 13, wherein the seed layer is embossed on the bottom surface of the metal layer.

15. The electronic device of claim 13, wherein the electrical connection elements are raised above a bottom surface of the seed layer and the bottom surface of the insulating layer.

16. The electronic device of claim 13, wherein a material of the metal layer comprises copper, a material of the electrical connection element comprises a silver-tin alloy, and a material of the seed layer comprises a titanium-tungsten alloy.

17. The electronic device of claim 13, wherein the electrical connection element is spherical, rectangular cylindrical, or cylindrical.

18, an electronic device, comprising:

an insulating layer having a top surface and a bottom surface opposite the top surface and defining an opening extending between the top surface and the bottom surface;

a metal layer disposed in the opening of the insulating layer; and

at least electrical connection elements attached to the metal layer and having a top surface and a bottom surface opposite the top surface, wherein the top surfaces of the electrical connection elements are substantially coplanar with the bottom surface of the insulating layer.

19. The electronic device of claim 18, wherein the metal layer has a top surface and a bottom surface opposite the top surface, and the electrical connection elements are raised to the bottom surface of the metal layer and the bottom surface of the insulating layer.

20. The electronic device of claim 18, wherein a material of the metal layer comprises copper and a material of the electrical connection element comprises a silver-tin alloy.

21. The electronic device of claim 18, further comprising a barrier layer interposed between the electrical connection element and the metal layer.

Technical Field

The present disclosure relates to an electronic device and a method of manufacturing a semiconductor package structure, and to an electronic device including an electrical connection element attached to a metal layer, and a method of manufacturing a semiconductor package structure including the electronic device.

Background

Semiconductor chips can be integrated with a large number of electronic components to achieve powerful electrical performance. Accordingly, the semiconductor chip is provided with a large number of input/output (I/O) connections. In order to keep a small semiconductor package while realizing a semiconductor chip provided with a large number of I/O connections, the bond pad density of the package substrate for external connection may be correspondingly increased. However, in such an embodiment, how to reliably and accurately implant the solder balls on the bonding pads of the package substrate is a concern. The ball placement process (molding process) is performed after the molding process (molding process) and before the singulation process (singulation process). However, after the molding process, the semi-finished product may warp and shrink, and especially when the semi-finished product has a large size, the difficulty of the solder ball implanting process may increase.

Disclosure of Invention

In embodiments, a electronic device includes an insulating layer having a top surface and a bottom surface opposite the top surface and defining an opening extending between the top surface and the bottom surface, a metal layer disposed in the opening of the insulating layer and having a top surface and a bottom surface opposite the top surface, the bottom surface of the metal layer being substantially coplanar with the bottom surface of the insulating layer, and at least electrical connection elements attached to the bottom surface of the metal layer by a seed layer.

In embodiments, a electronic device includes an insulating layer having a top surface and a bottom surface opposite the top surface and defining an opening extending between the top surface and the bottom surface, a metal layer disposed in the opening of the insulating layer, and at least electrical connection elements attached to the metal layer and having a top surface and a bottom surface opposite the top surface.

In embodiments, methods of fabricating semiconductor package structures include (a) providing a carrier having a th surface and defining a plurality of openings on the th surface, (b) forming a conductive material in the openings of the carrier, (c) forming a routing structure on the carrier and the conductive material, (d) electrically connecting at least semiconductor dies to the routing structure, (e) forming a package body to cover the at least semiconductor dies, and (f) removing the carrier.

Drawings

Various aspects of the embodiments of the disclosure are readily understood from the following detailed description when read in conjunction with the accompanying drawings it is noted that the various structures may not be drawn to scale and that the dimensions of the various structures may be arbitrarily increased or decreased for clarity of discussion.

Fig. 1 shows a cross-sectional view of an electronic device of embodiments of the present disclosure.

Fig. 2 shows an enlarged view of region "a" in fig. 1.

Fig. 3 shows a cross-sectional view of an electronic device of embodiments of the present disclosure.

Fig. 4 shows a cross-sectional view of an electronic device of embodiments of the present disclosure.

Fig. 5 shows a cross-sectional view of an electronic device of embodiments of the present disclosure.

Fig. 6 shows an enlarged view of the region "B" in fig. 5.

Fig. 7 shows a cross-sectional view of an electronic device of embodiments of the present disclosure.

Fig. 8 shows a cross-sectional view of an electronic device of embodiments of the present disclosure.

Fig. 9 shows a cross-sectional view of an electronic device of embodiments of the present disclosure.

Fig. 10 shows an enlarged view of region "C" in fig. 9.

Fig. 11 shows a cross-sectional view of an electronic device of embodiments of the present disclosure.

Fig. 12 shows a cross-sectional view of an electronic device of embodiments of the present disclosure.

Fig. 13 shows a cross-sectional view of an electronic device of embodiments of the present disclosure.

Fig. 14 shows a cross-sectional view of an electronic device of embodiments of the present disclosure.

Fig. 15 shows a cross-sectional view of an electronic device of embodiments of the present disclosure.

Fig. 16 shows a cross-sectional view of an assembly of embodiments of the present disclosure.

Fig. 17 shows or stages of embodiments of a method of manufacturing an electronic device of the present disclosure.

Fig. 18 shows or stages of embodiments of a method of manufacturing an electronic device of the present disclosure.

Fig. 19 shows or stages of embodiments of a method of manufacturing an electronic device of the present disclosure.

Fig. 20 shows or stages of embodiments of a method of manufacturing an electronic device of the present disclosure.

Fig. 21 shows or stages of embodiments of a method of manufacturing an electronic device of the present disclosure.

Fig. 22 shows or stages of embodiments of a method of manufacturing an electronic device of the present disclosure.

Fig. 23 shows or stages of embodiments of a method of manufacturing an electronic device of the present disclosure.

Fig. 24 shows or stages of embodiments of a method of manufacturing an electronic device of the present disclosure.

Fig. 25 shows or stages of embodiments of a method of manufacturing an electronic device of the present disclosure.

Fig. 26 shows or stages of embodiments of a method of manufacturing an electronic device of the present disclosure.

Fig. 27 shows or stages of embodiments of a method of manufacturing an electronic device of the present disclosure.

Fig. 28 shows or stages of embodiments of a method of manufacturing an electronic device of the present disclosure.

Fig. 29 shows or stages of embodiments of a method of manufacturing an electronic device of the present disclosure.

Fig. 30 shows or stages of embodiments of a method of manufacturing an electronic device of the present disclosure.

Fig. 31 shows or stages of embodiments of a method of manufacturing an electronic device of the present disclosure.

Fig. 32 shows or stages of embodiments of a method of manufacturing an electronic device of the present disclosure.

Fig. 33 shows or stages of embodiments of a method of manufacturing an electronic device of the present disclosure.

Fig. 34 shows or stages of embodiments of a method of manufacturing an electronic device of the present disclosure.

Fig. 35 shows or stages of embodiments of a method of manufacturing an electronic device of the present disclosure.

Fig. 36 shows or stages of embodiments of a method of manufacturing an electronic device of the present disclosure.

Fig. 37 shows or stages of embodiments of a method of manufacturing an electronic device of the present disclosure.

Fig. 38 shows or stages of embodiments of a method of manufacturing an electronic device of the present disclosure.

Fig. 39 shows or stages of embodiments of a method of manufacturing an electronic device of the present disclosure.

Fig. 40 shows or stages of embodiments of a method of manufacturing an electronic device of the present disclosure.

Fig. 41 shows or stages of embodiments of a method of manufacturing an electronic device of the present disclosure.

Fig. 42 shows or stages of embodiments of a method of manufacturing an electronic device of the present disclosure.

Fig. 43 shows or stages of embodiments of a method of manufacturing an electronic device of the present disclosure.

Fig. 44 shows or stages of embodiments of a method of manufacturing an electronic device of the present disclosure.

Fig. 45 shows or stages of embodiments of a method of manufacturing an electronic device of the present disclosure.

Fig. 46 shows or stages of embodiments of a method of manufacturing an electronic device of the present disclosure.

Fig. 47 shows or stages of embodiments of a method of manufacturing an electronic device of the present disclosure.

Fig. 48 shows or stages of embodiments of a method of manufacturing an electronic device of the present disclosure.

Fig. 49 shows or stages of embodiments of a method of manufacturing an electronic device of the present disclosure.

Fig. 50 shows or stages of embodiments of a method of manufacturing an electronic device of the present disclosure.

Fig. 51 shows or stages of embodiments of a method of manufacturing an electronic device of the present disclosure.

Fig. 52 shows or stages of embodiments of a method of manufacturing an electronic device of the present disclosure.

Fig. 53 shows or stages of embodiments of a method of manufacturing an electronic device of the present disclosure.

Fig. 54 shows or stages of embodiments of a method of manufacturing an electronic device of the present disclosure.

Fig. 55 shows or stages of embodiments of a method of manufacturing an electronic device of the present disclosure.

Fig. 56 shows or stages of embodiments of a method of manufacturing an electronic device of the present disclosure.

Fig. 57 shows or stages of embodiments of a method of manufacturing an electronic device of the present disclosure.

Fig. 58 shows or stages of embodiments of a method of manufacturing an electronic device of the present disclosure.

Fig. 59 shows or stages of embodiments of a method of manufacturing an electronic device of the present disclosure.

Detailed Description

Common reference numerals are used throughout the drawings and the detailed description to indicate the same or similar elements. Embodiments of the present disclosure will be readily understood by the following detailed description in conjunction with the accompanying drawings.

For example, in the following description, the formation of feature above or on the second feature may include embodiments in which feature and the second feature are formed or disposed in direct contact, and may also include embodiments in which additional features may be formed or disposed between feature and the second feature such that feature and the second feature may not be in direct contact.

In a comparative semiconductor package structure, the gap between solder balls may be 70 micrometers (μm.) in order to more accurately control the accuracy of a solder ball implanting process or a solder ball mounting process, the gap between solder balls may be as small as 50 μm.

For a chip-last packaging process, a substrate structure or wiring structure (including at least redistribution layers (RDL) and at least passivation layers) is formed or disposed on a carrier, and then a chip (or die) is attached to the substrate structure and electrically connected to the RDL, and finally, a molding compound (molding compound) is formed or disposed to cover the chip (or die) and the surface of the substrate structure, for example, the Young's modulus of a glass carrier or a silicone carrier is 100-200GPa, the Young's modulus of a metal carrier is 300GPa, the Young's modulus of the passivation layer of the substrate structure is 10-30GPa, and the Young's modulus of the molding compound is 10-30 GPa.

In the worst case, the pad displacement distance is even greater than the bond pad width (e.g., the pad displacement distance may be greater than 80 μm.) during a ball placement process or ball mounting process, solder balls are dropped onto the bond pads of the substrate structure through the through holes of the Stencil (Stencil). As a result, the solder balls may fall onto the center of the bond pads.

The present disclosure addresses at least of the above-mentioned problems and provides an improved electronic device, and an improved technique for fabricating a semiconductor package structure containing the electronic device.

Fig. 1 shows a cross-sectional view of an electronic device 1 of embodiments of the present disclosure, the electronic device 1 includes a wiring structure 2, a Seed layer (Seed layer)14, and at least electrical connection elements 12 the wiring structure 2 may be a substrate structure and may include a th insulating layer 20, a th metal layer 21, a second insulating layer 22, a second metal layer 23, a third insulating layer 24, a third metal layer 25, a fourth insulating layer 26, and at least Under Bump Metallization (UBM) 27.

The insulating layer 20 has a top surface 201 and a bottom surface 202 opposite the top surface 201 the insulating layer 20 defines at least openings 203 through the insulating layer 20 the openings 203 extend between the top surface 201 and the bottom surface 202 the material of the insulating layer 20 may comprise an insulating material, a passivation material, a dielectric material, or a solder resist material, such as a benzocyclobutene (BCB) type polymer or Polyimide (PI) in embodiments the insulating layer 20 may comprise a curable photosensitive dielectric (PID) material, such as an epoxy or PI. insulating layer 20 including a photoinitiator may have a thickness greater than about 5 μm in embodiments the insulating layer 20 may have a thickness of about 7 μm.

The th metal layer 21 may be a patterned wiring structure (e.g., a redistribution layer (RDL)) and disposed on the top surface 201 of the th insulating layer 20 and in the opening 203 of the 0 th insulating layer 20 may further include a seed layer (not shown) between the 1 th metal layer 21 and the 2 th insulating layer 20, the seed layer may be of titanium, copper, other metals, or alloys and may be formed, for example, by sputtering, the 3 th metal layer 21 may be of copper and may be formed, for example, by plating, the 4 th metal layer 21 may be greater than or equal to the thickness of the th insulating layer 20. in certain embodiments of , the th insulating layer 20 may be greater than about 5 μm thick, the th metal layer 21 may have a top surface 211 and a bottom surface 212 opposite the top surface 211. the bottom surface 212 of the th metal layer 21 is exposed at the bottom surface 202 of the th insulating layer 20 and may be substantially coplanar with the bottom surface 202 of the th insulating layer 20. the exposed portion of the bottom surface 212 forms a bonding pad for external connection.

The second insulating layer 22 covers at least portions of the th insulating layer 20 and the th metal layer 21 as shown in fig. 1, the second insulating layer 22 is disposed on the top surface 201 of the th insulating layer 20, the second insulating layer 22 has a top surface 221 and a bottom surface 222 opposite the top surface 221, the second insulating layer 22 defines at least openings 223 through the second insulating layer 22 to expose portions of the th metal layer 21, the material of the second insulating layer 22 may comprise an insulating material, a passivation material, a dielectric material, or a solder resist material, such as a benzocyclobutene (BCB) -based polymer or a Polyimide (PI), in embodiments, the second insulating layer 22 may comprise a curable photosensitive dielectric (PID) material, such as an epoxy or PI. containing a photoinitiator, the thickness of the second insulating layer 22 may be about 9 μm.

The second metal layer 23 may be a patterned line structure (e.g., a redistribution layer (RDL)) and disposed on the top surface 221 of the second insulating layer 22 and in the opening 223 of the second insulating layer 22 to contact or electrically connect the exposed portion of the th metal layer 21 a seed layer (not shown) may be additionally included between the second metal layer 23 and the second insulating layer 22. the material of the seed layer may be titanium, copper, other metals, or alloys and may be formed by, for example, sputtering, the material of the second metal layer 23 may comprise copper and may be formed by, for example, plating, the thickness of the second metal layer 23 may be greater than about 8 μm.

The third insulating layer 24 covers at least portions of the second insulating layer 22 and the second metal layer 23, as shown in FIG. 1, the third insulating layer 24 is disposed on a top surface 221 of the second insulating layer 22. the third insulating layer 24 has a top surface 241 and a bottom surface 242 opposite the top surface 241. the third insulating layer 24 defines at least openings 243 through the third insulating layer 24 to expose portions of the second metal layer 23. the material of the third insulating layer 24 may comprise an insulating material, a passivation material, a dielectric material, or a solder resist material, such as a benzocyclobutene (BCB) based polymer or Polyimide (PI). In embodiments, the third insulating layer 24 may comprise a curable photosensitive dielectric (PID) material, such as an epoxy or PI. comprising a photoinitiator, the third insulating layer 24 may have a thickness of about 9 μm.

The third metal layer 25 may be a patterned circuit structure (e.g., a redistribution layer (RDL)), and is disposed on the top surface 241 of the third insulating layer 24 and in the opening 243 of the third insulating layer 24 to contact or electrically connect the exposed portion of the second metal layer 23. A seed layer (not shown) may be further included between the third metal layer 25 and the third insulating layer 24. The material of the seed layer may be titanium, copper, other metals or alloys, and may be formed by, for example, sputtering. The material of the third metal layer 25 may include copper, and may be formed by, for example, plating. The thickness of the third metal layer 25 may be about 8 μm.

The fourth insulating layer 26 covers at least portions of the third insulating layer 24 and the third metal layer 25, as shown in FIG. 1, the fourth insulating layer 26 is disposed on a top surface 241 of the third insulating layer 24, the fourth insulating layer 26 has a top surface 261 and a bottom surface 262 opposite the top surface 261, the fourth insulating layer 26 defines at least openings 263 through the fourth insulating layer 26 to expose a portion of the third metal layer 25. the material of the fourth insulating layer 26 may comprise an insulating material, a passivation material, a dielectric material, or a solder resist material, such as a benzocyclobutene (BCB) based polymer or Polyimide (PI). In embodiments, the fourth insulating layer 26 may comprise a curable photosensitive dielectric (PID) material, such as an epoxy or PI. comprising a photoinitiator, the fourth insulating layer 26 may have a thickness of about 9 μm.

An Under Bump Metallurgy (UBM)27 is electrically connected to the third metal layer 25. As shown in FIG. 1, the UBM 27 is disposed in the opening 263 of the fourth insulating layer 26, and a portion of the UBM 27 may extend on the top surface 261 of the fourth insulating layer 26. in some embodiments , the UBM 27 comprises a UBM seed layer, a copper layer, a nickel layer, and a gold layer sequentially disposed in the opening 263 of the fourth insulating layer 26. the UBM seed layer may be made of titanium, copper, other metals, or alloys.

As described above, the wiring structure 2 includes four insulating layers (or passivation layers) and three metal layers, and is referred to as a "4P 3M" structure it should be noted that the wiring structure 2 may be a "5P 4M" structure including five insulating layers (or passivation layers) and four metal layers, a "5P 5M" structure including five insulating layers (or passivation layers) and five metal layers, or a "1P 1M" structure including insulating layers (or passivation layers) and metal layers.

Seed layer 14 may include th conductive layer 141 and second conductive layer 142. the material of th conductive layer 141 of seed layer 14 comprises a titanium-Tungsten (TiW) alloy that may be formed by Physical Vapor Deposition (PVD). the material of second conductive layer 142 of seed layer 14 comprises copper that may be formed by Physical Vapor Deposition (PVD). the thickness of th conductive layer 141 may be less than 1 μm and the thickness of second conductive layer 142 may be less than 1 μm. as shown in fig. 1, seed layer 14 is raised above the bottom surface 212 of th metal layer 21. that is, seed layer 14 is disposed above and below the bottom surface 212 of th metal layer 21. second conductive layer 142 of seed layer 14 contacts and/or electrically connects exposed portions of the bottom surface 212 of th metal layer 21 of wiring structure 2.

The electrical connection element 12 (e.g., solder bump) is attached and electrically connected to the bottom surface 212 of the th metal layer 21 through the seed layer 14 for external connection, as shown in fig. 1, the electrical connection element 12 is attached and electrically connected to the th conductive layer 141 of the seed layer 14, that is, the electrical connection element 12 is protruded from the bottom surface of the seed layer 14 and the bottom surface 202 of the th insulating layer 20, the material of the electrical connection element 12 comprises silver-tin (AgSn) alloy, the thickness of the electrical connection element 12 may be greater than about 20 μm, the electrical connection element 12 has a rectangular pillar, cylindrical or other pillar type shape, since the electronic device 1 is not subjected to reflow process (reflow process), that is, the electrical connection element 12 of fig. 1 is not spherical.

In the embodiment shown in fig. 1, the electrical connection element 12 and the seed layer 14 are formed before the wiring structure 2 is formed, and thus, the electrical connection element 12 and the seed layer 14 are disposed directly above the exposed portion (i.e., the bonding pad) of the bottom surface 212 of the th metal layer 21 of the wiring structure 2. that is, the vertical central axis of the electrical connection element 12 and the seed layer 14 may be substantially aligned with the central axis of the exposed portion (i.e., the bonding pad) of the bottom surface 212 of the th metal layer 21. further, even if the wiring structure 2 is warped, the electrical connection element 12 and the seed layer 14 may be displaced or moved from the exposed portion (i.e., the bonding pad) of the bottom surface 212 of the th metal layer 21. accordingly, the bonding yield between the electrical connection element 12 and the wiring structure 2 may be improved.

FIG. 2 shows an enlarged view of the area "A" in FIG. 1. the opening 203 in the th insulating layer 20 includes a top 2031 and a bottom 2032. the top 2031 has a th width W₁And the bottom 2032 has a second width W₂ th width W of top 2031₁Second width W greater than bottom 2032₂Thus, the opening 203 tapers from the top 2031 to the bottom 2032, however, in other embodiments, the th width W of the top 2031₁May be substantially equal to second width W of bottom 2032₂. Note that the second width W of the bottom 2032₂Is the width of the exposed portion (i.e., the bond pad) of the bottom surface 212 of the th metal layer 21 the width of the electrical connection element 12 is substantially equal to the width of the seed layer 14, both defined as the third width W₃ second width W of exposed portion (i.e., bond pad) of bottom surface 212 of metal layer 21₂Is less than or equal to the third width W of the electrical connection element 12 and the seed layer 14₃(e.g., may be about 1.0 times, less than about 0.9 times, less than about 0.8 times, less than about 0.7 times, or less than about 0.6 times). For example, (W)₂/W₃) The ratio of (A) may be in the range of 1.0-0.8, 0.9-0.7 or 0.8-06 as shown in fig. 2, a central portion of the seed layer 14 may contact the entire exposed portion (i.e., bond pad) of the bottom surface 212 of the metal layer 21 and peripheral portions (e.g., left and right sides) of the seed layer 14 may contact the bottom surface 202 of the th insulating layer 20 it is noted that the entire exposed portion (i.e., bond pad) of the bottom surface 212 of the th metal layer 21 is chemically (e.g., PVD) connected to the central portion of the seed layer 14 and the bottom surface 202 of the th insulating layer 20 is physically (e.g., adhesively) connected to the peripheral portions (e.g., left and right sides) of the seed layer 14, thus, the bonding force between the exposed portion (i.e., bond pad) of the bottom surface 212 of the th metal layer 21 and the seed layer 14 is greater than the bonding force between the bottom surface 202 of the th.

Fig. 3 shows a cross-sectional view of an electronic device 3 of embodiments of the present disclosure, the electronic device 3 of fig. 3 is a semiconductor package structure and includes the electronic device 1 of fig. 1, a th semiconductor die 32, at least of the 1 st interconnection element 31, a second semiconductor die 34, at least of the second interconnection element 33, and a package (encapsulant)36 the electronic device 1 includes a routing structure 2, a seed layer 14, and electrical connection elements 12 as described above the first semiconductor die 32 may be the same or different in function and size as the second semiconductor die 34, the th semiconductor die 32 is electrically connected to the third metal layer 25 of the routing structure 2 by th interconnection element 31 and UBM 27. for example, the th semiconductor die 32 includes at least of the th bump pad 321, the interconnection element 31 is disposed on the UBM 27 and connected to the bump pad 321 of the second semiconductor die 36, in embodiments the second interconnection element 31 may be formed by a presoal interconnection element 341-341, and may be formed by solder ball interconnection elements 34, and bump interconnection elements 34 may be formed by solder balls interconnection structures 34, similar to UBM interconnection elements 33, interconnection elements 34, 26 interconnection elements interconnection and/.

Package 36 is disposed on fourth insulating layer 26 and encapsulates and covers th semiconductor die 32, th interconnection element 31, second semiconductor die 34, second interconnection element 33, and UBM 27. the material of package 36 may be a mold compound with or without a filler material package 36 and wiring structure 2 are singulated simultaneously such that the sides of package 36 are substantially coplanar with the sides of wiring structure 2.

Fig. 4 shows a cross-sectional view of an electronic device 1a of embodiments of the present disclosure, the electronic device 1a is similar to the electronic device 1 shown in fig. 1 and 2, except that the electronic device 1a further includes a barrier layer (barrier layer)16 interposed between the electrical connection element 12 and the conductive layer 141 of the seed layer 14, the material of the barrier layer 16 may comprise nickel that may be formed by Physical Vapor Deposition (PVD), the thickness of the barrier layer 16 may be less than 1 μm in the embodiment shown in fig. 1 and 2, the barrier layer is not included, and thus, during the reflow process, copper in the second conductive layer 142 of the seed layer 14 and copper in the metal layer 21 may rapidly enter the electrical connection element 12 to form intermetallic compounds (IMCs), such as Cu₆Sn₅And Cu₃Sn₄。Cu₃Sn₄IMC is a brittle material that reduces the reliability of the bond between the electrical connection element 12 and the th metal layer 21 As shown in FIG. 4, the barrier layer 16 inhibits the formation of IMC, particularly Cu₃Sn₄The formation of the IMC, therefore, can increase the reliability of the bonding between the electrical connection element 12 and the th metal layer 21.

Fig. 5 shows a cross-sectional view of an electronic device 1b of the embodiments of the present disclosure, the electronic device 1b is similar to the electronic device 1 shown in fig. 1 and 2 except that the seed layer 14 of the electronic device 1 is omitted, and thus, the electrical connection element 12 is attached and electrically connected to an exposed portion of the bottom surface 212 of the metal layer 21 for external connection, the electrical connection element 12 has a top surface 121 and a bottom surface 122 opposite the top surface 121, the top surface 121 of the electrical connection element 12 is substantially coplanar with the bottom surface 202 of the th insulating layer 20, as shown in fig. 5, the electrical connection element 12 is raised above the bottom surface 212 of the th metal layer 21 and the bottom surface 202 of the th insulating layer 20, the electrical connection element 12 is in a rectangular cylindrical, pillar or other pillar type shape, because no reflow process is performed on the electronic device 1b, the electrical connection element 12 is formed before the formation of the wiring structure 2, therefore, the electrical connection element 12 is disposed directly above the exposed portion (i.e. the bonding pad) of the bottom surface 212 of the metal layer 21 of the wiring structure 2, that is vertically aligned with the exposed portion (i.e.e. the bonding pad) of the wiring structure 3521, and that the electrical connection element 12 is capable of being displaced, even if the bonding pad size of the bonding pad is increased, the bonding pad is not required to be aligned with the wiring structure 3521, or the bonding pad.

Fig. 6 shows an enlarged view of the region "B" in fig. 5. The opening 203 of fig. 6 is the same as the opening 203 of fig. 2, and tapers from the top 2031 to the bottom 2032. The width of the electrical connection member 12 is defined as a third width W₃ second width W of exposed portion (i.e., bond pad) of bottom surface 212 of metal layer 21₂Is less than or equal to the third width W of the electrical connection element 12₃(e.g., may be about 1.0 times, less than about 0.9 times, less than about 0.8 times, less than about 0.7 times, or less than about 0.6 times). For example, (W)₂/W₃) As shown in fig. 6, the central portion of the electrical connection element 12 may contact the entire exposed portion of the bottom surface 212 of the metal layer 21 (i.e., the bond pad), and the peripheral portions of the electrical connection element 12 (e.g., the left and right sides) may contact the bottom surface 202 of the insulating layer 20 it should be noted that the entire exposed portion of the bottom surface 212 of the metal layer 21 (i.e., the bond pad) is chemically (e.g., PVD) connected to the central portion of the electrical connection element 12, and the bottom surface 202 of the insulating layer 20 is physically (e.g., adhesively) connected to the peripheral portions of the electrical connection element 12 (e.g., the left and right sides), thus, the bonding force between the exposed portion of the bottom surface 212 of the metal layer 21 (i.e., the bond pad) and the electrical connection element 12 is greater than the bonding force between the bottom surface 202 of the insulating layer 20 and the electrical connection element 12.

Fig. 7 shows a cross-sectional view of an electronic device 3a of embodiments of the present disclosure, the electronic device 3a is similar to the electronic device 3 of fig. 3 except that the seed layer 14 of the electronic device 1 is omitted, the electronic device 3a of fig. 7 is a semiconductor package structure and includes the electronic device 1b of fig. 5, a semiconductor die 32, a interconnection element 31, a second semiconductor die 34, a second interconnection element 33, and an encapsulant 36, the electronic device 1b includes a routing structure 2 and an electrical connection element 12 as described above, the semiconductor die 32 is electrically connected to the third metal layer 25 of the wiring structure 2 through the interconnection element 31 and the UBM 27, the second semiconductor die 34 is electrically connected to the third metal layer 25 of the wiring structure 2 through the second interconnection element 33 and the UBM 27, the encapsulant 36 is disposed on the fourth insulating layer 26 and encapsulates and covers the semiconductor die 32, the interconnection element 31, the second semiconductor die 34, the second interconnection element 33, and the UBM 27, the routing material of the encapsulant 36 may be a single sided encapsulant 36 with or without the encapsulant 36, and the encapsulant 36 substantially co-sided planar side of the encapsulant structure.

FIG. 8 shows a cross-sectional view of an electronic device 1c of embodiments of the present disclosure, the electronic device 1c being similar to the electronic device 1b shown in FIG. 5, except that the electronic device 1c further includes a barrier layer 16 interposed between the electrical connection element 12 and the bottom surface 212 of the metal layer 21, the barrier layer 16 is disposed in the opening 203 of the insulating layer 20, and the bottom surface of the barrier layer 16 is substantially coplanar with the bottom surface 202 of the insulating layer 20, the material of the barrier layer 16 may comprise nickel that may be formed by Physical Vapor Deposition (PVD), the thickness of the barrier layer 16 may be less than 1 μm, the barrier layer 16 may inhibit the formation of IMCs, particularly Cu₃Sn₄The formation of the IMC, therefore, can increase the reliability of the bonding between the electrical connection element 12 and the th metal layer 21.

Fig. 9 shows a cross-sectional view of an electronic device 3b of some embodiments of the present disclosure fig. 10 shows an enlarged view of region "C" in fig. 9. electronic device 3b is a semiconductor package structure and is similar to electronic device 3a of fig. 7, except that the structure of electronic device 1 d. electronic device 1d of fig. 9 further includes a seed layer 15 under metal layer . the layout and pattern of seed layer 15 is the same as the layout and pattern of metal layer 0. seed layer 15 is interposed between metal layer and insulating layer . that is, seed layer 15 is disposed on top surface 201 and in opening 203 of insulating layer . seed layer 20. additionally, seed layer 15 is interposed between metal layer and electrical connection element 12. the bottom surface of seed layer 15 is substantially coplanar with bottom surface 202 of insulating layer . seed layer 15 may include conductive layer 151 and conductive layer 152. the material of conductive layer of seed layer 151 may include conductive layer 151 and conductive layer 152. the material of conductive layer 151 may include a titanium-Tungsten (TiW) alloy formed by Physical Vapor Deposition (PVD). the conductive layer may include a conductive layer 387 μm and may be less than the thickness of conductive layer 151, and the conductive layer 151 may be formed by PVD.

FIG. 11 shows a cross-sectional view of an electronic device 3c of embodiments of the present disclosure, the electronic device 3c is a semiconductor package structure and is similar to the electronic device 3 of FIG. 3, except for the structure of the electronic device 1e, the electronic device 1e of FIG. 11 further includes at least solid nuclear balls 40 disposed in the electrical connection element 12. in embodiments, the solid nuclear balls 40 may be copper nuclear balls, as shown in FIG. 11, the top ends of the solid nuclear balls 40 may contact the conductive layer 141 of the seed layer 14. when the electronic device 3c is mounted to a motherboard, the solid nuclear balls 40 may act as standoffs to prevent tilting.

Fig. 12 shows a cross-sectional view of an electronic device 3d of embodiments of the present disclosure, the electronic device 3d is a semiconductor package structure and is similar to the electronic device 3 of fig. 3 except for the structure of the electrical connection element 12, the electrical connection element 12 becomes spherical due to the cohesive force of melting as a result of the reflow process performed on the electronic device 3d of fig. 12.

Fig. 13 shows a cross-sectional view of an electronic device 3e of embodiments of the present disclosure, the electronic device 3e is a semiconductor package structure and is similar to the electronic device 3a of fig. 7 except for the structure of the electrical connection element 12, the electrical connection element 12 becomes spherical due to the cohesive force of the melt as a result of the reflow process performed on the electronic device 3e of fig. 13.

Fig. 14 shows a cross-sectional view of an electronic device 3f of embodiments of the present disclosure, the electronic device 3f is a semiconductor package structure and is similar to the electronic device 3b of fig. 9, except for the structure of the electrical connection element 12, the electrical connection element 12 becomes spherical due to the cohesive force of melting as a result of the reflow process performed on the electronic device 3f of fig. 14.

Fig. 15 shows a cross-sectional view of an electronic device 3g of embodiments of the present disclosure, the electronic device 3g being a semiconductor package structure and being similar to the electronic device 3c of fig. 11 except for the structure of the electrical connection element 12, the electrical connection element 12 becomes spherical due to the cohesive force of the melt as a result of the reflow process performed on the electronic device 3g of fig. 15.

Fig. 16 shows a cross-sectional view of an assembly 5 of some embodiments of the present disclosure . in assembly 5, the electronic device 3 of fig. 3 is mounted to a motherboard 42. motherboard 42 includes a plurality of pads 421 and electrical connection elements 12 of electronic device 3 contact pads 421 of motherboard 42. since electrical connection elements 12 are rectangular cylindrical or cylindrical prior to the reflow process, the contact area between electrical connection elements 12 and pads 421 of motherboard 42 is greater than the contact area between the solder balls and pads 421 of motherboard 42. thus, the bonding quality and reliability of assembly 5 after the reflow process can be increased.

Fig. 17-29 show or stages of embodiments of a method of manufacturing an electronic device 3 (e.g., a semiconductor package structure) of the present disclosure in embodiments the method is for manufacturing an electronic device such as the electronic device 3 (e.g., a semiconductor package structure) shown in fig. 3.

Referring to fig. 17, a carrier 44 is provided, the carrier 44 may be made of ceramic, silicon, glass, or metal, the carrier 44 has an th surface 441 and a second surface 442 opposite the th surface 441, and a plurality of openings 443 are defined on the th surface 441, each of the openings 443 is a blind hole recessed in the th surface 441 and not penetrating the carrier 44, the openings 443 may be formed by plasma etching, and the shape of the openings 443 may be any shape, for example, the openings 443 may be circular or rectangular when viewed from above, in embodiments, the gaps between the openings 443 may be less than about 70 μm, about 60 μm, or about 50 μm, and the aspect ratio (depth/width) of the openings 443 may be greater than or equal to about 1, about 1.2, about 1.5, or about 2.

Referring to fig. 18, a release layer (release layer)46 is formed or disposed in the opening 443 of the carrier 44 and on the -th surface 441 by, for example, coating.

Referring to fig. 19, conductive material 12a is formed or disposed on release layer 46 in opening 443 of carrier 44 by, for example, printing, the material of conductive material 12a includes a solder material such as a silver-tin (AgSn) alloy, in some embodiments of , a top surface of conductive material 12a may be substantially coplanar with a top surface of release layer 46 on surface 441 of carrier 44.

Referring to fig. 20, seed layer 14 is formed or disposed on conductive material 12a and release layer 46 on -th surface 441 of carrier 44 by, for example, sputtering in embodiments seed layer 14 may include -th conductive layer 141 and second conductive layer 142. the material of -th conductive layer 141 of seed layer 14 comprises a titanium-Tungsten (TiW) alloy that may be formed by Physical Vapor Deposition (PVD). the material of second conductive layer 142 of seed layer 14 comprises copper that may be formed by Physical Vapor Deposition (PVD) on -th conductive layer 141. the thickness of -th conductive layer 141 may be less than 1 μm, and the thickness of second conductive layer 142 may be less than 1 μm. as shown in fig. 20, -th conductive layer 141 of seed layer 14 is in contact with and/or electrically connected to conductive material 12 a.

Referring to fig. 21-24, a wiring structure 2 is formed or disposed on the seed layer 14, thus, the wiring structure 2 is formed or disposed on the carrier 44 and the conductive material 12a referring to fig. 21, an th insulating layer 20 is formed or disposed on the second conductive layer 142 of the seed layer 14 by, for example, coating, the material of the th insulating layer 20 may comprise an insulating material, a passivation material, a dielectric material, or a solder resist material, such as a benzocyclobutene (BCB) -based polymer or Polyimide (PI), in embodiments, the th insulating layer 20 may comprise a curable photosensitive dielectric (PID) material, such as an epoxy or PI. th insulating layer 20 comprising a photoinitiator, which may have a thickness greater than about 5 μm, in embodiments, the th insulating layer 20 may have a thickness of about 7 μm, the th insulating layer 20 has a top surface 201 and a bottom surface 202 opposite the top surface 201.

Referring to fig. 22, portions of the th insulating layer 20 are removed, for example, by photolithography (photolithography) to form exposed seed crystalsA plurality of openings 203 that are part of the layer 14, the openings 203 extend through the th insulating layer 20, that is, the openings 203 extend between the top surface 201 and the bottom surface 202. the positions of the openings 203 may correspond to the positions of the conductive material 12 a. As shown in FIG. 22, the openings 203 are disposed directly above the conductive material 12 a. As shown in FIG. 2, the openings 203 of the th insulating layer 20 include a top 2031 and a bottom 2032. the top 2031 has a th width W₁And the bottom 2032 has a second width W₂ th width W of top 2031₁Second width W greater than bottom 2032₂Thus, the opening 203 tapers from the top 2031 to the bottom 2032, however, in other embodiments, the th width W of the top 2031₁May be substantially equal to second width W of bottom 2032₂. The width of the electrical connection member 12 is defined as a third width W₃. Second width W of bottom 2032 of opening 203₂Is less than or equal to the third width W of the electrical connection element 12₃(e.g., may be about 1.0 times, less than about 0.9 times, less than about 0.8 times, less than about 0.7 times, or less than about 0.6 times). For example, (W)₂/W₃) The ratio of (A) may be in the range of 1.0-0.8, 0.9-0.7 or 0.8-0.6.

Referring to fig. 23, a th metal layer 21 is formed in the opening 203 of the th insulating layer 20 and on the exposed portion of the seed layer 14. 0 th metal layer 21 may be a patterned line structure (e.g., a redistribution layer (RDL)) and disposed on the top surface 201 of the 1 th insulating layer 20 and in the opening 203 of the 2 th insulating layer 20. a seed layer (not shown) may be further included between the 3 th metal layer 21 and the 4 th insulating layer 20. the material of the 5 th metal layer 21 may include copper and may be formed, for example, by plating. the thickness of the 6 th metal layer 21 may be greater than or equal to the thickness of the th insulating layer 20. in embodiments, the thickness of the th insulating layer 20 may be greater than about 5 μm. the th metal layer 21 has a top surface 211 and a bottom surface 212 opposite the top surface 211. the bottom surface 212 of the th metal layer 21 is exposed at the bottom surface 202 of the th insulating layer 20 and is substantially coplanar with the bottom surface 202 of the th insulating layer 20. the exposed portion of the for forming external bond pads.

As shown in fig. 23, a central portion of the seed layer 14 may contact the entire exposed portion (i.e., bond pad) of the bottom surface 212 of the th metal layer 21 and peripheral portions (e.g., left and right sides) of the seed layer 14 may contact the bottom surface 202 of the th insulating layer 20 it is noted that the entire exposed portion (i.e., bond pad) of the bottom surface 212 of the th metal layer 21 is chemically (e.g., PVD) connected to the central portion of the seed layer 14 and the bottom surface 202 of the th insulating layer 20 is physically (e.g., adhesively) connected to the peripheral portions (e.g., left and right sides) of the seed layer 14, thus, the bonding force between the exposed portion (i.e., bond pad) of the bottom surface 212 of the th metal layer 21 and the seed layer 14 is greater than the bonding force between the bottom surface.

Meanwhile, the conductive material 12a is attached and electrically connected to the bottom surface 212 of the metal layer 21 through the seed layer 14, as shown in FIG. 23, the conductive material 12a is attached and electrically connected to the conductive layer 141 of the seed layer 14. that is, the conductive material 12a protrudes from the bottom surface of the seed layer 14 and the bottom surface 202 of the insulating layer 20. since the Young's modulus of the carrier 44 is much greater than that of the insulating layer 20, the carrier 44 can hold the insulating layer 20. therefore, the insulating layer 20 will not warp and the exposed portions (i.e., bond pads) of the bottom surface 212 of the metal layer 21 will not be displaced and will be disposed at predetermined positions. that is, the exposed portions (i.e., bond pads) of the bottom surface 212 of the metal layer 21 can be precisely disposed over the conductive material 12 a.

Referring to fig. 24, second insulating layer 22, second metal layer 23, third insulating layer 24, third metal layer 25, fourth insulating layer 26, at least Under Bump Metallurgy (UBM)27 are then formed on insulating layer 20 and metal layer 21 to form wiring structure 2 it is noted that conductive material 12a and seed layer 14 are formed prior to the formation of wiring structure 2 and the bond between the exposed portion of bottom surface 212 of metal layer (i.e., the bond pad) and seed layer 14 (and conductive material 12a) is formed prior to the encapsulation process, thus the vertical central axis of conductive material 12a and seed layer 14 may be substantially aligned with the central axis of the exposed portion of bottom surface 212 of seed layer 21 (i.e., the bond pad) of metal layer 21. additionally, even if wiring structure 2 is warped, conductive material 12a and 14 may be displaced or moved from exposed portion of bottom surface 212 of seed layer 212 (i.e., the bond pad) of metal layer 21. further, the yield of the bond pad between conductive material 12a and wiring structure 2 may be improved by a thickness of 861, 865 μm, and the width of the exposed portion of conductive material of the exposed portion of the bottom surface of seed layer 212 may be less than about 1 μm or about 0 μm in embodiments, and may be greater than about 0 μm.

As described above, the wiring structure 2 includes four insulating layers (or passivation layers) and three metal layers, and is referred to as a "4P 3M" structure it should be noted that the wiring structure 2 may be a "5P 4M" structure including five insulating layers (or passivation layers) and four metal layers, a "5P 5M" structure including five insulating layers (or passivation layers) and five metal layers, or a "1P 1M" structure including insulating layers (or passivation layers) and metal layers.

In some embodiments, if carrier 44 and release layer 46 are removed, and the portions of seed layer 14 not covered by conductive material 12a are removed, such as by etching, electronic device 1 of fig. 1 may result — it is noted that conductive material 12a becomes electrically connecting element 12 in some embodiments, electronic device 1a of fig. 4 may result if barrier layer 16 (fig. 4) is formed on conductive material 12a prior to the formation of seed layer 14 (i.e., prior to the stage of fig. 20).

Referring to fig. 25, a th semiconductor die 32 and a second semiconductor die 34 are electrically connected to the wiring structure 2. the function and size of the th semiconductor die 32 may be the same as or different from the function and size of the second semiconductor die 34. the 0 th semiconductor die 32 is electrically connected to the third metal layer 25 of the wiring structure 2 by a 1 th interconnection element 31 and a UBM 27 and flip chip bonding (flip chip bonding). for example, the 2 th semiconductor die 32 includes at least th bump pads 321. the th interconnection element 31 is disposed on the UBM 27 and connected to the th bump pad 321. in embodiments, the th interconnection element 31 may be formed of a pre-solder or a solder ball. similarly, the second semiconductor die 34 is disposed on the UBM 27 and connected to the UBM 27 and flip chip bonding electrically connected to the third metal layer 25 of the wiring structure 2. for example, the second semiconductor die 34 includes at least second bump pads 341. the second interconnection element 33 is disposed on the UBM 27 and connected to the UBM pad . in some embodiments, the solder balls may be formed of a solder ball interconnection element or a solder ball interconnection element.

Referring to fig. 26, package 36 is formed or disposed on fourth insulating layer 26 of wiring structure 2 to encapsulate and cover th semiconductor die 32, th interconnection element 31, second semiconductor die 34, second interconnection element 33, and UBM 27. the material of package 36 may be a mold compound with or without a filler.

Referring to fig. 27, carrier 44 is removed, and at the same time, conductive material 12a and seed layer 14 may be displaced or moved from exposed portion (i.e., bonding pad) of bottom surface 212 of metal layer 21 even though wiring structure 2 and package 36 are warped.

Referring to fig. 28, the release layer 46 is removed.

Referring to fig. 29, the portions of seed layer 14 not covered by conductive material 12a are removed by, for example, etching. At the same time, the conductive material 12a becomes the electrical connection element 12. Subsequently, a singulation process is performed to obtain the electronic device 3 (i.e., the semiconductor package) shown in fig. 3. The package 36 and the wiring structure 2 are simultaneously singulated so that the side of the package 36 is substantially coplanar with the side of the wiring structure 2. It should be noted that if the electronic device 3 of fig. 3 is subjected to the reflow process, the electrical connection element 12 (i.e., the conductive material 12a) becomes spherical due to cohesive force of reflow and melting to obtain an electronic device 3d (i.e., a semiconductor package structure) as shown in fig. 12.

Fig. 30-41 show or stages of embodiments of a method of manufacturing an electronic device 3a (e.g., a semiconductor package structure) of the present disclosure in embodiments the method is for manufacturing an electronic device such as the electronic device 3a (e.g., a semiconductor package structure) shown in fig. 7.

Referring to FIG. 30, a carrier 44 is provided, the carrier 44 may be made of ceramic, silicon, glass, or metal, the carrier 44 has an th surface 441 and a second surface 442 opposite the th surface 441, and a plurality of openings 443 are defined on the th surface 441, each of the openings 443 being blind holes recessed in the th surface 441 and not extending through the carrier 44.

Referring to fig. 31, a release layer 46 is formed or disposed in the opening 443 and on the -th surface 441 of the carrier 44 by, for example, coating.

Referring to fig. 32, seed layer 14 is formed or disposed in opening 443 of carrier 44 and on release layer 46 on surface 441 of by, for example, sputtering in embodiments seed layer 14 may include a th conductive layer 141 and a second conductive layer 142. the material of th conductive layer 141 of seed layer 14 comprises a titanium-Tungsten (TiW) alloy that may be formed by physical vapor deposition (PVD.) the material of second conductive layer 142 of seed layer 14 comprises copper that may be formed by Physical Vapor Deposition (PVD) on th conductive layer 141.

Referring to fig. 33, conductive material 12a is formed or disposed on seed layer 14 in opening 443 of carrier 44 by, for example, electroplating, the material of conductive material 12a includes a solder material such as a silver-tin (AgSn) alloy, in some embodiments, top surface 121 of conductive material 12a may be substantially coplanar with a top surface of seed layer 14 on surface 441 of carrier 44.

Referring to fig. 34-37, a wiring structure 2 is formed or disposed on the seed layer 14 and the conductive material 12a, referring to fig. 34, an th insulating layer 20 is formed or disposed on the second conductive layer 142 of the seed layer 14 and the conductive material 12a, such as by coating, the th insulating layer 20 has a top surface 201 and a bottom surface 202 opposite the top surface 201, the top surface 121 of the conductive material 12a may be substantially coplanar with the bottom surface 202 of the th insulating layer 20.

Referring to FIG. 35, portions of the th insulating layer 20 are removed, such as by photolithography, to form a plurality of openings 203 exposing portions of the conductive material 12 a. the openings 203 extend through the th insulating layer 20, i.e., the openings 203 extend between the top surface 201 and the bottom surface 202. the positions of the openings 203 may correspond to the positions of the conductive material 12 a. As shown in FIG. 35, the openings 203 are disposed directly above the conductive material 12 a.

Referring to fig. 36, an th metal layer 21 is formed in the opening 203 of the th insulating layer 20 and on the exposed portion of the conductive material 12a, the th metal layer 21 may be a patterned circuit structure (e.g., a redistribution layer (RDL)) and disposed on the top surface 201 of the th insulating layer 20 and in the opening 203 of the th insulating layer 20, the th metal layer 21 has a top surface 211 and a bottom surface 212 opposite to the top surface 211, the bottom surface 212 of the th metal layer 21 is exposed at the bottom surface 202 of the th insulating layer 20 and contacts the top surface 121 of the conductive material 12 a.

As shown in fig. 36, the central portion of the conductive material 12a may contact the entire exposed portion (i.e., the bonding pad) of the bottom surface 212 of the metal layer 21 and the peripheral portions (e.g., the left and right sides) of the conductive material 12a may contact the bottom surface 202 of the insulation layer 20 it is noted that the entire exposed portion (i.e., the bonding pad) of the bottom surface 212 of the metal layer 21 is chemically (e.g., PVD) connected to the central portion of the conductive material 12a and the bottom surface 202 of the insulation layer 20 is physically (e.g., adhesively) connected to the peripheral portions (e.g., the left and right sides) of the conductive material 12a, and thus, the bonding force between the exposed portion (i.e., the bonding pad) of the bottom surface 212 of the metal layer 21 and the conductive material 12a is greater than the bonding force between the bottom surface 202 of the .

Meanwhile, the conductive material 12a is directly attached and electrically connected to the bottom surface 212 of the metal layer 21. that is, the conductive material 12a is protruded from the bottom surface 202 of the insulating layer 20. since the Young's modulus of the carrier 44 is much greater than that of the insulating layer 20, the carrier 44 can hold the insulating layer 20. therefore, the insulating layer 20 will not be warped and the exposed portion (i.e., the bonding pad) of the bottom surface 212 of the metal layer 21 will not be displaced and will be disposed at a predetermined position. that is, the exposed portion (i.e., the bonding pad) of the bottom surface 212 of the metal layer 21 can be precisely disposed on the conductive material 12 a.

Referring to fig. 37, a second insulating layer 22, a second metal layer 23, a third insulating layer 24, a third metal layer 25, a fourth insulating layer 26, and at least Under Bump Metallurgy (UBM)27 are then formed on insulating layer 20 and metal layer 21 to form wiring structure 2. in embodiments , if carrier 44, release layer 46, and seed layer 14 are removed, electronic device 1b of fig. 5 can be obtained-note that conductive material 12a becomes electrically connected element 12. in embodiments , if barrier layer 16 (fig. 8) is formed over conductive material 12a before metal layer 21 is formed (i.e., before the stage of fig. 36), electronic device 1c of fig. 8 can be obtained.

Referring to fig. 38, the th semiconductor die 32 and the second semiconductor die 34 are electrically connected to the wiring structure 2. the th semiconductor die 32 is electrically connected to the third metal layer 25 of the wiring structure 2 through the th interconnection element 31 and the UBM 27 and in flip-chip bonding, and the second semiconductor die 34 is electrically connected to the third metal layer 25 of the wiring structure 2 through the second interconnection element 33 and the UBM 27 and in flip-chip bonding.

Referring to fig. 39, package 36 is formed or disposed on fourth insulating layer 26 of wiring structure 2 to encapsulate and cover th semiconductor die 32, th interconnection element 31, second semiconductor die 34, second interconnection element 33, and UBM 27.

Referring to fig. 40, the carrier 44 is removed, and at the same time, even if the wiring structure 2 and the package body 36 are warped, the conductive material 12a may be displaced or moved from the exposed portion (i.e., the bonding pad) of the bottom surface 212 of the metal layer 21.

Referring to fig. 41, the release layer 46 and the seed layer 14 are removed. At the same time, the conductive material 12a becomes the electrical connection element 12. Next, a singulation process is performed to obtain an electronic device 3a (i.e., a semiconductor package) as shown in fig. 7. It should be noted that if the reflow process is performed on the electronic device 3a of fig. 7, the electrical connection elements 12 (i.e., the conductive materials 12a) become spherical due to cohesive force of reflow and melting to obtain an electronic device 3e (i.e., a semiconductor package structure) as shown in fig. 13.

Fig. 42-54 show or stages of embodiments of a method of manufacturing an electronic device 3b (e.g., a semiconductor package structure) of the present disclosure in embodiments the method is for manufacturing an electronic device such as the electronic device 3b (e.g., a semiconductor package structure) shown in fig. 9.

Referring to FIG. 42, a carrier 44 is provided, the carrier 44 has an th surface 441 and a second surface 442 opposite the th surface 441, and defines a plurality of openings 443 on the th surface 441, each of the openings 443 are blind holes recessed in the th surface 441 and not through the carrier 44.

Referring to fig. 43, a release layer 46 is formed or disposed in the opening 443 and on the -th surface 441 of the carrier 44 by, for example, coating.

Referring to fig. 44, the conductive material 12a is formed or disposed on the release layer 46 in the opening 443 of the carrier 44 by, for example, printing embodiments, the top surface 121 of the conductive material 12a may be substantially coplanar with the top surface of the release layer 46 on the -th surface 441 of the carrier 44.

Referring to fig. 45-50, wiring structure 2 is formed or disposed on conductive material 12a and release layer 46 on -th surface 441 of carrier 44. referring to fig. 45, th insulating layer 20 is formed or disposed on conductive material 12a and on release layer 46, such as by coating, th insulating layer 20 has a top surface 201 and a bottom surface 202 opposite top surface 201. top surface 121 of conductive material 12a may be substantially coplanar with bottom surface 202 of th insulating layer 20.

Referring to FIG. 46, portions of the th insulating layer 20 are removed, such as by photolithography, to form a plurality of openings 203 exposing portions of the conductive material 12 a. the openings 203 extend through the th insulating layer 20, i.e., the openings 203 extend between the top surface 201 and the bottom surface 202. the positions of the openings 203 may correspond to the positions of the conductive material 12 a. As shown in FIG. 46, the openings 203 are disposed directly above the conductive material 12 a.

Referring to fig. 47, seed layer 15 is formed or disposed on conductive material 12a and on top surface 201 of insulating layer 20 by, for example, sputtering in embodiments seed layer 15 may include a th conductive layer 151 and a second conductive layer 152. the material of th conductive layer 151 of seed layer 15 comprises a titanium-Tungsten (TiW) alloy that may be formed by Physical Vapor Deposition (PVD). the material of second conductive layer 152 of seed layer 15 comprises copper that may be formed by Physical Vapor Deposition (PVD) on th conductive layer 151. as shown in fig. 47, th conductive layer 151 of seed layer 15 is in contact with and/or electrically connected to conductive material 12 a.

Referring to fig. 48, an th metal layer 21 is formed in the opening 203 of the th insulating layer 20 and on the seed layer 15. the th metal layer 21 may be a patterned line structure (e.g., a redistribution layer (RDL)) and disposed on a top surface of the seed layer 15 and in the opening 203 of the th insulating layer 20. the th metal layer 21 has a top surface 211 and a bottom surface 212 opposite to the top surface 211. at the same time, a conductive material 12a is attached and electrically connected to the bottom surface 212 of the th metal layer 21 through the seed layer 15.

Referring to fig. 49, portions of seed layer 15 not covered by th metal layer 21 are removed by, for example, etching.

Referring to fig. 50, a second insulating layer 22, a second metal layer 23, a third insulating layer 24, a third metal layer 25, a fourth insulating layer 26, and at least Under Bump Metallurgy (UBM)27 are then formed on the insulating layer 20 and the metal layer 21 to form the wiring structure 2. in embodiments , if the carrier 44 and the release layer 46 are removed, the electronic device 1d of fig. 9 can be obtained.

Referring to fig. 51, the th semiconductor die 32 and the second semiconductor die 34 are electrically connected to the wiring structure 2. the th semiconductor die 32 is electrically connected to the third metal layer 25 of the wiring structure 2 through the th interconnection element 31 and the UBM 27 and in flip-chip bonding, and the second semiconductor die 34 is electrically connected to the third metal layer 25 of the wiring structure 2 through the second interconnection element 33 and the UBM 27 and in flip-chip bonding.

Referring to fig. 52, package 36 is formed or disposed on fourth insulating layer 26 of wiring structure 2 to encapsulate and cover th semiconductor die 32, th interconnection element 31, second semiconductor die 34, second interconnection element 33, and UBM 27.

Referring to fig. 53, the carrier 44 is removed.

Referring to fig. 54, the release layer 46 is removed. At the same time, the conductive material 12a becomes the electrical connection element 12. Next, a singulation process is performed to obtain an electronic device 3b (i.e., a semiconductor package) as shown in fig. 9. It should be noted that if the electronic device 3b of fig. 9 is subjected to the reflow process, the electrical connection elements 12 (i.e., the conductive materials 12a) become spherical due to cohesive force of reflow and melting to obtain an electronic device 3f (i.e., a semiconductor package structure) as shown in fig. 14.

Fig. 55-59 show or stages of embodiments of a method of manufacturing an electronic device 3c (e.g., a semiconductor package structure) of the present disclosure in embodiments the method is for manufacturing an electronic device such as the electronic device 3c (e.g., a semiconductor package structure) shown in fig. 11.

Referring to FIG. 55, a carrier 44 is provided, the carrier 44 has an th surface 441 and a second surface 442 opposite the th surface 441, and defines a plurality of openings 443 on the th surface 441, each of the openings 443 are blind holes recessed in the th surface 441 and not through the carrier 44.

Referring to fig. 56, a release layer 46 is formed or disposed in the opening 443 and on the -th surface 441 of the carrier 44 by, for example, coating.

Referring to fig. 57, conductive material 12a is formed or disposed on release layer 46 in opening 443 of carrier 44 by, for example, printing, the material of conductive material 12a includes a solder material such as a silver-tin (AgSn) alloy, in some embodiments of , the top surface of conductive material 12a may be substantially coplanar with the top surface of release layer 46 on surface 441 of carrier 44.

Referring to fig. 58, a template 50 is provided, the template 50 defines a plurality of through-holes 501, each through-holes 501 being located at a position corresponding to a position of each openings 443 of the carrier 44 in embodiments, each through-holes 501 of the template 50 are disposed directly over each openings 443 of the carrier 44, then, a plurality of solid core balls 40 (e.g., copper core balls) are provided, the solid core balls 40 being disposed through the through-holes 501 of the template 50 over the conductive material 12a in the openings 443 of the carrier 44.

Referring to fig. 59, the template 50 is removed. Next, a pressing plate is provided to press the solid core ball 40 downward so that the solid core ball 40 is buried in the conductive material 12 a. Next, the stages subsequent to fig. 59 are similar to those shown in fig. 20 to 29, thus forming the electronic device 3c shown in fig. 11. It should be noted that if the electronic device 3c of fig. 11 is subjected to the reflow process, the electrical connection elements 12 (i.e., the conductive materials 12a) become spherical due to cohesive force of reflow and melting to obtain an electronic device 3g (i.e., a semiconductor package structure) as shown in fig. 15.

Unless otherwise specified, spatial descriptions such as "above," "below," "upper," "left," "right," "lower," "top," "bottom," "vertical," "horizontal," "side," "above," "below," "upper," "on … …," "under … …," and the like are directed relative to the orientation shown in the figures. It is to be understood that the spatial descriptions used herein are for purposes of illustration only and that actual implementations of the structures described herein may be spatially arranged in any orientation or manner, provided that the advantages of the embodiments of the present disclosure are not so arranged.

As used herein, the terms "substantially", "substantially" and "about" are used to describe and explain minor variations. When used in conjunction with an event or circumstance, the terms may refer to instances in which the event or circumstance occurs specifically, and instances in which the event or circumstance occurs in close proximity. For example, when used in conjunction with numerical values, the term can refer to a range of variation of less than or equal to ± 10% of the stated numerical value, such as less than or equal to ± 5%, less than or equal to ± 4%, less than or equal to ± 3%, less than or equal to ± 2%, less than or equal to ± 1%, less than or equal to ± 0.5%, less than or equal to ± 0.1%, or less than or equal to ± 0.05%. For example, two numerical values are considered to be "substantially" identical or equal if the difference between the two numerical values is less than or equal to ± 10% (e.g., less than or equal to ± 5%, less than or equal to ± 4%, less than or equal to ± 3%, less than or equal to ± 2%, less than or equal to ± 1%, less than or equal to ± 0.5%, less than or equal to ± 0.1%, or less than or equal to ± 0.05%) of the mean of the values.

Two surfaces can be considered co-planar or substantially co-planar if the displacement between the two surfaces is no greater than 5 μm, no greater than 2 μm, no greater than 1 μm, or no greater than 0.5 μm.

As used herein, the singular terms " (a/an)" and "the" may include plural referents unless the context clearly dictates otherwise.

As used herein, the terms "conductive", "electrically conductive", and "electrical conductivity" refer to the ability to carry current.an electrically conductive material generally refers to those materials that exhibit little or zero resistance to the flow of current. measures of electrical conductivity are Western seeds/meter (S/m.) generally, an electrically conductive material is materials having an electrical conductivity greater than about 104S/m (e.g., at least 105S/m or at least 106S/m.) the electrical conductivity of a material can sometimes vary with temperature.

It is to be understood that such range format is used for convenience and brevity, and should be interpreted flexibly to include not only the numerical values explicitly recited as the limits of the range, but also to include all the individual numerical values or sub-ranges encompassed within that range as if each numerical value and sub-range is explicitly recited.

While the present disclosure has been described and illustrated with reference to particular embodiments thereof, such description and illustration are not intended to be limiting. It should be understood by those skilled in the art that various changes may be made and equivalents substituted without departing from the true spirit and scope of the disclosure as defined by the appended claims. The illustrations may not necessarily be drawn to scale. Due to manufacturing processes and tolerances, there may be a distinction between artistic renditions in this disclosure and actual devices. There may be other embodiments of the disclosure that are not specifically illustrated. The specification and drawings are to be regarded in an illustrative rather than a restrictive sense. Modifications may be made to adapt a particular situation, material, composition of matter, method, or process to the objective, spirit and scope of the present disclosure. All such modifications are intended to be within the scope of the appended claims. Although the methods disclosed herein have been described with reference to particular operations performed in a particular order, it should be understood that these operations may be combined, sub-divided, or reordered to form equivalent methods without departing from the teachings of the present disclosure. Accordingly, unless specifically indicated herein, the order and grouping of the operations is not a limitation of the present disclosure.