阅读说明：本技术 信号开关装置 (Signal switch device ) 是由 陈智圣 李宗翰 赵传珍 于 2018-09-26 设计创作，主要内容包括：一种信号开关装置,包括信号控制开关、开关电路、隔离电容以及突波电流抑制电路。信号控制开关耦接在第一信号收发端与第二信号收发端间,依据第一控制信号以被导通或断开。开关电路具有至少一第一晶体管,开关电路的第一端耦接至第一信号收发端,并受控于第二控制信号以被导通或断开。隔离电容耦接在开关电路的第二端以及参考电位端间。突波电流抑制电路具有至少一第二晶体管,突波电流抑制电路耦接在开关电路的第二端与参考电位端间。第二晶体管于突波电流产生时,抑制突波电流,并于信号开关装置正常操作时依据第一偏压电压被断开。(A signal switch device comprises a signal control switch coupled between a signal transceiver terminal and a second signal transceiver terminal and turned on or off according to a control signal, an isolation capacitor having at least a transistor, a terminal coupled to a signal transceiver terminal and controlled by the second control signal to be turned on or off, and a surge current suppressing circuit having at least a second transistor, the surge current suppressing circuit coupled between the second terminal of the switch circuit and a reference potential terminal, the second transistor suppressing surge current when the surge current is generated and turned off according to a bias voltage when the signal switch device is operating normally.)

An signal switching device, comprising:

a signal control switch coupled between the st signal transceiver terminal and the second signal transceiver terminal for being turned on or off according to st control signal;

a switch circuit having at least a transistor, wherein a terminal of the switch circuit is coupled between the signal transceiver terminal and the signal control switch, and the switch circuit is controlled by second control signal to be turned on or off;

a isolation capacitor coupled between the second terminal of the switch circuit and a reference potential terminal

a surge current suppression circuit having at least second transistor, the surge current suppression circuit coupled between the second terminal of the switch circuit and the reference potential terminal, the at least second transistor for suppressing the surge current when the surge current is generated and being turned off according to bias voltage when the signal switch device is operating normally.

2. The signal switching device of claim 1 wherein the at least transistor and the at least second transistor are both enhancement mode transistors or both depletion mode transistors.

3. The signal switching device of claim 1 wherein the signal controlled switch is turned on or off in opposition to the switch circuit during normal operation of the signal switching device.

4. The signal switching device of claim 1, wherein when the at least st transistors are plural, the th transistors are connected in series between the th transceiving terminal and the th isolation capacitor, and control terminals of the th transistors commonly receive the second control signal.

5. The signal switching device as claimed in claim 1, wherein the surge current suppression circuit further comprises:

a th bias voltage generator coupled to the control terminal of the at least second transistor for generating the th bias voltage.

6. The signal switching device as claimed in claim 5, wherein the -th bias voltage generator comprises:

at least inverter connected in series between the control terminal of the at least second transistor and the internal node, and

a delay circuit coupled to the internal node;

the delay circuit is configured to provide a low voltage level to the internal node for at least hours when a surge current is generated, and to provide a input voltage to the internal node to generate the th bias voltage according to a reference voltage when the signal switching device is operating normally.

7. The signal switching device of claim 6 wherein the delay circuit comprises a resistor and a capacitor serially connected between the reference voltage receiving terminal and the reference potential terminal, and the internal node is coupled between the resistor and the capacitor.

8. The signal switching device as claimed in claim 5, wherein the -th bias voltage generator comprises:

transmission line, its terminal is connected to the control terminal of the at least second transistor, its terminal is connected to the reference potential terminal or reference voltage receiving terminal.

9. The signal switching device as claimed in claim 5, wherein the -th bias voltage generator comprises:

resistor, its terminal is coupled to the control terminal of the at least second transistor, and its terminal is coupled to the reference potential terminal or reference voltage receiving terminal.

10. The signal switching device of claim 9 wherein said resistor has another terminal coupled to said reference potential terminal, said at least second transistor has a terminal coupled to said second terminal of said switching circuit, said at least second terminal coupled to said reference potential terminal, said bias voltage generator further comprising:

capacitor, its terminal is coupled to the control terminal of the at least second transistor, its terminal is coupled to the terminal of the at least second transistor.

11. The signal switching device as claimed in claim 5, wherein the -th bias voltage generator comprises:

inverter, having:

a power supply terminal to receive an operating voltage;

an input end; and

an output terminal coupled to the control terminal of the at least second transistor, an

delay circuit, coupled to the input end of the inverter, for providing a low voltage level for at least time when the surge current is generated, so that the voltage level at the output end of the inverter is substantially equal to the voltage level of the operating voltage.

12. The signal switching device as claimed in claim 11, wherein the -th bias voltage generator further comprises:

a turn-on voltage controller coupled to the th transceiver terminal for generating the operation voltage according to the voltage at the th transceiver terminal.

13. The signal switching device of claim 12, wherein the turn-on voltage controller comprises:

and N diodes connected in series, wherein an anode of the th diode is coupled to the th end or the second end of the at least th transistor, and a cathode of the Nth diode is coupled to a power supply end of the inverter.

14. The signal switching device as claimed in claim 11, wherein the delay circuit comprises a resistor and a capacitor serially connected between the voltage receiving terminal and the reference terminal.

15. The signal switching device according to claim 11, wherein the terminal of the at least second transistor is coupled to the second terminal of the switch circuit, the second terminal of the at least second transistor is coupled to the reference potential terminal, and a power supply terminal of the inverter is coupled to the terminal of the at least second transistor, the bias voltage generator further comprising:

resistor connected in series between the voltage receiving terminal and the th terminal of the th transistor of or between the voltage receiving terminal and the second terminal of the th transistor of .

16. The signal switch device as claimed in claim 15, wherein the voltage receiving terminal is configured to receive bias voltage, and the potential of the bias voltage is changed according to the turning on or off of the th switch circuit.

A signal switching device of the type 17, , comprising:

a signal control switch coupled between the signal transceiver terminal and the second signal transceiver terminal for being turned on or off according to a control signal;

a switch circuit having at least a transistor, wherein a terminal of the switch circuit is coupled between the signal transceiver terminal and the signal control switch, and the switch circuit is controlled by second control signal to be turned on or off;

a isolation capacitor coupled in series with the signal control switch between the signal transceiver terminal and the second signal transceiver terminal, such that the signal control switch is coupled to the of the signal transceiver terminal and the second signal transceiver terminal through the isolation capacitor;

a second isolation capacitor coupled between the second terminal of the switch circuit and the reference potential terminal of

a surge current suppression circuit having at least a second transistor, the surge current suppression circuit having and second terminals coupled to the and second terminals of the isolation capacitor, respectively, the second transistor for suppressing the surge current when the surge current is generated, the second transistor for being turned off according to a bias voltage when the signal switch device is operating normally.

18. The signal switching device of claim 17, further comprising:

a second inrush current suppression circuit having at least a third transistor, the second inrush current suppression circuit coupled between the second terminal of the switch circuit and the reference potential terminal, the at least a third transistor for suppressing the inrush current when the inrush current is generated and being turned off according to a second bias voltage when the signal switch device is operating normally.

A signal switching device of the type 19, , comprising:

a signal control switch coupled between the st signal transceiver terminal and the second signal transceiver terminal for being turned on or off according to st control signal;

a switch circuit having at least a transistor, wherein a terminal of the switch circuit is coupled between the signal transceiver terminal and the signal control switch, and the switch circuit is controlled by second control signal to be turned on or off;

a isolation capacitor coupled between the second terminal of the switch circuit and a reference potential terminal;

a surge current suppression circuit having at least second transistor, the surge current suppression circuit being coupled between the second terminal of the switch circuit and the reference potential terminal, the at least second transistor being configured to suppress the surge current when the surge current is generated and to be turned off according to bias voltage when the signal switch device is operating normally;

a second signal control switch coupled between the third signal transceiving terminal and the second signal transceiving terminal for being turned on or off according to the third control signal;

a second switch circuit having at least third transistors, the terminal of the second switch circuit being coupled between the third signal transceiving terminal and the second signal control switch, the second switch circuit being controlled by fourth control signal to be turned on or off;

a second isolation capacitor coupled between the second terminal of the second switch circuit and the reference potential terminal, and

a second inrush current suppression circuit having at least a fourth transistor, the second inrush current suppression circuit coupled between the second terminal of the second switch circuit and the reference potential terminal, the at least a fourth transistor for suppressing the inrush current when the inrush current is generated and being turned off according to a second bias voltage when the signal switch device is operating normally.

20. The signal switching device of claim 19 wherein the at least th transistor, the at least second transistor, the at least third transistor, and the at least fourth transistor are all enhancement mode transistors or all depletion mode transistors.

Technical Field

The present invention relates to signal switch devices, and more particularly, to signal switch devices capable of effectively suppressing surge current when the surge current is generated.

Background

In the known technical field, the signal switch device may be provided with a corresponding shunt circuit at the signal transceiving end. When the signal transmitting and receiving end does not execute the signal transmitting and receiving action, the corresponding shunt circuit is switched off, and on the contrary, when the signal transmitting and receiving end does not execute the signal transmitting and receiving action, the corresponding shunt circuit is switched on to avoid the signal from being transmitted to the signal transmitting and receiving end which does not act by mistake.

It should be noted that when a surge current occurs in the signal switch device of the prior art, in order to prevent the electronic components in the signal switch device from being damaged by the surge current, it is often necessary to provide a surge current protection device to suppress the surge current. However, the surge current protection device in the prior art usually requires a large circuit area, and the parasitic effect thereof also causes the signal quality of the high frequency signal transmitted by the signal switching device to be degraded, which has negative effects in terms of both product cost and product performance.

Disclosure of Invention

The invention provides kinds of signal switch devices, which can effectively restrain surge current when surge current is generated.

The present invention provides a signal switch device including a signal control switch, a switch circuit, a 0 isolation capacitor and a 1 inrush current suppression circuit, wherein the 2 th signal control switch is coupled between the 3 th signal transceiving terminal and the second signal transceiving terminal for being turned on or off according to a 4 th control signal, the 5 th switch circuit has at least 6 th 7 th transistor, a 8 th switch circuit has a 9 th terminal coupled between the th signal transceiving terminal and the 0 th signal control switch, a 1 th switch circuit is controlled by a second control signal to be turned on or off, a 2 isolation capacitor is coupled between a second terminal of the th switch circuit and a reference potential terminal, a inrush current suppression circuit has at least second transistor, a inrush current suppression circuit is coupled between a second terminal of the th switch circuit and the reference potential terminal, at least second transistor is used for suppressing inrush current generation and normal operation of the switch device according to a biasing voltage .

Another switching device according to the present invention comprises a switching control switch, an switching circuit, an isolating capacitor, a second isolating capacitor and an surge current suppression circuit, wherein the switching control switch is coupled between the signal transceiver terminal and the second signal transceiver terminal for being turned on or off according to a second control signal, the switching circuit comprises at least a and a transistor, the terminal of the switching circuit is coupled between the signal transceiver terminal and the 1 signal control switch, the switching circuit is controlled by a second control signal for being turned on or off, the isolating capacitor and the signal control switch are coupled in series between the signal transceiver terminal and the second signal transceiver terminal, so that the switching control switch is coupled to the signal transceiver terminal through the isolation capacitor, the isolation capacitor is coupled to the signal transceiver terminal and the second signal transceiver terminal, the switching control switch is coupled to the second signal transceiver terminal for generating a surge current according to the second signal voltage, the circuit has a second bias voltage, and the second circuit is coupled to the second terminal of the second circuit when the second surge current suppression circuit is normally operated, the second isolation switch is coupled between the and the second isolation capacitor is coupled.

A signal switching device of the present invention includes a signal control switch, a 0 switch circuit, a isolation capacitor, a surge current suppression circuit, a second signal control switch, a second switch circuit, a second isolation capacitor and a second surge current suppression circuit.A signal control switch is coupled between the signal transceiver terminal and the second signal transceiver terminal for being turned on or off in accordance with a control signal.A switch circuit has at least a second transistor, a terminal of a switch circuit is coupled between an signal transceiver terminal and a 1 signal control switch, a switch circuit is controlled by a second control signal to be turned on or off.A isolation capacitor is coupled between the second terminal of the switch circuit and a reference potential terminal.A surge current suppression circuit has at least , a second switch 72 is coupled between the second terminal of the switch circuit and the reference potential terminal for suppressing a surge current when the second switch circuit is turned on or off in accordance with a second control signal, the second switch circuit has at least coupled between the second terminal of the second switch circuit and the second switch circuit for suppressing a second surge current when the second surge current is coupled between the second terminal of the second switch circuit and the second switch circuit, the second switch circuit is coupled between the second switch circuit for generating a , the second surge current suppression circuit is coupled between the second switch circuit and the second switch circuit for generating a third surge voltage, the second surge current suppression circuit is coupled between the second switch circuit and the second switch circuit for generating a , the second surge voltage control switch circuit for generating a , the second surge voltage suppressing the second surge voltage when the second surge voltage suppressing circuit is coupled between the second switch circuit and the second switch circuit, the second switch circuit is coupled between the second switch circuit, the second switch circuit is coupled between the second switch circuit and the second switch circuit, the second switch circuit for generating a , the second switch circuit for generating a third switch circuit for generating a , the second surge voltage generating a 36.

In order to make the aforementioned and other features and advantages of the invention more comprehensible, embodiments accompanied with figures are described in detail below.

Drawings

FIG. 1 is a schematic diagram of a signal switching device according to an embodiment of the present invention.

Fig. 2A is a schematic diagram of a bias voltage generation mechanism according to an embodiment of the present invention.

Fig. 2B-2G are circuit diagrams of embodiments of bias voltage generators according to embodiments of the present invention.

Fig. 3 is a schematic diagram of another exemplary embodiment of a signal switch device according to the present invention.

Fig. 4 is a schematic diagram of another exemplary embodiment of a signal switch device according to the present invention.

Fig. 5A and 5B are schematic diagrams of signal switching devices according to different embodiments of the present invention.

Fig. 6 is a schematic diagram of a signal switching device according to another embodiment of the present invention.

[ notation ] to show

100. 300, 400, 500, 600: signal switch device

110. 310, 420, 530, 632, 642: switching circuit

120. 330, 430, 510, 520, 612, 622: surge current suppression circuit

210. 320, 410, 652, 662: bias voltage generator

322: conduction voltage controller

IV1-IV4, 323, 412: inverter with a capacitor having a capacitor element

321. 411, 612, 622: delay circuit

RX1, RX2, RFC: signal receiving and transmitting terminal

T1-T4, T11-T13, T41, T42, TA 1: transistor with a metal gate electrode

VC1, VC 2: control signal

ISC1, ISCA1, ISCB1, ISCB 2: isolation capacitor

SW1, SW 2: signal control switch

VB1, VB2, Vbias: bias voltage

GND: reference potential terminal

VRN: voltage receiving terminal

R1, R221, R231, R241, R251, R41, R1-R6, HR: resistance (RC)

RUP1-RUP 5: bias resistor

C1, C221, C231, C251, C41: capacitor with a capacitor element

REF: internal node

VCC: reference voltage

D1-DN: diode with a high-voltage source

ST: signal

VD: operating voltage

VP: electric potential

W1: transmission conductor

Detailed Description

Referring to fig. 1, fig. 1 is a schematic diagram of a signal switch device according to an embodiment of the invention, the signal switch device 100 includes a signal control switch SW1, a switch circuit 110, an isolation capacitor ISC1 and a surge current suppression circuit 120, the signal control switch SW1 is coupled between a signal transceiving terminal RX1 and a signal transceiving terminal RFC, the signal control switch SW1 is controlled by a control signal VC1 to be turned on or off, a first terminal 1 of the switch circuit 110 is coupled between the signal transceiving terminal RX1 and the signal control switch SW1, a second terminal of the switch circuit 110 is coupled between the first terminal 1 of the isolation capacitor ISC1, the switch circuit 110 is controlled by the control signal VC1 to be turned on or off, in the present embodiment, the switch circuit 110 has at least a transistor T1, wherein the first terminal 1 of the transistor T1 is coupled between the signal transceiving terminal RX1 and the signal control switch SW 72, the second terminal of the transistor T1 is coupled between the signal transceiving terminal RX1 and the signal control switch VC1, and the switch circuit receives the isolation switch VC1, the switch 1, and the switch circuit receives the switch circuit 1, and the switch control transistor T1.

In the present embodiment, the signal transceiving terminals RX1 and RFC can be used to receive or transmit Radio Frequency (RF) signals.

In addition, the inrush current suppression circuit 120 has a terminal and a second terminal, a terminal coupled between the terminal of the isolation capacitor ISC1 and the second terminal of the switch circuit 110, a second terminal coupled to the reference potential terminal GND, and a second terminal coupled to the reference potential terminal GND. the inrush current suppression circuit 120 has at least a transistor T2, wherein the terminal of the transistor T2 is coupled to the terminal of the inrush current suppression circuit 120, a second terminal of the transistor T2 is coupled to the second terminal of the inrush current suppression circuit 120, and a control terminal of the transistor T2 is configured to receive the bias voltage vb1. that is, the inrush current suppression circuit 120 and the isolation capacitor ISC1 thereof are configured to form a shunt (shunt) path, the isolation capacitor ISC 3527 is configured to receive the bias voltage VB 14 when the switch circuit is in parallel with the switch circuit 847, and the switch circuit is configured to receive the bias voltage VB 14 and to maintain the plurality of the inrush current suppression transistors VB 14 in a normal state according to the VB voltage VB 14, VB 14 and the VB 14 is maintained by the isolation capacitor ISC 14.

For the details of the operation of the switch device 100, when a signal transceiving operation is to be performed between the transceiving terminals RX1 and RFC, the switch SW1 can be turned on according to the control signal VC1, so that a signal can be transmitted between the transceiving terminals RX1 and RFC, and at the same time, the transistor T1 in the switch circuit 110 can be turned off according to the control signal VC2 to prevent the signal from leaking to the reference potential terminal GND to cause a loss of energy, whereas, when a signal transceiving operation is not to be performed between the transceiving terminals RX1 and RFC, the switch SW1 can be turned off according to the control signal VC1, so that a signal can be prevented from being transmitted between the transceiving terminals RX1 and RFC, while the transistor T1 in the switch circuit 110 can be turned on according to the control signal VC2 to shunt a signal leaking to the signal terminal RX1 through the off capacitor (Coff) of the switch SW1, and the switch SW 48 is turned on to prevent the signal transceiving operation when the switch SW 596 is normally operated in the off state, that the switch SW 59648 is normally controlled to switch SW 3926, and the switch SW is turned off when the parasitic signal transceiving operation is performed when the switch SW 596 is in the opposite state.

In another aspect , the effect of the inrush current suppression circuit 120 on the quality of the transmitted and received rf signal is reduced by maintaining the transistor T2 in the inrush current suppression circuit 120 turned off during normal operation of the signal switching device 100.

It should be noted that when a surge current is generated in the signal switch device 100 (during abnormal operation), the transistor T2 in the surge current suppression circuit 120 can be used to suppress the surge current and make the circuit elements in the signal switch device 100 and the circuit elements connected to the signal switch device 100 less susceptible to the surge current. In the present embodiment, the transistor T2 can be turned on at the moment of the occurrence of the surge current, and the surge current is suppressed by providing a channel. The transistor T2 can conduct the surge current to the reference potential terminal GND to suppress the surge current.

In addition, in another embodiment of the present invention, the switch circuit 110 further includes a coupling capacitor coupled between the terminal of the transistor T1 and the control terminal VC2, so that the transistor T1 can pass more surge current.

, to reduce the complexity of the process, in the embodiment of the present invention, the transistors T1 and T2 may be both enhancement transistors or both depletion transistors, and in another embodiment of the present invention, the transistors T1 and T2 may be both N-type transistors or both P-type transistors.

Referring to fig. 1 and 2A, wherein fig. 2A is a schematic diagram of a bias voltage generation mechanism according to an embodiment of the present invention, in an embodiment of the present invention, a bias voltage VB1 received by a transistor T2 may be provided by a bias voltage generator 210. regarding the implementation of the bias voltage generator 210, referring to the circuit diagram of the implementation of the bias voltage generator illustrated in fig. 2B-2G, the bias voltage generator 210 includes two serially connected inverters (inverter) IV1, IV2 and a delay circuit composed of a resistor R221 and a capacitor C221. in fig. 2B, the bias voltage generator 210 is serially connected between a control terminal of the transistor T2 and an internal node REF 6. an output terminal of an inverter IV1 provides a bias voltage VB1 and is coupled to a control terminal of the transistor T2, an input terminal of the inverter IV1 is coupled to an output terminal of the inverter IV2, an input terminal of the inverter IV 39 2 is coupled to an internal node VCC 46221 and a capacitor C46221, which is serially connected to a high voltage VCC reference node vref 221, and a high voltage is provided by a resistor JFET 9, and a high voltage reference node vref 99, and a high voltage is coupled to a high voltage reference node vref transistor C for generating a high voltage potential voltage, the FET 12, the FET 221 is coupled to a high voltage, the FET 221 is coupled to a high voltage FET 12, the FET 221, the FET may be coupled to a high voltage FET 12, and the FET 12, the FET 221, the FET may be coupled to a high voltage reference node of the FET may be coupled to a high voltage FET 210, and the FET may be coupled to a high voltage FET.

Fig. 2C is a circuit diagram of another embodiment of the bias voltage generator according to the present invention, in which the bias voltage generator 210 includes inverters iv1 generating bias voltages VB1 at output terminals, the coupling manner and the operation principle of the resistor R231 and the capacitor C231 of the present embodiment are similar to those of the resistor R221 and the capacitor C221 of fig. 2B, respectively, and are not described herein again, the output terminal of the inverter IV1 of the present embodiment provides a bias voltage VB1 with a low voltage level and is coupled to the control terminal of the transistor T2, and the input terminal of the inverter IV1 is coupled to the internal node ref.

In the embodiment of fig. 2B and 2C, when the reference voltage VCC is generated, the delay circuit can provide the input voltage to the internal node ref according to the reference voltage VCC, when the signal switching device 100 operates normally, and when the reference voltage VCC is in a steady state, the delay circuit continuously provides the input voltage equal to the reference voltage VCC to the inverter IV1, or IV1 and IV2, and makes the inverter IV1 generate the bias voltage VB1 that substantially keeps the transistor T2 turned off, so as to reduce the influence of the surge current suppression circuit 120 on the quality of the received rf signal.

In FIG. 2D, the bias voltage generator 210 includes a resistor R241, a resistor R241 having an terminal coupled to the reference voltage terminal for receiving the reference voltage VCC, and a terminal coupled to the control terminal of the transistor T2 for providing the bias voltage VB1. in this embodiment, the transistor T2 may be a P-type enhancement transistor, and when the signal switch device 100 operates normally, the resistor R241 provides the bias voltage VB1 equal to the reference voltage VCC, and the transistor T2 is kept turned off.

In FIG. 2E, the bias voltage generator 210 is formed by a transmission line W1, a transmission line W1 is connected between the control terminal of the transistor T2 and the reference potential terminal GND. when the signal switching device 100 operates normally, the bias voltage VB1 generated by the transmission line W1 is equal to the voltage at the reference potential terminal GND and provides the bias voltage VB1 to the control terminal of the transistor T2. in this embodiment, the transistor T2 may be an enhancement mode transistor of the N-type. in another embodiment, the terminal of the transmission line W1 may be connected to the reference voltage receiving terminal for receiving the reference voltage VCC, the other thereof is connected to the control terminal of the transistor T2, and the transistor T2 may be an enhancement mode transistor of the P-type.

In FIG. 2F, the bias voltage generator 210 includes a resistor R241, a terminal of the resistor R241 generates a bias voltage VB1, a terminal of the resistor R241 is coupled to the GND terminal, a bias voltage VB1 generated by the resistor R241 is equal to the voltage on the GND terminal, and provides the bias voltage VB1 to the control terminal of the transistor T2. in this embodiment, the transistor T2 may be an N-type enhancement transistor.

In fig. 2G, the bias voltage generator 210 includes a capacitor C251 and a resistor R251, wherein the end of the capacitor C251 is coupled to the end of the transistor T2, the second end of the capacitor C251 is coupled to the control end of the transistor T2 and the end of the resistor R251, the second end of the resistor R251 is coupled to the GND terminal, and generates the bias voltage vb1, and the transistor T2 may be an N-type enhancement transistor in this embodiment.

In the embodiment of fig. 2D to 2G, when the signal switching device 100 operates normally, the bias voltage generator 210 generates the bias voltage VB1 that substantially keeps the transistor T2 turned off by the reference voltage VCC or the voltage at the reference potential terminal GND, so as to reduce the influence of the inrush current suppression circuit 120 on the quality of the transmitted rf signal.

Referring to fig. 3, fig. 3 is a schematic diagram of a signal switch device according to another embodiment of the invention, the signal switch device 300 includes a signal control switch SW1, a switch circuit 310, an isolation capacitor ISC1, a surge current suppression circuit 330 and a bias voltage generator 320, the coupling manner and the operation principle of the signal control switch SW1, the isolation capacitor ISC1 and the surge current suppression circuit 330 of the present embodiment are similar to those of the signal control switch SW1, the isolation capacitor ISC1 and the surge current suppression circuit 120 of fig. 1, and are not repeated herein.

In the present embodiment, a plurality of transistors may be included in the switch circuit 310, and the number of transistors in the switch circuit 310 may be set by a designer according to actual requirements without fixed limitations.

In addition, the bias voltage generator 320 includes a delay circuit 321, a turn-on voltage controller 322 and an inverter 323, the turn-on voltage controller 322 may include N diodes D1-DN connected in series, wherein an anode of the diode D1 is coupled to the transceiver terminal RX1, a cathode of the diode DN is coupled to the power terminal of the inverter 323, and N is a positive integer greater than or equal to 1. in another embodiment, an anode of the diode D1 may be coupled to any terminal in the series path of the switch circuit 310, such as the rd or second terminal of the switch circuit 310, or the th or second terminal of any transistors in the series transistors T11-T13 in the switch circuit 310. in another embodiment, the turn-on voltage controller 322 detects the voltage at the transceiver terminal RX1 and is turned on when the voltage at the transceiver terminal RX1 is greater than the sum of the turn-on voltages of the diodes D1-DN 7 to provide a voltage VD to the power terminal of the inverter 323.

The input terminal of the inverter 323 receives the signal ST generated by the delay circuit 321, the output terminal of the inverter 323 generates the bias voltage vb1 according to the signal ST, the delay circuit 321 includes a resistor R1 and a capacitor C1, the terminal of the resistor R1 is coupled to the voltage receiving terminal VRN for receiving the reference voltage VCC, the second terminal of the resistor R1 is coupled to the terminal of the capacitor C1, the second terminal of the capacitor C1 is coupled to the reference potential terminal gnd, and the internal node of the resistor R1 coupled to the capacitor C1 generates the signal ST.

Please note that, when the surge current is generated, the delay circuit provides the low voltage level maintained at least for a certain time to the internal node coupled to the resistor R1 and the capacitor C1, and makes the inverter 323 generate the bias voltage VB1 for substantially turning on the transistor T2, at this time, the potential of the bias voltage VB1 is substantially equal to the potential of the operating voltage VD at the power source terminal of the inverter 323, so , the surge current can be suppressed through the turned-on transistor T2, thereby effectively protecting the circuit device from being damaged by the surge current.

In contrast, when the signal switch device 300 is in the normal operation state (when no surge current is generated), the signal ST generated by the delay circuit 321 is substantially equal to the reference voltage VCC, so that the inverter 323 generates the bias voltage vb1 substantially equal to the reference potential terminal GND, so , the transistor T2 can be kept turned off to reduce the influence of the surge current suppression circuit 330 on the quality of the transmitted and received rf signal.

Referring to fig. 4, fig. 4 is a schematic diagram of a signal switch device according to another embodiment of the present invention, the signal switch device 400 includes a signal control switch SW1, a switch circuit 420, an isolation capacitor ISC1, a surge current suppression circuit 430, and a bias voltage generator 410, the coupling manner and the operation principle of the signal control switch SW1, the switch circuit 420, the isolation capacitor ISC1, and the surge current suppression circuit 430 of the present embodiment are respectively similar to the signal control switch SW1, the switch circuit 110, the isolation capacitor ISC1, and the surge current suppression circuit 120 of fig. 1, and are not repeated herein.

In addition, the delay circuit 411 is composed of a resistor R and a capacitor C, wherein an internal node coupled between the resistor R and the capacitor C generates a second terminal of the signal resistor R coupled to the voltage receiving terminal VRN for receiving the bias voltage Vbias, a second terminal of the resistor R is coupled to the 0 th terminal and the internal node of the capacitor C, a second terminal of the capacitor C is coupled to the reference potential terminal, and the second terminal of the resistor R and the 1 st terminal of the capacitor C are coupled together to the internal node and the input terminal of the inverter 412, a 2 nd terminal of the resistor R is further coupled to the 3 rd terminal of the resistor HR, a second terminal of the resistor HR is coupled between the second terminal of the switch circuit 420 and the second terminal of the transistor T for providing the bias voltage Vbias, and the switch circuit includes a plurality of transistors T and T, wherein the switch circuit includes a switch circuit 310 connected in series to the second terminal of the transistor T, and a resistor R are coupled to the second terminal of the switch 420, and the switch HR is coupled to the second terminal of the transistor T in series.

When a surge current occurs, the delay circuit 411 provides a low voltage level that is maintained for at least hours to the internal node coupled to the resistor R41 and the capacitor C41, so that the output terminal of the inverter 412 generates a bias voltage VB1 whose potential is substantially equal to the operating voltage VD, and the transistor T2 is turned on according to the bias voltage VB1, so that the surge current can be conducted to the reference potential terminal GND through the turned-on transistor T2 to perform a suppression operation, thereby effectively protecting circuit elements from being damaged by the surge current.

In contrast, in the normal operation state of the signal switching device 400 (no inrush current occurs), the delay circuit 411 provides a signal substantially equal to the bias voltage Vbias to the input terminal of the inverter 412, causes the inverter 412 to generate the bias voltage VB1 substantially equal to the reference potential terminal GND, and causes the transistor T2 to be maintained in the off state according to the bias voltage VB 1.

It is worth mentioning that the bias voltage Vbias may have a different potential from the reference voltage VCC in the previous embodiment, and in the embodiment of the present invention, the bias voltage Vbias may have a potential smaller than the reference voltage VCC. in another embodiment , the bias voltage Vbias may be changed in coordination with the turning on or off of the switch circuit 420, so as to optimize the high frequency operation characteristics of the signal switch device 400.

Referring to fig. 5A and 5B, fig. 5A and 5B are schematic diagrams of a signal switch device according to various embodiments of the present invention, respectively, the coupling manner and operation principle of the signal control switch SW, the switch circuit 530, the isolation capacitor ISC, and the surge current suppression circuit 510 of fig. 5A and 5B are similar to those of the signal control switch SW, the switch circuit 110, the isolation capacitor ISC, and the surge current suppression circuit 120 of fig. 1, and are not repeated herein, in fig. 5A, the signal switch device 500 further includes an isolation capacitor ISCA and a surge current suppression circuit 520, the isolation capacitor ISCA and the signal control switch SW are connected in series between the signal transceiving terminal RX and the signal transceiving terminal RFC, one end of the isolation capacitor ISCA is coupled to the signal transceiving terminal RX, the other end of the isolation capacitor ISCA is coupled to the second end of the signal control switch SW, the signal control switch SW is coupled to the signal transceiving terminal RX through the isolation capacitor a, the other end of the isolation capacitor ISCA is coupled to the second end of the signal control switch SW, the signal control switch SW is coupled to the signal transceiving terminal RX, the second end of the signal switch ISCA 520, the isolation capacitor ISCA is coupled to the second end of the signal transceiver RX, the isolation capacitor ISCA is coupled to the isolation switch SW, the isolation capacitor ISCA is coupled to the signal switch SW, the isolation capacitor ISCA is coupled to the second end of the isolation capacitor ISCA, the isolation transistor 520, the isolation switch SW is coupled to the isolation switch circuit 500, and the isolation capacitor ISCA, the isolation transistor 500 is coupled to the isolation transistor 500, and the isolation transistor 500 is coupled to the second end of the isolation transistor 500, the isolation.

When a surge current occurs in the signal switch device 500 (e.g., at the signal transceiver RX 1), the transistor TA1 can be turned on corresponding to the surge current, and similar to the surge current suppressing circuit 120 in the previous embodiment, the surge current suppressing circuit 520 can generate a suppressing path of the surge current substantially parallel to the isolation capacitor ISCA1, so as to effectively guide and suppress the surge current and achieve the effect of protecting circuit elements.

Note that in the embodiments of the present invention, the transistors T1 and TA1 may be both enhancement transistors and may be both depletion transistors, and in another embodiment of the present invention , the transistors T1 and TA1 may be both N-type transistors or both P-type transistors.

Referring to fig. 5B, the main difference between fig. 5B and fig. 5A is that the end of the isolation capacitor ISCA1 is coupled to the signal transceiving end RFC, the other end of the isolation capacitor ISCA1 is coupled to the signal transceiving end RX1 through the signal control switch SW1, so that the signal control switch SW1 is indirectly coupled to the signal transceiving end RFC through the isolation capacitor ISCA1, the isolation capacitor ISCA1 and the inrush current suppression circuit 520 coupled in parallel therewith are connected in series between the signal control switch SW1 and the signal transceiving end RFC, when an inrush current occurs in the signal switching device 500 (e.g. at the signal transceiving end RFC), the transistor TA1 can be turned on corresponding to the inrush current to effectively suppress the inrush current and achieve the protection effect of the circuit elements.

Referring to fig. 6, fig. 6 is a schematic diagram of a signal switch device according to another embodiment of the present invention, the signal switch device 600 may be used for transmitting and receiving a high frequency signal, such as a radio frequency signal, the signal switch device 600 includes signal control switches SW, switch circuits 632, 642, isolation capacitors ISCB, and surge current suppression circuits 612, 622. the signal transceiver terminal RX, RFC, the signal control switch SW, the switch circuit 632, the isolation capacitors ISCB, and the surge current suppression circuit 612 of the present embodiment are coupled and activated in a manner similar to that of the signal control switch SW, the isolation capacitor ISC, and the surge current suppression circuit 120 of fig. 1, and the signal transceiver terminal RX, RFC, the signal control switch SW, the switch circuit 642, the isolation capacitor ISCB, and the surge current suppression circuit 622 of fig. 1, and are coupled and activated in a manner similar to that the signal control terminals RX, RFC, the signal control switch circuit 110, the isolation capacitors ISCB, and the surge current suppression circuit 622 of fig. 1, and are respectively connected to the signal switch SW, switch circuit 120 of the switch SW, switch circuit 120, and switch SW, and switch VC, and switch VC, switch, and switch, VC, and switch.

When the signal control switch SW1 is turned on, the transceiving operation of high frequency signals can be performed between the transceiving terminal RX1 and RFC, and at the same time, the signal control switch SW2 and the transistor T1 are turned off at the same time to prevent the signals on the transceiving terminal RX1 and the transceiving path of RFC from being interfered by the signals on the transceiving terminal RX2, and the transistor T3 is turned on to couple the transceiving terminal RX2 to the GND terminal, so that the step prevents the signals on the transceiving terminal RX2 from interfering with the signals on the transceiving terminal RX1 and the transceiving path of RFC.

In this embodiment, the signal switch device 600 may further include bias resistors RUP1-RUP5 respectively coupled between the transceiving terminals RX1 and RX2 and the RFC voltage and the voltage VP for biasing the transceiving terminals RX1 and RX2 to the voltage VP. In addition, the bias resistors RUP4-RUP5 are respectively coupled between the second terminals of the transistors T1 and T3 and the voltage VP to bias the second terminals of the transistors T1 and T3 to the voltage VP.

The signal switching device 600 may also include bias voltage generators 652, 662. The bias voltage generator 652 comprises inverters IV1, IV2 coupled in series, an input terminal of the inverter IV2 is coupled to the reference voltage terminal through a resistor to receive the reference voltage VCC, and is coupled to the reference potential terminal GND through a capacitor, an output terminal of the inverter IV1 provides the bias voltage VB1 to the control terminal of the transistor T2, and the transistor T2 is kept turned off under the condition of no surge current (e.g., when the signal switch device 600 is operating normally). The bias voltage generator 662 includes inverters IV3 and IV4, which are coupled in a manner similar to the operation of the inverters IV1 and IV2, and thus are not described herein again.

In addition, in the present embodiment, the switches SW1, SW2 and the transistors T1-T4 may be coupled in parallel with the resistors R1, R3, R2, R5, R4 and R6, respectively. In addition, in the embodiment, the resistors R1-R6 may be bypass resistors, and the transistors T1-T4 may be all enhancement transistors or all depletion transistors.

In other embodiments, the bias voltage generator 210 of fig. 2B to 2G, the bias voltage generator 320 of fig. 3, and the bias voltage generator 410 of fig. 4 may be used to generate the bias voltage VB1 or VB 2.

In summary, the signal switch device of the present invention provides a surge current suppressing circuit coupled in parallel with the isolation capacitor, and the transistor in the surge current suppressing circuit is kept in an off state under a normal state according to the received bias voltage, as shown in , when a surge current is generated on the signal switch device, the transistor in the surge current suppressing circuit can be turned on and a guiding channel is provided to suppress the surge current.

Although the present invention has been described with reference to the above embodiments, it should be understood that various changes and modifications can be made therein by those skilled in the art without departing from the spirit and scope of the invention.