阅读说明：本技术 摄像装置及电子设备 (Imaging device and electronic apparatus ) 是由 山本朗央 于 2018-06-05 设计创作，主要内容包括：提供一种容易进行池化处理的摄像装置。在摄像装置中,像素区域包括多个池化模块及输出电路,池化模块包括池化电路及比较模块,池化电路包括多个像素及运算电路,比较模块包括多个比较电路及判定电路。像素可以通过光电转换而取得第一信号,以任意倍率对第一信号进行乘法而生成第二信号。池化电路通过运算电路对多个第二信号进行加法而生成第三信号,比较模块通过比较多个第三信号而将最大的第三信号输出到判定电路,判定电路具有判定最大的第三信号而使其二值化,并生成第四信号。池化模块根据像素的数量进行池化处理,并输出进行了池化处理的数据。(An image pickup apparatus is provided with types of image pickup apparatuses in which a pixel region includes a plurality of pooling modules each including a pooling circuit and a comparison circuit, each pooling circuit including a plurality of pixels and an arithmetic circuit, and each comparison module including a plurality of comparison circuits each including a determination circuit and a determination circuit, each pixel can acquire a th signal by photoelectric conversion, and multiply a th signal at an arbitrary magnification to generate a second signal, each pooling circuit generates a third signal by adding the plurality of second signals by the arithmetic circuit, each comparison module outputs the largest third signal to the determination circuit by comparing the plurality of third signals, the determination circuit determines the largest third signal to binarize the third signal, and generates a fourth signal, and each pooling module performs pooling processing according to the number of pixels and outputs pooled data.)

An image pickup apparatus of , comprising:

a pixel region; and

the th circuit is used to make,

wherein the pixel region comprises a pooling module and an output circuit,

the pooling module includes a plurality of pooling circuits and a comparing module,

the pooling circuit includes a plurality of pixels and an arithmetic circuit,

the comparing module comprises a plurality of comparing circuits and a judging circuit,

the pixel has a function of obtaining an th signal by photoelectric conversion,

the pixel has a function of multiplying the th signal by an arbitrary magnification to generate a second signal,

the pooling circuit has a function of generating a third signal by adding a plurality of the second signals by the arithmetic circuit,

the comparison module has a function of selecting the largest third signal by comparing a plurality of the third signals and outputting it to the determination circuit,

the determination circuit has a function of determining the largest third signal, binarizing the third signal, and generating a fourth signal,

the th circuit controls the timing of outputting the fourth signal to the output circuit,

the pooling module performs pooling according to the number of the pixels,

and the pooling module outputs the fourth signal generated by the pooling process.

2. The image pickup device according to claim 1, further comprising a second circuit, a third circuit, an th wiring, a second wiring, and a third wiring,

wherein the pixel includes an th output terminal,

the operational circuit comprises an th transistor, a second transistor and a third transistor,

the second circuit is electrically connected to a plurality of the pixels extending in the row direction through the th wiring,

the third circuit is electrically connected to a plurality of the pixels extending in the column direction through the second wiring,

the third wiring is electrically connected to of a source and a drain of the th transistor, of the source and the drain of the second transistor, and of the source and the drain of the third transistor,

a gate of the th transistor is electrically connected to another of the source and the drain of the th transistor, the gate of the second transistor, the gate of the third transistor, and the th output terminal of the pixel included in the pooling circuit,

the third circuit has a function of outputting a selection signal to the second wiring,

the second circuit has a function of setting the pixel to an arbitrary magnification through the th wiring,

the th transistor has the same channel length as the second and third transistors,

the second transistor has a function of outputting the third signal which adds a plurality of the second signals by having the same width as a channel width of the th transistor,

and the third transistor has a length obtained by dividing the channel width of the th transistor by the number of pixels included in the pooling circuit, and thereby has a function of outputting the fifth signal having a size obtained by dividing the size of the third signal by the number of pixels.

3. The image pickup apparatus according to claim 1,

wherein the comparing module comprises th comparing circuit, second comparing circuit and current mirror circuit,

the comparison circuit includes a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, a input terminal, a second output terminal, and a fourth wiring,

the second output terminal of the th comparator circuit is electrically connected to the th input terminal of the second comparator circuit through the current mirror circuit,

the th input terminal is electrically connected to of the source and the drain of the fifth transistor, of the source and the drain of the seventh transistor, the gate of the fourth transistor, the gate of the fifth transistor, and the gate of the sixth transistor,

the second input terminal is electrically connected to of the source and the drain of the eighth transistor, of the source and the drain of the sixth transistor, the gate of the seventh transistor, the gate of the eighth transistor, and the gate of the ninth transistor,

the second output terminal is electrically connected to of the source and the drain of the fourth transistor and of the source and the drain of the ninth transistor,

the fourth transistor to the ninth transistor have the same channel length,

the channel width of the fourth transistor is preferably the same as the channel width of the fifth transistor,

the channel width of the sixth transistor is preferably twice the channel width of the fifth transistor,

the fourth to sixth transistors form an th current mirror circuit,

the channel width of the ninth transistor is preferably the same as the channel width of the eighth transistor,

the channel width of the seventh transistor is preferably twice the channel width of the eighth transistor,

the seventh to ninth transistors form a second current mirror circuit,

the input terminal of the th comparison circuit is supplied with a sixth signal,

the second input terminal of the th comparison circuit is supplied with a seventh signal,

the second output terminal of the comparison circuit outputs the greater of the sixth and seventh signals as an eighth signal,

the th input terminal of the second comparison circuit is supplied with the eighth signal,

the second input terminal of the second comparison circuit is supplied with a ninth signal,

the second output terminal of the second comparison circuit outputs a larger of the eighth signal and the ninth signal to the determination circuit as a tenth signal,

the determination circuit has a function of determining the tenth signal to binarize the tenth signal and generating the fourth signal,

and the th circuit has a function of controlling the timing of outputting the fourth signal to the output circuit.

4. The image pickup apparatus according to claim 1 or 2, wherein the plurality of pixels are arranged in a matrix and have a region shielded from light between adjacent pixels.

5. The image pickup apparatus according to claim 1 or 2,

wherein the pixel further comprises a photoelectric conversion element, a tenth transistor, a tenth transistor, a twelfth transistor, a thirteenth transistor, a fourteenth transistor, and a capacitor,

electrodes of the photoelectric conversion element are electrically connected to of the source and the drain of the tenth transistor,

another of the source and drain of the tenth transistor are electrically connected to of the source and drain of the tenth transistor,

of the source and drain of the tenth transistor are electrically connected to the gate of the twelfth transistor,

a gate of the twelfth transistor is electrically connected to electrodes of the th capacitor,

of the source and the drain of the twelfth transistor are electrically connected to the th output terminal,

another electrodes of the th capacitor are electrically connected to of the source and drain of the thirteenth transistor,

another of the source and the drain of the thirteenth transistor are electrically connected to the th wiring,

a gate of the thirteenth transistor is electrically connected to the second wiring,

and the tenth transistor and the twelfth transistor include a metal oxide in a channel formation region.

6. The image pickup apparatus according to claim 5, wherein the metal oxide contains In, Zn, and M (M is Al, Ti, Ga, Sn, Y, Zr, La, Ce, Nd, or Hf).

7. The image pickup device according to claim 5, wherein the photoelectric conversion element contains selenium or a compound containing selenium.

An electronic device of the kind , comprising:

the imaging device according to any of claims 1 to 3, and

a display device.

Technical Field

The aspects of the present invention relate to imaging devices and electronic apparatuses.

Note that aspects of the present invention are not limited to the above-described technical fields the technical field of aspects of the invention disclosed in this specification and the like relates to objects, methods, or manufacturing methods, and particularly, aspects of the present invention relates to semiconductor devices, display devices, light-emitting devices, power storage devices, driving methods thereof, or manufacturing methods thereof.

In addition, in this specification and the like, a semiconductor device refers to an element, a circuit, a device, or the like which can operate by utilizing semiconductor characteristics, examples of semiconductor elements such as a transistor and a diode are semiconductor devices, examples of a circuit including a semiconductor element are semiconductor devices, and examples of a device including a circuit including a semiconductor element are semiconductor devices.

Background

With the development of information technologies such as IoT (Internet of things) and AI (Artificial Intelligence), the amount of data to be processed tends to increase. In order to utilize information technologies such as IoT and AI in electronic devices, it is necessary to manage a large amount of data in a decentralized manner.

In an image processing system of an in-vehicle electronic device, an image processing system for monitoring a moving object, and the like, improvement of an image recognition processing speed using AI has been receiving attention. For example, patent document 1 discloses a technique for providing an imaging device with an arithmetic function.

[ Prior Art document ]

[ patent document ]

[ patent document 1] Japanese patent application laid-open No. 2016-123087

Disclosure of Invention

Technical problem to be solved by the invention

With the development of technology, in an image pickup apparatus including a solid-state image pickup element such as a CMOS image sensor, it is possible to easily pick up a high-quality image, and it is necessary to install a more intelligent function also in the next -generation image pickup apparatus.

In order to recognize an object from image data, high-level image processing is required. In the height image processing, various analysis processes for analyzing an image, such as a filter process and a comparison operation process, are used. In the analysis processing for performing image processing, the larger the number of pixels processed, the larger the amount of computation, and the larger the amount of computation, the longer the processing time. For example, in an in-vehicle image processing system, there is a problem that an increase in processing time affects safety. Further, in the image processing system, there is a problem that the power consumption increases as the amount of computation increases.

In view of the above, , which is an object of aspects of the present invention, provides 0 imaging apparatuses having a novel structure, , which is an object of 1 aspects of the present invention, provides imaging apparatuses having a neural network pooling function, , which is an object of aspects of the present invention, provides imaging apparatuses having a novel structure capable of reducing the amount of computation and shortening the processing time, and , which is an object of aspects of the present invention, provides imaging apparatuses having a novel structure capable of reducing power consumption.

The objects other than the above objects will be apparent from the description of the specification, drawings, claims, and the like, and objects other than the above objects may be extracted from the description of the specification, drawings, claims, and the like.

The object of the mode of the present invention is not limited to the above-mentioned object, the above-mentioned object does not hinder the existence of other objects, the other objects are objects which are not mentioned above and will be described in the following description, and a person of ordinary skill in the art can derive from the description of the specification, the drawings, and the like and appropriately extract the above-mentioned objects, and modes of the present invention achieve at least objects out of the above-mentioned description and/or the other objects.

Means for solving the problems

The aspects of the present invention are image pickup apparatuses including a pixel region and a circuit, wherein the pixel region includes a pooling module and an output circuit, the pooling module includes a plurality of pooling circuits and a comparison module, the pooling circuit includes a plurality of pixels and an arithmetic circuit, the comparison module includes a plurality of comparison circuits and a determination circuit, the pixels have a function of acquiring a th signal by photoelectric conversion, the pixels have a function of generating a second signal by multiplying a th signal at an arbitrary magnification, the pooling circuit has a function of generating a third signal by adding the plurality of second signals by the arithmetic circuit, the comparison module has a function of selecting a maximum third signal by comparing the plurality of third signals and outputting the third signal to the determination circuit, the determination circuit has a function of determining the maximum third signal and binarizing the third signal to generate a fourth signal, the circuit controls a timing of outputting the fourth signal to the output circuit, the pooling module performs pooling processing according to the number of pixels, and the pooling module generates the fourth signal by the pooling processing.

In the image pickup device having the above-described configuration, it is preferable that the image pickup device further includes a second circuit, a third circuit, a wiring, a second wiring, and a third wiring, wherein the pixel includes a th output terminal, the arithmetic circuit includes a th transistor, a second transistor, and a third transistor, the second circuit is electrically connected to a plurality of pixels extending in the row direction through a th wiring, the third circuit is electrically connected to a plurality of pixels extending in the column direction through the second wiring, the third wiring is electrically connected to of the source and drain of the 2 transistor, of the source and drain of the second transistor, and 6855 of the source and drain of the third transistor, another of the source and drain of the th transistor of the transistor, the gate of the third transistor, and a th output terminal of a pixel included in the battery circuit, the third circuit has a function of outputting a selection signal to the second wiring, the gate of the third transistor, and the th output terminal of the battery circuit included in a pixel, the third circuit have a function of outputting a signal with a channel length equal to a channel length of the second transistor, and a function of the third transistor, and a channel length of the third transistor is set to be equal to a channel length of a channel , thereby a fifth transistor, and a signal of a channel is set to be equal to a channel length of a channel, and a channel of a transistor, and.

In the image pickup device having the above-described configuration, it is preferable that the comparison module includes a comparison circuit , a comparison circuit and a current mirror circuit, the th comparison circuit includes fourth to ninth transistors, an input terminal 0, a second input terminal, a second output terminal and a fourth wiring, the 1 th comparison circuit has a second output terminal electrically connected to the th input terminal of the comparison circuit through the current mirror circuit, the th input terminal is electrically connected to of the source and drain of the fifth transistor, of the source and drain of the seventh transistor, a gate of the fourth transistor, a gate of the fifth transistor and a gate of the sixth transistor, the second input terminal is electrically connected to of the source and drain of the eighth transistor, of the source and drain of the sixth transistor, a gate of the seventh transistor and a gate of the ninth transistor, the second output terminal is electrically connected to the source and drain of the eighth transistor, the gate of the seventh transistor and the gate of the ninth transistor are electrically connected to the fifth input terminal 638 of the eighth transistor, the gate of the seventh transistor, the seventh transistor has a width equal to the ninth transistor, the ninth transistor is preferably, the ninth transistor and the ninth comparison circuit supplies a signal having a width equal to the signal output terminal of the ninth transistor which is equal to the ninth comparison circuit, the ninth transistor and the ninth comparison circuit, the signal input terminal is supplied to the ninth transistor, the signal input terminal of the ninth transistor is supplied to the ninth transistor, the ninth transistor has a signal input terminal of the ninth transistor, the ninth transistor is preferably, the ninth transistor is connected to the ninth transistor, the signal input terminal of the ninth transistor is connected to the ninth transistor, the signal input terminal of the ninth transistor, the ninth transistor is connected to the ninth transistor, the signal input terminal of the ninth transistor is connected to the ninth transistor, the signal input terminal of the ninth transistor, the ninth transistor is connected to the ninth transistor, the signal input terminal of the ninth transistor is connected to the signal input terminal of.

In the imaging device having the above configuration, it is preferable that the plurality of pixels are arranged in a matrix and have a region shielded from light between adjacent pixels.

In the image pickup device having the above-described structure, it is preferable that the pixel further includes a photoelectric conversion element, a tenth transistor, a tenth transistor, a twelfth transistor, a thirteenth transistor, and a capacitor, 0 electrodes of the photoelectric conversion element are electrically connected to 1 of sources and drains of the tenth transistor, the other 2 of the sources and drains of the tenth transistor are electrically connected to 4 of the sources and drains of the tenth 3 transistor, 6 of the sources and drains of the tenth 5 transistor are electrically connected to a gate of the twelfth transistor, a gate of the twelfth transistor is electrically connected to electrodes of the 7 capacitor, of the sources and drains of the twelfth transistor are electrically connected to the output terminal, the other electrodes of the capacitor are electrically connected to of the sources and drains of the thirteenth transistor, the other of the sources and drains of the thirteenth transistor are electrically connected to a gate wiring of the thirteenth transistor, a gate of the thirteenth wiring is electrically connected to the thirteenth transistor, and the twelfth metal-containing channel oxide is formed in a region.

In the imaging device having the above structure, it is preferable that the metal oxide contains In, Zn, and M (M is Al, Ti, Ga, Sn, Y, Zr, La, Ce, Nd, or Hf).

In the imaging device having the above configuration, the photoelectric conversion element preferably contains selenium or a selenium-containing compound.

Effects of the invention

In view of the above, aspects of the present invention can provide image pickup apparatuses having a novel structure, and aspects of the present invention can provide image pickup apparatuses having a neural network pooling function, and aspects of the present invention can provide image pickup apparatuses having a novel structure capable of reducing the amount of computation and shortening the processing time, and , which is an object of aspects of the present invention, provides image pickup apparatuses having a novel structure capable of reducing power consumption.

The present invention is not limited to the above-described effects, and other effects are not mentioned above and will be described in the following description.

Drawings

Fig. 1 illustrates a block diagram of an image pickup apparatus.

Fig. 2 illustrates a block diagram of an image pickup apparatus.

Fig. 3 (a) illustrates a block diagram of the image pickup apparatus. (B) A circuit diagram of an image pickup apparatus is explained.

Fig. 4 illustrates a circuit diagram of a pixel.

Fig. 5 (a) illustrates a block diagram of the image pickup apparatus. (B) A timing chart for explaining the operation of the image pickup apparatus will be described.

Fig. 6 illustrates a block diagram of an image pickup apparatus.

Fig. 7 illustrates a circuit diagram of a pixel.

Fig. 8 is a diagram illustrating a structure of a pixel of an imaging device.

Fig. 9 is a diagram illustrating a structure of a pixel of an imaging device.

Fig. 10 is a diagram illustrating a structure of a pixel of an imaging device.

Fig. 11 (a) is a diagram illustrating a structure of a pixel of an imaging device. (B) A sectional view showing the structure of the image pickup apparatus.

Fig. 12 is a diagram illustrating a structure of a pixel of an imaging device.

Fig. 13 is a diagram illustrating a structure of a pixel of an imaging device.

FIG. 14 is a perspective view of a package and a module for housing an image pickup device.

Fig. 15 is a diagram showing a configuration example of an electronic apparatus.

Detailed Description

(embodiment mode 1)

In this embodiment, an imaging apparatus that efficiently performs pooling processing of a neural network will be described with reference to fig. 1 to 7.

First, a block diagram of the image pickup apparatus 10 will be described with reference to fig. 1. The imaging device 10 includes a pixel region, a driver 11, a driver 12, a driver 13, a plurality of wirings 111, a plurality of wirings 112 (not shown), and a plurality of wirings 113a (not shown). The pixel region includes a plurality of pooling modules 200, a plurality of analog-to-digital conversion circuits 250, and an output circuit 251. The pooling module 200 includes a plurality of pooling circuits 210 and a comparing module 220, the pooling circuits 210 including a plurality of pixels 100 and an arithmetic circuit 212 (not shown). The comparing module 220 includes a plurality of comparing circuits 230 (not shown) and a determining circuit 221 (not shown).

The pixel 100 may convert light into an electrical signal to obtain an th signal, and the pixel 100 may multiply the th signal by an arbitrary magnification to generate a second signal, the th signal and the second signal are output as a current, the arbitrary magnification is a value of weight data used for pooling of the neural network.

Pooling circuit 210 may generate a third signal by adding the plurality of second signals via arithmetic circuit 212. The arithmetic circuit 212 may average the plurality of second signals to generate a fifth signal.

The comparison module 220 may select the largest third signal by comparing the plurality of third signals and output it to the decision circuit 221. The determination circuit 221 may determine the largest third signal, binarize the largest third signal, and generate a fourth signal.

That is, the pooling module 200 may obtain the th signal from the plurality of pixels included in the pooling module 200, pool the th signal to generate a fourth signal, and output the fourth signal.

The driver 11 can control the timing of outputting the fourth signal to the output circuit 251 in accordance with the selection signal supplied to the wiring 111 although not shown, the output circuit 251 can output the fourth signal to a neural network that controls the image pickup apparatus 10, when th data is pooled by the image pickup apparatus 10, data that extracts the feature of the data is input to the neural network.

The pooling module 200 preferably includes a plurality of pooling circuits 210 fig. 1 shows an example in which the pooling module 200 includes four pooling circuits 210, the number of pooling circuits 210 included in the pooling module 200 may be 1 or more and n or less (n is a natural number of 2 or more), when a plurality of pooling circuits are provided, features of data are easily extracted, furthermore, as the number of pixels the pooling circuits 210 have increases, the compression rate of data becomes high, and thus the amount of operation of the neural network is reduced, and therefore, the power consumption of the neural network is reduced by steps .

In fig. 2, examples of the pooling circuit 210 are described with reference to a block diagram, the pooling circuit 210 includes a plurality of pixels 100, an arithmetic circuit 212, a switch 203, a switch 204, a plurality of wirings 112, a plurality of wirings 113a, a wiring 114, a wiring 115, and a wiring 210a, the pixel 100 includes a th output terminal, the arithmetic circuit 212 includes a transistor 212a, a transistor 212b, and a transistor 212c, and note that the pooling circuit 210 shown in fig. 2 includes an example of four pixels.

The driver 12 is electrically connected to the plurality of pixels 100 extending in the row direction through a wiring 112, and the driver 13 is electrically connected to the plurality of pixels 100 extending in the column direction through a wiring 113 a.

The wiring 114 is electrically connected to of the sources and drains of the transistors 212a, of the sources and drains of the transistors 212b, and of the sources and drains of the transistors 212c, the gate of the transistor 212a is electrically connected to another of the sources and drains of the transistors 212a, the gate of the transistor 212b, and the gate of the transistor 212c, the gate of the transistor 212a is also electrically connected to the output terminal 100a of the plurality of pixels 100 included in the pooling circuit 210.

Another of the source and the drain of the transistor 212b are electrically connected to the electrodes of the switch 203, another of the source and the drain of the transistor 212c are electrically connected to the electrodes of the switch 204, another electrodes of the switch 203 are electrically connected to another electrodes of the switch 204 and the comparison module 220 through the wiring 210 a.

The driver 13 can output a selection signal to the wiring 113 a. The driver 12 can set the pixels 100 to an arbitrary magnification as weight data through the wiring 112. The transistor 212a has the same channel length as the transistor 212b and the transistor 212c, and the transistor 212b has the same channel width as the transistor 212a, whereby a third signal obtained by adding a plurality of second signals can be output. The transistor 212c has a channel width obtained by dividing the channel width of the transistor 212a by the number of pixels 100 included in the pool circuit 210, and can thereby output a fifth signal having a size obtained by dividing the size of the third signal by the number of pixels 100. The third signal and the fifth signal are controlled by current. Switch 203 and switch 204 are preferably in a complementary relationship.

The switch 203 and the switch 204 are controlled by an th switching signal supplied to the wiring 115 fig. 2 shows an example in which a p-channel type transistor is used for the switch 203 and an n-channel type transistor is used for the switch 204.

In the case where the th switching signal is "L", the pooling circuit 210 may output a third signal to the comparing block 220 through the wiring 210 a.

In the case where the th switching signal is "H", the pooling circuit 210 may output a fifth signal to the comparing block 220 through the wiring 210 a.

For example, in the in-vehicle image processing system, it is necessary to instantaneously determine the surrounding situation of the vehicle moving at a high speed, and therefore, the imaging device 10 having the pooling module 200 is dedicated to for detecting the feature from the imaging data, so that the amount of computation can be suppressed and the processing time can be shortened.

Note that fig. 2 shows an example in which different weight data is supplied to each pixel 100 included in the pooling circuit 210, and since the weight data can be supplied for units by the pooling circuit 210 or the pooling module 200, the wiring 112 and the wiring 113a can be electrically connected for units by the pooling circuit 210 or the pooling module 200, and the degree of integration of the imaging apparatus 10 can be improved by reducing the wiring 112 and the wiring 113 a.

In the diagram (a) of fig. 3, examples of the comparison module 220 are described with reference to a block diagram, the comparison module 220 includes a plurality of comparison circuits 230, a plurality of current mirror circuits 222, and a determination circuit 221, each of the comparison circuits 230 includes an input terminal 231a, an input terminal 231b, and an output terminal 231c, the determination circuit 221 includes an input terminal 221a, an input terminal 221b, and an output terminal 221c, and the current mirror circuit 222 includes an input terminal 224a and an output terminal 224 b.

In the diagram (a) of fig. 3, output signals are supplied from four pooling circuits 210 to an example of a comparison module 220. In addition, the comparison module 220 is electrically connected to the four different pooling circuits 210 through the wirings 210a (i, j) to 210a (i +1, j + 1). The comparator circuit 230 is preferably provided according to the number of input signals. In the example shown in fig. 3 (a), the comparison module 220 includes a comparison circuit 230a, a comparison circuit 230b, a comparison circuit 230c, a current mirror circuit 222a, a current mirror circuit 222b, and a determination circuit 221.

Next, connection examples of the comparison circuits 230a, 230b, 230c, 222a, 222b, and 221 are described. The input terminal 231a of the comparison circuit 230a is electrically connected to the wiring 210a (i, j), the input terminal 231b is electrically connected to the wiring 210a (i +1, j), the output terminal 231c is electrically connected to the input terminal 224a of the current mirror circuit 222a, and the output terminal 224b of the current mirror circuit 222a is electrically connected to the input terminal 231a of the comparison circuit 230 b.

The input terminal 231b of the comparison circuit 230b is electrically connected to the wiring 210a (i, j +1), the output terminal 231c is electrically connected to the input terminal 224a of the current mirror circuit 222b, and the output terminal 224b of the current mirror circuit 222b is electrically connected to the input terminal 231a of the comparison circuit 230 c. The input terminal 231b of the comparator circuit 230c is electrically connected to the wiring 210a (i +1, j +1), and the output terminal 231c is electrically connected to the input terminal 221a of the determination circuit 221.

The current mirror circuit 222 includes transistors 223a and 223 b. the transistors 223a and 223b are preferably p-channel transistors of the source and the drain of the transistor 223a are electrically connected to of the source and the drain of the transistor 223b and the wiring 114. the gate of the transistor 223a is electrically connected to the other of the source and the drain of the transistor 223a and the gate of the transistor 223 b.

The input terminal 231a of the comparison circuit 230a is supplied with a signal a1. through the wiring 210a (i, j) and the input terminal 231b is supplied with a signal a2 through the wiring 210a (i +1, j) the larger of the signal a1 and the signal a2, which is supplied to the input terminal 224a of the current mirror circuit 222a, are output from the output terminal 231c as the signal a3, the signal a3 becomes the signal b1 of the same size as the signal a3 through the current mirror circuit 222a, and the signal b1 is supplied to the output terminal 224b of the current mirror circuit, so the input terminal 231a of the comparison circuit 230b is supplied with the signal b1 of the same size as the signal a3, note that the directions of the signal a3 and the signal b1 are different.

The input terminal 231b of the comparator circuit 230b is supplied with a signal b2 through a wiring 210a (i, j +1), larger of the signals b1 and b2 are output from the output terminal 231c as a signal b3, the input terminal 231a of the comparator circuit 230c is supplied with a signal c1 through the current mirror circuit 222b, the input terminal 231b is supplied with a signal c2 through a wiring 210a (i +1, j +1), and larger of the signals c1 and c2 are output from the output terminal 231c as a signal c3 to the decision circuit 221, and each of the signals a1, a2, a3, b1, b2, b3, c1, c2, and c3 is preferably an analog signal.

Therefore, the determination circuit 221 determines the signal c3 input to the input terminal 221a, binarizes the signal, generates a fourth signal, and outputs the fourth signal to the output terminal 221 c. The driver 11 can control timing of outputting the fourth signal to the output circuit 251 through the wiring 211 in accordance with the selection signal supplied to the wiring 111.

In fig. 3 (B), a circuit diagram of the comparison circuit 230 is explained. The comparison circuit 230 includes transistors 241 to 246, an input terminal 231a, an input terminal 231b, an output terminal 231c, and a wiring 232.

The input terminal 231a is electrically connected to of the sources and drains of the transistors 242, of the sources and drains of the transistors 244, the gate of the transistor 241, the gate of the transistor 242, and the gate of the transistor 243, the input terminal 231b is electrically connected to of the sources and drains of the transistor 245, of the sources and drains of the transistor 243, the gate of the transistor 244, the gate of the transistor 245, and the gate of the transistor 246, the output terminal 231c is electrically connected to of the sources and drains of the transistors 241 and of the sources and drains of the transistors 246, and the wiring 232 is electrically connected to the other of the sources and drains of the transistors 241 to 246.

Further, the transistors 241 to 246 have the same size of channel length.

In addition, the channel width of the transistor 241 is preferably the same as the channel width of the transistor 242, and the channel width of the transistor 243 is preferably twice the channel width of the transistor 242 the transistors 241 to 243 form the th current mirror circuit.

In addition, the channel width of the transistor 246 is preferably the same as the channel width of the transistor 245, and the channel width of the transistor 244 is preferably twice the channel width of the transistor 245. The transistors 244 to 246 form a second current mirror circuit.

Next, an operation of the comparison circuit 230 will be described, note that the input terminal 231a and the input terminal 231b are supplied with current as analog signals, and the output terminal 231c sinks current as analog signals, for example, when the signal input to the input terminal 231a is larger than the signal input to the input terminal 231b, the signal supplied to the input terminal 231b is sunk to the transistor 243, as a different example, when the signal input to the input terminal 231b is larger than the signal input to the input terminal 231a, the signal input to the input terminal 231a is sunk to the transistor 244, and therefore, the output terminal 231c can sink signals having the same magnitude as that of the larger one of the signals input to the input terminal 231a or the input terminal 231b by any of the -th current mirror circuit and the second current mirror circuit.

Note that when the input signals to the input terminal 231a and the input terminal 231b have the same magnitude, the magnitude of the signal absorbed by the transistor 242 and the transistor 245 is approximately half of the signal.

Accordingly, in the diagram (a) of fig. 3, as the signal c3, the largest signal among the signals a1, a2, b2, and c2 supplied to the comparison module 220 is supplied to the determination circuit 221. The determination circuit 221 may determine the signal c3 to binarize and generate a fourth signal. The driver 11 can output the determination result in the output circuit 251 by supplying a selection signal to the determination circuit 221 through the wiring 111.

In fig. 4, examples of the pixel 100 will be described with reference to a circuit diagram, the pixel 100 includes a photoelectric conversion element 101, a transistor 102, a transistor 103, a capacitor 104, a transistor 105, a transistor 106, and an output terminal 100a, and the pixel 100 is electrically connected to a wiring 112, a wiring 113a, a wiring 113b, a wiring 117, a wiring 118, and a wiring 119.

electrodes of the photoelectric conversion element 101 are electrically connected to of the source and the drain of the transistor 102, the other 0 of the source and the drain of the transistor 102 are electrically connected to 1 of the source and the drain of the transistor 103, the gate of the transistor 105, and electrodes of the capacitor 104, of the source and the drain of the transistor 105 is electrically connected to the output terminal 100a, the other electrodes of the capacitor 104 are electrically connected to of the source and the drain of the transistor 106, the other of the source and the drain of the transistor 106 is electrically connected to the wiring 112, the gate of the transistor 106 is electrically connected to the wiring 113a, the gate of the transistor 102 is electrically connected to the wiring 113b, the gate of the transistor 103 is electrically connected to the wiring 113c, the other of the source and the drain of the transistor 103 are electrically connected to the wiring 118, the other electrodes of the photoelectric conversion element 101 are electrically connected to the wiring 117, and the other of the source and the drain of the transistor 105 are electrically connected to the wiring 119.

Note that the node FN. is formed by connecting another of the source and the drain of the transistor 102, of the source and the drain of the transistor 103, the gate of the transistor 105, and electrodes of the capacitor 104, and a structure in which the capacitor 104 is not provided may be employed.

The transistor 103 can be turned on in accordance with a signal supplied to the wiring 113c, whereby the node FN can be initialized in accordance with a reset potential supplied to the wiring 118, the transistor 102 can be turned on in accordance with a signal supplied to the wiring 113b, therefore, the photoelectric conversion element 101 can be updated with image pickup data into which data of the node FN is photoelectrically converted by the transistor 102, further, the transistor 102 can be turned off in accordance with a signal supplied to the wiring 113b, the node FN can hold the image pickup data by turning the transistor 102 off, that is, the th signal refers to a current flowing when the image pickup data is supplied to the gate of the transistor 105.

Fig. 4 shows an example in which an n-channel transistor is used as the transistor 105, but a p-channel transistor may also be used. Note that in the case where the transistor 105 is an n-channel transistor, the potential supplied to the wiring 119 is preferably low, and in the case where the transistor 105 is a p-channel transistor, the potential supplied to the wiring 119 is also preferably low.

Further, the transistor 106 can be turned on in accordance with a signal supplied to the wiring 113 a. The weight data can be supplied from the wiring 112 to the capacitor 104 through the transistor 106. Preferably, node FN is a floating node when transistors 102 and 103 are in an off state. Therefore, transistors with small off-state current (off-state current) are preferably used for the transistors 102 and 103. A transistor having a small off-state current is preferably a transistor including metal oxide in a channel formation region (OS transistor). As for the OS transistor, it will be described in detail in embodiment mode 2.

The weight data is added to the image pickup data held in the node FN via the capacitor 104. That is, the gate of the transistor 105 is supplied with a data voltage in which weight data is added to image sensing data. Therefore, the transistor 105 can multiply by an arbitrary magnification of the weight data using the resistance of the transistor 105. That is, the second signal is a current flowing when a data voltage obtained by adding weight data to image sensing data is supplied to the gate of the transistor 105.

In fig. 5, examples of the operation method of the pooling module 200 are described, and in the diagram (a) of fig. 5, an example in which the pooling module 200 includes four pooling circuits 210 and a comparison module 220 is described for the sake of simplicity.

Fig. 5 (B) is a timing chart showing examples of the operation method of the pooling module 200 shown in fig. 5 (a), and although not shown, the timing chart shown in fig. 5 (B) shows an example in which the L signal is supplied to the wiring 115 and the pooling circuit 210 adds up the th signal of the plurality of pixels 100.

At T1, the transistor 103 included in each pixel 100 is turned on by supplying an H signal to the wiring 113 c. Therefore, the node FN is reset using the potential supplied to the wiring 118. Further, the wiring 113a is supplied with a selection signal, and an initial value Res of the weight data is supplied through the wiring 112.

At T2, an H signal is supplied to the wiring 113b, each pixel 100 is photoelectrically converted (sensing) by the photoelectric conversion element 101, and the node FN is updated using the image data.

At T3, the L signal is supplied to the wiring 113b, and the image pickup data of the node FN is determined. In addition, a selection signal is supplied to the wiring 113a (1), and weight data of the pixel 100(1), the pixel 100(2), the pixel 100(5), and the pixel 100(6) are set through the wirings 112(1) to 112 (4).

At T4, a selection signal is supplied to the wiring 113a (2), and weight data of the pixel 100(3), the pixel 100(4), the pixel 100(7), and the pixel 100(8) are set via the wirings 112(1) to 112 (4).

At T5, a selection signal is supplied to the wiring 113a (3), and weight data of the pixels 100(9), 100(10), 100(13), and 100(14) are set via the wirings 112(1) to 112 (4). The pooling circuit 210(1, 1) outputs a data signal a1 obtained by adding weight data to the image pickup data to the wiring 210a (1, 1). The pooling circuit 210(2, 1) outputs a signal a2 obtained by adding weight data to the image pickup data to the wiring 210a (2, 1).

At T6, a selection signal is supplied to the wiring 113a (4), and weight data of the pixels 100(11), 100(12), 100(15), and 100(16) are set via the wirings 112(1) to 112 (4).

At T7, the pooling circuit 210(1, 1) outputs a data signal b2 obtained by adding weight data to the image pickup data to the wiring 210a (1, 2). The pooling circuit 210(2, 2) outputs a signal c2 obtained by adding weight data to the image pickup data to the wiring 210a (2, 2).

At T8, the comparison module 220 detects the largest signal among a1, a2, b2, and c 2. The determination circuit 221 included in the comparison module 220 determines the detected maximum signal, binarizes the signal, and outputs a digital signal out to the wiring 211. The digital signal out is supplied to the output circuit 251. For easy processing in the neural network, the output circuit 251 combines the digital signals out and outputs them as digital data of an arbitrary data width.

In fig. 6, an example of a pooling circuit 210 having a different structure from that of fig. 2 is explained with reference to a block diagram. Fig. 6 differs from fig. 2 in that: the pooling circuit 210 includes a plurality of wirings 113d, a wiring 211a, and a wiring 211 b; the pixel 100 includes an output terminal 100 b.

The wiring 113d is electrically connected to a plurality of pixels extending in the column direction. The wiring 211a is electrically connected to the output terminals 100b of the pixels 100 extending in the row direction. The wiring 211a or the wiring 211b outputs image pickup data. The image data is output to the analog-digital conversion circuit 250 through the wiring 211a and the wiring 211 b.

Fig. 7 illustrates an example of the pixel 100 having a different structure from that of fig. 4. Fig. 7 is different from fig. 4 in that a transistor 107 and a transistor 108 are included.

A gate of the transistor 107 is electrically connected to the node FN, of the source and the drain of the transistor 107 are electrically connected to of the source and the drain of the transistor 108, the other of the source and the drain of the transistor 108 are electrically connected to the output terminal 100b, the gate of the transistor 108 is electrically connected to the wiring 113d, and the other of the source and the drain of the transistor 107 are electrically connected to the wiring 119.

The transistor 107 can flow a current in accordance with the potential of the image pickup data held in the node FN. The transistor 108 can output image pickup data to the output terminal 100b in accordance with a selection signal supplied to the wiring 113 d. Note that when weight data is set in the capacitor 104, a multiplication result obtained by adding the weight data to image sensing data and by the resistance of the transistor 105 is output.

By having the pooling module 200, the imaging apparatus 10 can easily perform pooling. Therefore, by reducing the amount of data and the amount of computation transmitted to the neural network, power consumption can be reduced.

As described above, the structure and method described in this embodiment can be used in combination with the structures and methods described in other embodiments as appropriate.

(embodiment mode 2)

In this embodiment, a photoelectric conversion element 101 used in the imaging apparatus 10 is described with reference to fig. 8 to 14.

< example of Structure of Pixel Circuit >

Fig. 8 (a) illustrates a structure of a pixel having the pixel circuit described above. Fig. 8 (a) shows an example in which the pixel has a stacked-layer structure of the layer 61 and the layer 62.

The layer 61 includes the photoelectric conversion element 101. As shown in fig. 8 (C), the photoelectric conversion element 101 may be a stack of layers 65a, 65b, and 65C.

The photoelectric conversion element 101 shown in fig. 8 (C) is a pn junction photodiode, and p is used as the layer 65a, for example⁺A type semiconductor, an n-type semiconductor as the layer 65b, and n as the layer 65c⁺A semiconductor. Alternatively, it may be the layer 65a use of n⁺A p-type semiconductor as the layer 65b and a p-type semiconductor as the layer 65c⁺A semiconductor. In addition, a pin junction photodiode using an i-type semiconductor as the layer 65b may be used as the photoelectric conversion element 101.

The pn junction type photodiode or the pin junction type photodiode can be formed using single crystal silicon. The pin junction type photodiode can be formed using a thin film such as amorphous silicon, microcrystalline silicon, or polycrystalline silicon.

As shown in fig. 8 (D), the photoelectric conversion element 101 included in the layer 61 may be a stack of the layer 66a, the layer 66b, the layer 66c, and the layer 66D, and the photoelectric conversion element 101 shown in fig. 8 (D) is examples of an avalanche photodiode, and the layer 66a and the layer 66D correspond to electrodes, and the layer 66b and the layer 66c correspond to photoelectric conversion portions.

The layer 66a is preferably a metal layer having low resistance. For example, aluminum, titanium, tungsten, tantalum, silver, or a stack thereof may be used.

A conductive layer having high transmittance to visible Light (Light) is preferably used for the layer 66 d. For example, indium oxide, tin oxide, zinc oxide, indium tin oxide, gallium zinc oxide, indium gallium zinc oxide, graphene, or the like can be used. In addition, layer 66d may be omitted.

The layers 66b and 66c of the photoelectric conversion section may have a pn junction photodiode structure in which a selenium-based material is used as a photoelectric conversion layer, for example. Preferably, a selenium-based material of a p-type semiconductor is used for the layer 66b, and a gallium oxide of an n-type semiconductor is used for the layer 66 c.

The photoelectric conversion element using the selenium-based material has high external quantum efficiency for visible light. The photoelectric conversion element may increase an electron amplification amount with respect to an incident light amount by avalanche multiplication. In addition, since the selenium-based material has a high light absorption coefficient, it is advantageous from the viewpoint of production because, for example, a photoelectric conversion layer can be formed as a thin film. The thin film of the selenium-based material can be formed by a vacuum deposition method, a sputtering method, or the like.

As the selenium-based material, crystalline selenium such as single crystal selenium and polycrystalline selenium, amorphous selenium, a compound of copper, indium, and selenium (CIS), a compound of copper, indium, gallium, and selenium (CIGS), or the like can be used.

The n-type semiconductor is preferably formed of a material having a wide band gap and having transparency to visible light, and for example, zinc oxide, gallium oxide, indium oxide, tin oxide, or an oxide obtained by mixing with the above-mentioned materials can be used.

As the layer 62 shown in fig. 8 (a), for example, a silicon substrate can be used. The silicon substrate is provided with an Si transistor and the like, and a circuit for driving the pixel circuit, a readout circuit for an image signal, an image processing circuit, and the like can be provided in addition to the pixel circuit.

As shown in fig. 8 (B), the pixel may have a stacked-layer structure of a layer 61, a layer 63, and a layer 62.

Layer 63 may include OS transistors (e.g., transistors 102, 103 of a pixel circuit). At this time, the layer 62 preferably includes Si transistors (e.g., transistors 107, 108 of the pixel circuit).

With this configuration, the elements constituting the pixel circuit can be dispersed in a plurality of layers and can be provided so as to overlap with each other, and therefore the area of the imaging device can be reduced. In the structure shown in fig. 8 (B), the layer 62 may be used as a supporting substrate, and the pixel 100 and the peripheral circuit may be provided over the layers 61 and 63.

< OS transistor >

As a semiconductor material used for the OS transistor, a metal oxide having an energy gap of 2eV or more, preferably 2.5eV or more, and more preferably 3eV or more can be used. Typically, an oxide semiconductor containing indium or the like can be used, and for example, CAC-OS or the like described later can be used.

As the semiconductor layer, for example, a film represented by "In-M-Zn based oxide" containing indium, zinc, and M (metal such as aluminum, titanium, gallium, germanium, yttrium, zirconium, lanthanum, cerium, tin, neodymium, or hafnium) can be used.

When the oxide semiconductor constituting the semiconductor layer is an In-M-Zn type oxide, it is preferable that the atomic ratio of the metal elements of the sputtering target for depositing and forming the In-M-Zn oxide film satisfies in.M and Zn.M. The atomic ratio of the metal elements In the sputtering target is preferably In: M: Zn 1:1:1, In: M: Zn 1:1.2, In: M: Zn 3:1:2, In: M: Zn 4:2:3, In: M: Zn 4:2:4.1, In: M: Zn 5:1:6, In: M: Zn 5:1:7, In: M: Zn 5:1:8, and the like. Note that the atomic ratio of the semiconductor layers formed by deposition may be varied within a range of ± 40% of the atomic ratio of the metal element in the sputtering target described above, respectively.

As the semiconductor layer, an oxide semiconductor having a low carrier density can be used. For example, a semiconductor layer having a carrier density of 1 × 10 can be used¹⁷/cm³Hereinafter, it is preferably 1 × 10¹⁵/cm³Hereinafter, more preferably 1 × 10¹³/cm³Hereinafter, the step is preferably 1X 10¹¹/cm³Hereinafter, the further step is preferably less than 1X 10¹⁰/cm³And is 1X 10^-9/cm³An oxide semiconductor having the above carrier density. Such an oxide semiconductor is referred to as an oxide semiconductor which is intrinsic to high purity or substantially intrinsic to high purity. Accordingly, the oxide semiconductor has low impurity concentration and low defect level density, and thus has stable characteristics.

Note that the present invention is not limited to the above description, and a material having an appropriate composition may be used in accordance with the semiconductor characteristics and the electrical characteristics (field effect mobility, threshold voltage, and the like) of a transistor which are required. In addition, it is preferable to appropriately set the carrier density, the impurity concentration, the defect density, the atomic ratio of the metal element to oxygen, the interatomic distance, the density, and the like of the semiconductor layer so as to obtain desired semiconductor characteristics of the transistor.

When the oxide semiconductor constituting the semiconductor layer contains -type silicon or carbon of a group 14 element, oxygen defects increase and it becomes n-type, and therefore, the concentration of silicon or carbon in the semiconductor layer (concentration measured by secondary ion mass spectrometry) is set to 2 × 10¹⁸atoms/cm³Hereinafter, 2 × 10 is preferable¹⁷atoms/cm³The following.

In addition, when an alkali metal or an alkaline earth metal is bonded to an oxide semiconductor, carriers are generated, and an off-state current of a transistor may be causedAnd is increased. Therefore, the concentration of the alkali metal or alkaline earth metal (concentration measured by secondary ion mass spectrometry) of the semiconductor layer is set to 1 × 10¹⁸atoms/cm³Hereinafter, 2 × 10 is preferable¹⁶atoms/cm³The following.

When the oxide semiconductor constituting the semiconductor layer contains nitrogen, electrons as carriers are generated, and the carrier density increases, so that n-type conversion is facilitated. As a result, a transistor using an oxide semiconductor containing nitrogen is likely to have normally-on characteristics. Therefore, the nitrogen concentration (concentration measured by secondary ion mass spectrometry) of the semiconductor layer is preferably 5 × 10¹⁸atoms/cm³The following.

The semiconductor layer may have a non-single crystal structure. Non-single crystal structures include, for example, CAAC-OS (C-Axis Aligned Crystalline Oxide Semiconductor or C-Axis Aligned and A-B-plane amorphous Oxide Semiconductor) crystals having a C-Axis orientation, polycrystalline structures, microcrystalline structures, or amorphous structures. In the non-single crystalline structure, the defect level density of the amorphous structure is the highest, and the defect level density of the CAAC-OS is the lowest.

The oxide semiconductor film having an amorphous structure has, for example, disordered atomic arrangement and has no crystalline component. Alternatively, the oxide film having an amorphous structure has, for example, a completely amorphous structure and does not have a crystal portion.

The semiconductor layer may be a mixed film of two or more kinds selected from a region having an amorphous structure, a region having a microcrystalline structure, a region having a polycrystalline structure, a region having CAAC-OS, and a region having a single crystal structure. The hybrid film sometimes has, for example, a single-layer structure or a laminated structure including two or more of the above-described regions.

Next, the structure of the CAC (Cloud-Aligned Composite) -OS of types of non-single crystal semiconductor layers will be described.

Note that, in the following, a state in which or more metal elements are unevenly distributed in the oxide semiconductor and a region containing the metal elements is mixed in a size of 0.5nm or more and 10nm or less, preferably 1nm or more and 2nm or less or approximately is also referred to as mosaic (mosaic) or patch (patch) state.

The oxide semiconductor preferably contains at least indium, and particularly preferably contains indium and zinc, and may contain kinds or more selected from aluminum, gallium, yttrium, copper, vanadium, beryllium, boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, and the like in addition to these.

For example, CAC-OS among In-Ga-Zn oxides (In CAC-OS, In-Ga-Zn oxide may be particularly referred to as CAC-IGZO) means that the material is divided into indium oxide (hereinafter, referred to as InO)_X1(X1 is a real number greater than 0). ) Or indium zinc oxide (hereinafter, referred to as In)_X2Zn_Y2O_Z2(X2, Y2, and Z2 are real numbers greater than 0). ) And gallium oxide (hereinafter, referred to as GaO)_X3(X3 is a real number greater than 0)) or gallium zinc oxide (hereinafter referred to as Ga_X4Zn_Y4O_Z4(X4, Y4, and Z4 are real numbers greater than 0). ) Etc. into mosaic shape, and mosaic-shaped InO_X1Or In_X2Zn_Y2O_Z2A structure uniformly distributed in the film (hereinafter, also referred to as a cloud).

In other words, the CAC-OS is of GaO_X3A region containing as a main component In_X2Zn_Y2O_Z2Or InO_X1In this specification, for example, when the atomic number ratio of In to the element M In the th region is larger than the atomic number ratio of In to the element M In the second region, the In concentration In the th region is higher than that In the second region.

Note that IGZO is a generic term, and may be a compound containing In, Ga, Zn, and O. A typical example is InGaO₃(ZnO)_m1(m1 is a natural number) or In_(1+x0)Ga_(1-x0)O₃(ZnO)_m0A crystalline compound represented by (-1. ltoreq. x 0. ltoreq.1, m0 is an arbitrary number).

The crystalline compound has a single crystal structure, a polycrystalline structure, or a CAAC structure. The CAAC structure is a crystal structure in which a plurality of IGZO nanocrystals have c-axis orientation and are connected in a non-oriented manner on the a-b plane.

In addition, , CAC-OS is a material composition of an oxide semiconductor, and is a composition In which a nano-particle-like region mainly composed of Ga is observed In part and a nano-particle-like region mainly composed of In is observed In part In a material composition containing In, Ga, Zn and O, and these regions are irregularly dispersed In a mosaic shape.

The CAC-OS does not contain a laminate structure of two or more films different in composition. For example, a structure composed of two layers of a film containing In as a main component and a film containing Ga as a main component is not included.

Note that GaO is sometimes not observed_X3A region containing as a main component In_X2Zn_Y2O_Z2Or InO_X1Is a well-defined boundary between regions of major composition.

When kinds or more selected from aluminum, yttrium, copper, vanadium, beryllium, boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, and the like are contained In the CAC-OS In place of gallium, the CAC-OS is configured such that a nano-particle-like region containing the element as a main component is observed In part and a nano-particle-like region containing In as a main component is observed In part and is randomly dispersed In a mosaic shape.

In the case of forming the CAC-OS by the sputtering method, or more selected from an inert gas (typically argon), an oxygen gas, and a nitrogen gas can be used as the film forming gas, and the flow ratio of the oxygen gas in the total flow of the film forming gas at the time of film formation is lower, and for example, the flow ratio of the oxygen gas is set to 0% or more and less than 30%, preferably 0% or more and 10% or less.

CAC-OS is characterized in that when measured by an Out-of-plane method of according to X-ray diffraction (XRD) measurement method using a theta/2 theta scan, no clear peak is observed.

In addition, in the electron diffraction pattern of CAC-OS obtained by irradiating an electron beam (also referred to as a nanobeam) having a beam diameter of 1nm, an annular region having high brightness and a plurality of bright spots in the annular region were observed. From this, it is known that the crystal structure of the CAC-OS has an nc (nano-crystal) structure having no orientation in the plane direction and the cross-sectional direction, from the electron diffraction pattern.

In addition, for example, In the CAC-OS of In-Ga-Zn oxide, it was confirmed that, based on an EDX-plane analysis image (EDX-mapping) obtained by Energy Dispersive X-ray spectrometry (EDX: Energy Dispersive X-ray spectroscopy): with GaO_X3A region containing as a main component and In_X2Zn_Y2O_Z2Or InO_X1The main component region is unevenly distributed and mixed.

The CAC-OS has a structure different from that of an IGZO compound in which metal elements are uniformly distributed, and has properties different from those of the IGZO compound. In other words, CAC-OS has a GaO_X3Etc. as main component and In_X2Zn_Y2O_Z2Or InO_X1The regions having the main components are separated from each other, and the regions having the elements as the main components are formed in a mosaic shape.

In here, In_X2Zn_Y2O_Z2Or InO_X1The conductivity of the region having the main component is higher than that of GaO_X3Etc. as the main component. In other words, when carriers flow In_X2Zn_Y2O_Z2Or InO_X1The region containing the main component exhibits conductivity of the oxide semiconductor. Therefore, when In is used_X2Zn_Y2O_Z2Or InO_X1When the region as a main component is distributed in a cloud shape in the oxide semiconductor, high field-effect mobility (μ) can be achieved.

In another aspect of , the composition is GaO_X3Etc. as main componentHas higher insulating property than In_X2Zn_Y2O_Z2Or InO_X1Is the region of the main component. In other words, when GaO is used_X3When the region containing the main component is distributed in the oxide semiconductor, leakage current can be suppressed, and a good switching operation can be achieved.

Therefore, when CAC-OS is used for the semiconductor element, the heat radiation is caused by GaO_X3Insulation property of the like and the cause of In_X2Zn_Y2O_Z2Or InO_X1Can realize high-current (I)_on) And high field effect mobility (μ).

In addition, the semiconductor element using the CAC-OS has high reliability. Therefore, CAC-OS is suitable for constituent materials of various semiconductor devices.

Fig. 9 (a) is a diagram illustrating examples of the cross section of the pixel shown in fig. 8 (a), the layer 61 includes a pn junction photodiode using silicon as a photoelectric conversion layer as the photoelectric conversion element 101, and the layer 62 includes a Si transistor or the like constituting a pixel circuit.

In the photoelectric conversion element 101, the layer 65a may be p⁺Type region, layer 65b is n-type region and layer 65c is n⁺A molding region. In addition, the layer 65b is provided with a region 36 connecting the power supply line with the layer 65 c. For example, region 36 may be p⁺A molding region.

Although the Si transistor has a planar structure in which the silicon substrate 40 has a channel formation region as shown in fig. 9 a, a structure in which the silicon substrate 40 includes a fin-type semiconductor layer may be employed as shown in fig. 12a and 12B. Fig. 12 (a) corresponds to a cross section in the channel length direction, and fig. 12 (B) corresponds to a cross section in the channel width direction.

As shown in fig. 12 (C), a transistor including a semiconductor layer 45 of a silicon thin film may be used. For example, the semiconductor layer 45 may be single crystal Silicon (SOI) formed over an insulating layer 46 on a Silicon substrate 40.

Fig. 9 (a) shows an example in which the components of the layer 61 and the components of the layer 62 are electrically connected by a bonding technique.

An insulating layer 42, a conductive layer 33, and a conductive layer 34 are provided over the layer 61, the conductive layer 33 and the conductive layer 34 have a region where the insulating layer 42 is buried, the conductive layer 33 is electrically connected to the layer 65a, the conductive layer 34 is electrically connected to the region 36, and the surfaces of the insulating layer 42, the conductive layer 33, and the conductive layer 34 are planarized to degrees.

An insulating layer 41, a conductive layer 31, and a conductive layer 32 are provided over the layer 62, the conductive layer 31 and the conductive layer 32 have a region where the insulating layer 41 is buried, the conductive layer 32 is electrically connected to a power supply line, the conductive layer 31 is electrically connected to of the source and the drain of the transistor 102, and the surfaces of the insulating layer 41, the conductive layer 31, and the conductive layer 32 are planarized so that the heights thereof are .

Here, the main components of the conductive layer 31 and the conductive layer 33 are preferably the same metal element. The main components of the conductive layers 32 and 34 are preferably the same metal element. The insulating layer 41 and the insulating layer 42 are preferably made of the same composition.

For example, Cu, Al, Sn, Zn, W, Mo, Ag, Pt, Au, or the like can be used as the conductive layers 31, 32, 33, and 34. From the viewpoint of ease of bonding, Cu, Al, W, or Au is preferably used. In addition, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, titanium nitride, or the like can be used for the insulating layers 41 and 42.

In other words, it is preferable to use the same metal material as the above-described metal material for the combination of the conductive layer 31 and the conductive layer 33 and the combination of the conductive layer 32 and the conductive layer 34. Further, it is preferable to use the same insulating material as the insulating material described above for both the insulating layer 41 and the insulating layer 42. By adopting the above configuration, bonding can be performed with the boundary between the layer 61 and the layer 62 as a bonding position.

By the bonding step, each electrical connection of the combination of the conductive layer 31 and the conductive layer 33 and the combination of the conductive layer 32 and the conductive layer 34 can be obtained. In addition, a mechanically strong connection of the insulating layer 41 and the insulating layer 42 can be obtained.

When bonding the metal layers, a surface activation bonding method may be used. In this method, the surface is bonded by removing an oxide film, an impurity-adsorbing layer, and the like on the surface by sputtering treatment or the like, and bringing the cleaned and activated surface into contact with each other. Alternatively, a diffusion bonding method in which surfaces are bonded by using a combination of temperature and pressure may be used. The above-described methods can all be combined at the atomic level, and thus excellent electrical and mechanical bonding can be obtained.

In the case of bonding insulating layers, a hydrophilic bonding method or the like may be used, in which after high flatness is obtained by polishing or the like, surfaces hydrophilically treated with oxygen plasma or the like are brought into contact to temporarily bond, and dehydration is performed by heat treatment to thereby perform main bonding. Hydrophilic bonding also occurs at the atomic level, and therefore mechanically excellent bonding can be obtained.

In the case of the laminate layer 61 and the layer 62, the insulating layer and the metal layer are mixed at each bonding surface, and therefore, for example, a surface activation bonding method and a hydrophilic bonding method may be combined.

For example, a method of cleaning the surface after polishing, performing an anti-oxygen treatment on the surface of the metal layer, and then performing a hydrophilic treatment to perform bonding may be employed. Further, a metal such as Au, which is difficult to oxidize, may be used as the surface of the metal layer, and hydrophilic treatment may be performed. In addition, a bonding method other than the above-described method may be used.

Fig. 9 (B) is a cross-sectional view of the case where a pn junction photodiode using a selenium-based material as a photoelectric conversion layer is used as the layer 61 of the pixel shown in fig. 8 (a), the layer 66a is included as electrodes, the layers 66B and 66c are included as photoelectric conversion layers, and the layer 66d is included as another electrodes.

In this case, layer 61 may be disposed directly on layer 62. Layer 66a is electrically connected to the source or drain of transistor 102. Layer 66d is electrically connected to the power supply line through conductive layer 37.

Fig. 10 (a) is a diagram illustrating examples of the cross section of the pixel shown in fig. 8 (B) as the photoelectric conversion element 101, the layer 61 includes a pn junction photodiode using silicon as a photoelectric conversion layer, the layer 62 includes a Si transistor or the like, the layer 63 includes an OS transistor or the like, and fig. 10 (a) illustrates a structural example in which the adhesive layer 61 and the layer 63 are electrically connected.

Fig. 10 (a) shows that the OS transistor is a self-aligned structure, but may be a non-self-aligned structure as shown in fig. 12 (D).

Although the structure in which the transistor 102 includes the back gate 35 is shown, a structure including a back gate may be employed. As shown in fig. 12 (E), the back gate 35 may be electrically connected to the front gate of the transistor facing thereto. Alternatively, a structure may be adopted in which a fixed potential different from that of the front gate can be supplied to the back gate 35.

An insulating layer 43 having a function of preventing diffusion of hydrogen is provided between a region where the OS transistor is formed and a region where the Si transistor is formed, hydrogen in the insulating layer provided in the vicinity of a channel formation region of the transistors 107 and 108 terminates dangling bonds of silicon, and shows that hydrogen in the insulating layer provided in the vicinity of the channel formation region of the transistor 102 may cause generation of carriers in the oxide semiconductor layer.

By enclosing hydrogen in layers by providing the insulating layer 43, the reliability of the transistors 107 and 108 can be improved, and at the same time, since diffusion of hydrogen from layers to another layers can be suppressed, the reliability of the transistor 102 can be improved.

For the insulating layer 43, for example, aluminum oxide, aluminum oxynitride, gallium oxide, gallium oxynitride, yttrium oxide, yttrium oxynitride, hafnium oxide, hafnium oxynitride, yttria-stabilized zirconia (YSZ), or the like can be used.

Fig. 10 (B) is a cross-sectional view illustrating a case where a pn junction photodiode using a selenium-based material as a photoelectric conversion layer is used as the layer 61 of the pixel shown in fig. 8 (B). Layer 61 may be disposed directly on layer 63. The details of the layers 61, 62, 63 can be found in the above description.

Fig. 11 (a) is a diagram illustrating the structure of fig. 10. The sensor region is constituted by the layer 61 having the photoelectric conversion element 101 and the layer 63 having the OS transistor. The operation region is constituted by a layer 63 having a Si transistor or the like. The operation region includes the transistors 107 and 108 in the pixel, and the circuits of the pooling circuit and the drivers 11, 12, and 13 of embodiment 1. By the stacked structure having the sensor region and the operation region, the circuit area can be reduced.

Fig. 11 (B) is a photograph of a cross section of the sensor region and a photograph of a cross section of the calculation region. The sensor region is composed of a pn junction photodiode and an OS transistor (OSFET) each having a selenium-based material as a photoelectric conversion layer, and the operation region is composed of a Si transistor (SiFET) to constitute various circuits.

< structural elements of other pixels >

Fig. 13 (a) is a perspective view showing an example in which a color filter or the like is added to a pixel of an -mode image pickup device according to the present invention, and the perspective view also shows a cross section of a plurality of pixels, an insulating layer 80 is formed on the layer 61 on which the photoelectric conversion element 101 is formed, a silicon oxide film or the like having high transparency to visible light may be used for the insulating layer 80, a structure in which a silicon nitride film is stacked may be used as a passivation film, and a structure in which a dielectric film such as hafnium oxide is stacked may be used as an antireflection film.

A light-shielding layer 81 may be formed on the insulating layer 80. The light-shielding layer 81 has a function of preventing mixing of light transmitted through the upper color filter. As the light-shielding layer 81, a metal layer of aluminum, tungsten, or the like can be used. In addition, the metal layer and a dielectric film having a function of an antireflection film may be laminated.

An organic resin layer 82 used as a planarizing film may be provided on the insulating layer 80 and the light-shielding layer 81. In addition, a color filter 83 ( color filters 83a, 83b, 83c) is formed in each pixel. For example, the color filters 83a, 83B, and 83C are made to have colors of R (red), G (green), B (blue), Y (yellow), C (cyan), M (magenta), and the like, whereby a color image can be obtained.

An insulating layer 86 or the like having transparency to visible light may be provided on the color filter 83.

As shown in fig. 13 (B), an optical conversion layer 85 may be used instead of the color filter 83. With this configuration, an imaging device capable of obtaining images in various wavelength regions can be formed.

For example, when a color filter that blocks light of a wavelength of visible light or less is used as the optical conversion layer 85, an infrared imaging device can be obtained. When a color filter that blocks light of a wavelength of near infrared rays or less is used as the optical conversion layer 85, a far infrared imaging device can be obtained. Further, a color filter which blocks light of a wavelength of visible light or longer is used as the optical conversion layer 85, whereby an ultraviolet imaging device can be obtained. A color filter for visible light may be combined with a color filter for infrared or ultraviolet rays.

In addition, by using a scintillator for the optical conversion layer 85, an imaging apparatus for obtaining an image that visualizes radiation intensity, such as an X-ray imaging apparatus, can be formed. When radiation such as X-rays transmitted through an object enters a scintillator, the radiation is converted into light (fluorescence) such as visible light or ultraviolet light by a photoluminescence phenomenon. Image data is obtained by detecting the light by the photoelectric conversion element 101. The imaging device having this configuration may be used for a radiation detector or the like.

The scintillator contains: when a scintillator is irradiated with radiation such as X-rays or gamma rays, the scintillator absorbs energy of the radiation and emits visible light or ultraviolet light. For example, Gd may be used₂O₂S：Tb、Gd₂O₂S：Pr、Gd₂O₂S：Eu、BaFCl：Eu、NaI、CsI、CaF₂、BaF₂、CeF₃LiF, LiI, ZnO, and the like are dispersed in a resin or ceramic.

In addition, in the photoelectric conversion element 101 using the selenium-based material, since radiation such as X-rays can be directly converted into electric charges, a scintillator does not need to be used.

As shown in fig. 13 (C), a microlens array 84 may be provided on the color filter 83. The light transmitted through each lens of the microlens array 84 is irradiated to the photoelectric conversion element 101 via the color filter 83 provided thereunder. Further, the microlens array 84 may be provided on the optical conversion layer 85 shown in fig. 13 (B).

< example of Structure of Package and Module >

Next, examples of a package and a camera module that house an image sensor chip will be described, and the configuration of the image pickup device described above can be used as the image sensor chip.

Fig. 14 (a1) is an external perspective view of the top side of a package in which an image sensor chip is housed, the package including a package substrate 410 to which an image sensor chip 450 is fixed, a glass cover plate 420, an adhesive 430 to which the image sensor chip is bonded, and the like.

Fig. 14 (a2) is an external perspective view of the bottom side of the package, and includes BGA (Ball Grid Array) with solder balls as bumps 440 on the bottom.

Fig. 14 (a3) is a perspective view of a package in which a glass cover 420 and portion of an adhesive 430 are omitted, an electrode pad 460 is formed on a package substrate 410, the electrode pad 460 is electrically connected to a bump 440 through a through hole, and the electrode pad 460 is electrically connected to an image sensor chip 450 through a wire 470.

Fig. 14 (B1) is an external perspective view of a camera module in which an image sensor chip is housed on the top surface side of a lens body package, the camera module including a package substrate 411 for fixing an image sensor chip 451, a lens cover 421, a lens 435, and the like, and an IC chip 490 having functions of a driving circuit, a signal conversion circuit, and the like of an imaging device is provided between the package substrate 411 and the image sensor chip 451, and has a configuration as an SiP (System in package).

Fig. 14 (B2) is an external perspective view of the bottom surface side of the camera module, and the bottom surface and the side surfaces of the package substrate 411 have a structure of QFN (Quad flat no-lead package) provided with a receiving land 441, and it is noted that the structure is examples, and QFP (Quad flat package) or the BGA described above may be provided.

Fig. 14 (B3) is a perspective view of the module shown without the lens cover 421 and the portion of the lens 435, the land 441 is electrically connected to the electrode pad 461, and the electrode pad 461 is electrically connected to the image sensor chip 451 or the IC chip 490 via a lead 471.

By housing the image sensor chip in the package of the above-described type, the image sensor chip can be easily mounted on a printed circuit board or the like, and thus can be mounted on various semiconductor devices and electronic apparatuses.

As described above, the structure and method described in this embodiment can be used in combination with the structures and methods described in other embodiments as appropriate.

(embodiment mode 3)

Examples of electronic devices that can use the -format image pickup devices according to the present invention include display devices, personal computers, image storage devices and image playback devices provided with a recording medium, mobile phones, portable game machines, portable data terminals, electronic book readers, image pickup devices such as video cameras and digital cameras, goggle-type displays (head mounted displays), navigation systems, audio playback devices (car audio systems, digital audio players, and the like), copying machines, facsimile machines, printers, multifunction printers, Automated Teller Machines (ATMs), vending machines, and the like, and specific examples of these electronic devices are shown in fig. 15.

Fig. 15 (a) shows a monitoring camera including a stand 951, a camera unit 952, a protective cover 953, and the like, the camera unit 952 is provided with a rotating mechanism and the like, and the periphery can be photographed by being installed on a ceiling, and image pickup devices of systems of the present invention can be provided as members for obtaining an image in the camera unit, note that the "monitoring camera" is a name similar to and is not limited to its use, and for example, a device having a function of a monitoring camera is called a video camera or a video camera.

Fig. 15 (B) shows a video camera including a th housing 971, a second housing 972, a display portion 973, operation keys 974, a lens 975, a connection portion 976, and the like, wherein the operation keys 974 and the lens 975 are provided in the th housing 971, and the display portion 973 is provided in the second housing 972, and image pickup devices of the present invention can be provided as members for obtaining images in the video camera.

Fig. 15 (C) shows a digital camera including a housing 961, a flash button 962, a microphone 963, a light emitting portion 967, a lens 965, and the like, and members of the members used for obtaining images in the digital camera may include image pickup devices according to the present invention.

Fig. 15 (D) shows a wristwatch-type information terminal including a display unit 932, a case/wrist band 933, a camera 939, and the like, the display unit 932 may include a touch panel for operating the information terminal, the display unit 932 and the case/wrist band 933 are flexible and suitable for wearing on the body, and the information terminal may include types of image pickup devices of the present invention as members for acquiring images.

Fig. 15 (E) shows examples of a mobile phone including a housing 981, a display portion 982, operation buttons 983, an external connection interface 984, a speaker 985, a microphone 986, a camera 987, and the like, in which the display portion 982 includes a touch sensor, and various operations such as making a call or inputting characters can be performed by touching the display portion 982 with a finger, a stylus, and the like, and image pickup devices according to the present invention can be provided as members for obtaining images in the mobile phone.

Fig. 15 (F) shows a portable data terminal including a housing 911, a display portion 912, a camera 919, and the like, which can input and output information by a touch panel function provided in the display portion 912, and which can include image pickup devices according to the present invention as members used for obtaining images in the portable data terminal.

This embodiment can be combined with the description of the other embodiments as appropriate.

In addition, in the present specification and the like, a Display device, a light-emitting element, and a light-emitting device, which is a device including a Display element, may be implemented in various forms or include various elements, a Display device, a light-emitting element, or a light-emitting device, such as an EL (electroluminescence) element (an EL element including an organic substance and an inorganic substance, an organic EL element, an inorganic EL element), an LED chip (a white LED chip, a red LED chip, a green LED chip, a blue LED chip, and the like), a transistor (a transistor which emits light according to a current), a Plasma Display Panel (PDP), an Electron-emitting element, a Display element using a carbon nanotube, a liquid crystal element, an electronic ink, an electrowetting element, an electrophoretic element, a Display element using a MEMS (micro-electro-mechanical system) (for example, a Grating Light Valve (GLV), a Digital Micromirror Device (DMD), a DMS (digital micromirror device), a MIRASOL (a trademark registered in japan), an IMOD (interference modulation) element, a MEMS Display element, a fast type MEMS Display element, a quantum dot, a Display device, a silicon nitride, a silicon-organic light-emitting diode, a silicon-based on-organic light-emitting diode, organic light-emitting diode, or the like, organic light-emitting diode, organic.

Note that this embodiment mode can be combined with other embodiment modes shown in this specification as appropriate.

(supplementary notes on the description of the present specification, etc.)

Hereinafter, the respective configurations and explanations of the above embodiments will be described with reference to the drawings.

< notes attached to embodiments of the present invention shown in the embodiments >

The structures described in the respective embodiments can be combined with the structures described in the other embodiments as appropriate to constitute modes of the present invention, and when a plurality of configuration examples are described in modes, the configuration examples can be combined as appropriate.

In addition, the contents described in a certain embodiment (or portion thereof) may be applied/combined/replaced with other contents described in this embodiment (or portion thereof) and at least contents of the contents described in another or more other embodiments (or portion thereof).

Note that the content described in the embodiments refers to content described in various figures or content described in a text described in the specification in each embodiment.

In addition, further figures may be constructed by combining a figure shown in an implementation (or portion thereof) with at least figures from other portions of the figure, other figures shown in the implementation (or portion thereof), and figures shown in another or more other implementations (or portion thereof).

< accompanying notation of ordinal number >

In this specification and the like, ordinal numbers such as "", "second", "third", and the like are added to avoid confusion of constituent elements, and therefore, they are not added to limit the number of constituent elements, and they are not added to limit the order of constituent elements.

< accompanying notes for description of drawings >

However, those skilled in the art will readily understand that points of the present invention are capable of being embodied in many different forms and that the embodiments can be modified in various forms and that the details thereof can be changed without departing from the spirit and scope of the present invention.

For convenience, in this specification and the like, terms such as "upper" and "lower" are used to describe positional relationships of constituent elements with reference to the drawings. The positional relationship of the components is changed as appropriate in accordance with the direction in which each component is described. Therefore, the words of the display arrangement are not limited to those described in the present specification, and the expression may be appropriately changed depending on the case.

For example, when the term "electrode B on the insulating layer a" is described, it is not necessary to form the electrode B in such a manner that the electrode B directly contacts the insulating layer a , and the term "upper" or "lower" may include a case where another component is included between the insulating layer a and the electrode B.

In the drawings, the size, the thickness of layers, or the region may be exaggerated for clarity, and thus the present invention is not limited to the above-described dimensions .

In the drawings such as the perspective view, some components may not be illustrated for clarity.

In the drawings, the same constituent elements, constituent elements having the same function, constituent elements made of the same material, constituent elements formed at the same time, and the like may be shown by the same reference numerals , and redundant description may be omitted.

< accompanying notes on description that can be modified >

In this specification and the like, when a connection relationship of a transistor is described, of a source and a drain is referred to as " of the source and the drain" ( th electrode or th terminal), and another of the source and the drain is referred to as "another of the source and the drain" (second electrode or second terminal), because the source and the drain of the transistor are interchanged depending on a structure, an operating condition, and the like of the transistor.

In two input/output terminals serving as a source or a drain, terminals are used as sources and terminals are used as drains depending on the type of the transistor or the potential level supplied to each terminal.

Note that in this specification and the like, the term "electrode" or "wiring" does not functionally limit its constituent elements, and for example, "electrode" may be used as the portion of "wiring" or vice versa.

Note that in this specification and the like, a voltage and a potential may be appropriately exchanged, and a voltage refers to a potential difference from a reference potential, and for example, when the reference potential is a ground potential, the ground potential may be referred to as a potential, and the ground potential is not , which means 0 v.

In this specification and the like, terms such as "film" and "layer" may be interchanged depending on the situation or state. For example, the "conductive layer" may be converted to a "conductive film". In addition, the "insulating film" may be converted into an "insulating layer". In addition, other words may be used instead of words such as "film" and "layer" depending on the situation or state. For example, a "conductive layer" or a "conductive film" may be converted into a "conductor". Further, for example, an "insulating layer" or an "insulating film" may be converted into an "insulator".

In this specification and the like, terms such as "wiring", "signal line", and "power supply line" may be interchanged depending on the situation or state. For example, the "wiring" may be converted into a "signal line". In addition, for example, the "wiring" may be converted into a "power supply line". Vice versa, a "signal line" or a "power supply line" may be sometimes converted to a "wiring". Sometimes the "power line" may be converted to a "signal line". Vice versa, the "signal line" may sometimes be converted to a "power line". In addition, "potentials" applied to wirings can be mutually converted into "signals" according to the situation or the state. Vice versa, a "signal" may sometimes be converted into an "electric potential".

< notes on definition of words and sentences >

Next, definitions of words and phrases related to the above embodiments will be described.

Impurities relating to semiconductors

When the semiconductor is an oxide semiconductor, for example, an group element, a second group element, a thirteenth group element, a fourteenth group element, a fifteenth group element, or a transition metal other than the main component, particularly, hydrogen (also contained in water), lithium, sodium, silicon, boron, phosphorus, carbon, nitrogen, and the like are given as impurities for changing the characteristics of the semiconductor.

Transistors (transistors)

In this specification, a transistor refers to an element including at least three terminals, i.e., a gate, a drain, and a source. The transistor has a channel formation region between a drain (drain terminal, drain region, or drain electrode) and a source (source terminal, source region, or source electrode). By supplying a voltage exceeding a threshold voltage between the gate and the source, a channel can be formed in the channel formation region to flow a current between the source and the drain.

In addition, when transistors having different polarities are used, or when the direction of current flow during circuit operation changes, the functions of the source and the drain may be interchanged. Therefore, in this specification and the like, "source" and "drain" may be interchanged with each other.

Switch(s)

In this specification and the like, a switch is an element having a function of controlling whether or not to allow a current to flow by being turned into an on state (on state) or an off state (off state). Alternatively, the switch refers to an element having a function of selecting and switching a current path.

For example, an electrical switch or a mechanical switch or the like may be used. In other words, the switch is not limited to a specific switch as long as the current can be controlled.

Examples of the electric switch include a transistor (e.g., a bipolar transistor or a MOS transistor), a diode (e.g., a PN diode, a PIN diode, a schottky diode, a metal-insulator-metal (MIM) diode, a metal-insulator-semiconductor (MIS) diode, or a diode-connected transistor), or a logic circuit combining these elements.

When a transistor is used as a switch, the "on state" of the transistor refers to a state in which a source electrode and a drain electrode of the transistor are electrically short-circuited. The "non-conductive state" of the transistor refers to a state in which a source electrode and a drain electrode of the transistor are electrically disconnected. When only a transistor is used as a switch, the polarity (conductivity type) of the transistor is not particularly limited.

As examples of the mechanical switch, there is a switch using MEMS (micro electro mechanical system) technology such as a Digital Micromirror Device (DMD) which has an electrode mechanically movable and operates by moving the electrode to control conduction and non-conduction.

Connection (connection)

Note that, in this specification and the like, when it is described that "X is connected to Y", the following cases are included: the case where X and Y are electrically connected; the case where X and Y are functionally linked; and X is directly linked to Y. Therefore, the connection relation is not limited to the predetermined connection relation such as the connection relation shown in the drawings or the description, and includes connection relations other than the connection relation shown in the drawings or the description.

X and Y used herein are objects (e.g., devices, elements, circuits, wirings, electrodes, terminals, conductive films, layers, and the like).

As examples of the case where X and Y are electrically connected, or more elements capable of electrically connecting X and Y (for example, a switch, a transistor, a capacitor, an inductor, a resistor, a diode, a display element, a light-emitting element, a load, and the like) may be connected between X and Y.

As examples of the case where X and Y are functionally connected, or more circuits capable of functionally connecting X and Y (for example, a logic circuit (an inverter, a NAND circuit, a NOR circuit, or the like), a signal conversion circuit (a DA conversion circuit, an AD conversion circuit, a γ (gamma) correction circuit, or the like), a potential level conversion circuit (a power supply circuit (a voltage boosting circuit, a voltage dropping circuit, or the like), a level converter circuit that changes a potential level of a signal, or the like), a voltage source, a current source, a switching circuit, an amplification circuit (a circuit capable of increasing a signal amplitude, a current amount, or the like, an operational amplifier, a differential amplification circuit, a source follower circuit, a buffer circuit, or the like), a signal generation circuit, a storage circuit, a control circuit, or the like) may be connected between X and Y.

When it is explicitly stated that "X is electrically connected to Y", the following cases are included: a case where X and Y are electrically connected (in other words, a case where X and Y are connected with another element or another circuit interposed therebetween); a case where X and Y are functionally connected (in other words, a case where X and Y are functionally connected with another circuit interposed therebetween); and X and Y are directly connected (in other words, X and Y are connected without interposing another element or another circuit). In other words, when "electrical connection" is explicitly described, the same is true as when only "connection" is explicitly described.

Note that, for example, in the case where the source (or the th terminal or the like) of the transistor is electrically connected to X through Z1 (or not through Z1), the drain (or the second terminal or the like) of the transistor is electrically connected to Y through Z2 (or not through Z2), and in the case where the source (or the th terminal or the like) of the transistor is directly connected to the portion of Z1, another portion of Z1 is directly connected to X, the drain (or the second terminal or the like) of the transistor is directly connected to the portion of Z2, and another portion of Z2 is directly connected to Y, it can be shown as follows.

For example, it may be expressed that "X, Y" the source of the transistor (or terminal or the like) and the drain of the transistor (or second terminal or the like) are electrically connected to each other and are electrically connected in the order of X, the source of the transistor (or terminal or the like), the drain of the transistor (or second terminal or the like) and Y ". alternatively, it may be expressed that" the source of the transistor (or terminal or the like) is electrically connected to X, the drain of the transistor (or terminal or the like) is electrically connected to Y, and X, the source of the transistor (or terminal or the like), the drain of the transistor (or second terminal or the like), and Y are electrically connected in this order ". alternatively, it may be expressed that" X is electrically connected to Y through the source of the transistor (or terminal or the like) and the drain of the transistor (or second terminal or the like) ". X, the source of the transistor (or terminal or the like), the drain of the transistor (or the second terminal or the like), and Y are sequentially provided as being connected to each other". these terms are defined by using the same expression method as in the circuit structure, the specification of the description of the source of the transistor (or the transistor, the description of the term "the transistor, the transistor.

In addition, even if independent components are electrically connected to each other in a circuit diagram, components may have functions of a plurality of components, and for example, when portions of wirings are used as electrodes, conductive films have functions of two components of the wirings and the electrodes.

Parallel and perpendicular

In the present specification, "parallel" means a state in which an angle formed by two straight lines is-10 ° or more and 10 ° or less. Therefore, the angle is from-5 ° to 5 °. "substantially parallel" means a state in which the angle formed by two straight lines is-30 ° or more and 30 ° or less. The term "perpendicular" means a state in which an angle formed by two straight lines is 80 ° or more and 100 ° or less. Therefore, the angle is 85 ° or more and 95 ° or less. The term "substantially perpendicular" means a state in which an angle formed by two straight lines is 60 ° or more and 120 ° or less.

[ description of symbols ]

The camera device, 11: driver, 12: driver, 13: driver, 31: conductive layer, 32: conductive layer, 33: conductive layer, 34: conductive layer, 35: back gate, 36: region, 37: conductive layer, 40: silicon substrate, 41: insulating layer, 42: insulating layer, 43: insulating layer, 45: semiconductor layer, 46: insulating layer, 80: insulating layer, 81: light shielding layer, 82: organic resin layer, 83: color filter, 83 a: color filter, 83 b: color filter, 83 c: color filter, 84: microlens array, 85: optical conversion layer, 86: insulating layer, 100: pixel, 100 a: output terminal, 100 b: output terminal, 101: photoelectric conversion element, 102: transistor, 103: transistor, 104: capacitor, 105: transistor, 106: transistor, 107: transistor, 108: transistor, 111: wiring, 112: wiring, 113 a: wiring, 113 b: wiring, 113 c: wiring, 113 d: wiring, 114: wiring, 115: wiring, 117: wiring, 118: wiring 119, 200: wiring 119, 112: wiring, 113 a: wiring 972: wiring, camera module.