阅读说明：本技术 电流调整电路和方法 (Current regulation circuit and method ) 是由 郑吉麟 于 2018-06-28 设计创作，主要内容包括：本发明提供了一种电流调整电路和方法。该电流调整电路包括一第一反向器、一第二反向器、一P型晶体管、一N型晶体管以及一电容。第一反向器会接收一控制信号。第二反向器会接收上述控制信号。上述P型晶体管的一第一栅极耦接至上述第一反向器。上述N型晶体管耦接至上述P型晶体管,且上述N型晶体管的一第二栅极耦接至上述第二反向器。上述电容耦接至上述P型晶体管和上述N型晶体管于一节点,以及耦接至一低压差稳压器电路至一参考节点。本发明提出的电流调整电路和方法可以加快低压差稳压器电路从等待模式切换到启动模式的反应速度。(The invention provides a current regulation circuit and a method. The current adjusting circuit comprises a first reverser, a second reverser, a P-type transistor, an N-type transistor and a capacitor. The first inverter receives a control signal. The second inverter receives the control signal. A first gate of the P-type transistor is coupled to the first inverter. The N-type transistor is coupled to the P-type transistor, and a second gate of the N-type transistor is coupled to the second inverter. The capacitor is coupled to a node between the P-type transistor and the N-type transistor, and coupled to a reference node between a low dropout regulator circuit and the N-type transistor. The current regulation circuit and the method provided by the invention can accelerate the reaction speed of switching the low dropout regulator circuit from the waiting mode to the starting mode.)

1. A current regulation circuit, comprising:

a first inverter for receiving a control signal;

a second inverter for receiving the control signal;

a P-type transistor, wherein a first gate of the P-type transistor is coupled to the first inverter;

an N-type transistor coupled to the P-type transistor, wherein a second gate of the N-type transistor is coupled to the second inverter; and

a capacitor coupled to a node of the P-type transistor and the N-type transistor and coupled to a low dropout regulator circuit to a reference node.

2. The current regulation circuit of claim 1 wherein a first drain of the P-type transistor is coupled to the capacitor at the node and a first source of the P-type transistor receives an input voltage, and wherein a second source of the N-type transistor is coupled to the capacitor at the node and a second drain of the N-type transistor is coupled to a ground.

3. The current regulator circuit according to claim 1, wherein the P-type transistor is turned on and the N-type transistor is turned off when the control signal changes from a first level to a second level.

4. The current regulator circuit according to claim 3, wherein when the P-type transistor is turned on, the voltage level of the node is raised to a high level to increase the speed at which the voltage level of the reference node reaches a target voltage level.

5. The current regulator circuit according to claim 3, wherein when the control signal changes from the second level to the first level, the P-type transistor is turned off and the N-type transistor is turned on.

6. The current regulator circuit according to claim 5, wherein the voltage level of the node drops from a high level to a low level when the N-type transistor is turned on.

7. The current regulator circuit according to claim 6, wherein the voltage level of the node gradually decreases from the high level to the low level.

8. A current regulation method for a current regulation circuit, the current regulation method comprising:

turning on a P-type transistor of the current regulation circuit and turning off an N-type transistor of the current regulation circuit when a control signal changes from a first level to a second level, wherein the P-type transistor and the N-type transistor are coupled to a node; and

and increasing the voltage level of the node to a high level so as to accelerate the voltage level of a reference node coupled with the current regulation circuit and a low dropout regulator circuit to reach a target voltage level.

9. The method of claim 8, further comprising:

turning off the P-type transistor and turning on the N-type transistor when the control signal changes from the second level to the first level; and

and reducing the voltage level of the node from the high level to a low level.

10. The method of claim 9, further comprising:

gradually decreasing the voltage level of the node from the high level to the low level.

Technical Field

The present invention relates generally to current regulation, and more particularly to current regulation for accelerating the response speed of a low dropout regulator (LDO) circuit from standby mode to active mode.

Background

In the operation of the LDO circuit, the LDO circuit has a corresponding active mode and a standby mode (or a power saving mode).

However, in the conventional low dropout regulator circuit, when the low dropout regulator circuit is switched from the standby mode (the current of the amplifier inside the low dropout regulator circuit is small) to the start-up mode (the quiescent current of the amplifier inside the low dropout regulator circuit is large), it takes much time (refer to the description of fig. 1 below).

FIG. 1 is a diagram illustrating voltage levels of a control signal Vint _ en and a reference Node _ i-ref according to a conventional technique. As shown in fig. 1, when the control signal Vint _ en changes from low to high (i.e., the low dropout regulator circuit switches from the standby mode to the active mode), the voltage level of the reference Node _ i-ref of the low dropout regulator circuit changes from a low level to a target voltage level. However, since the voltage level of the reference Node _ i-ref of the low dropout regulator circuit reaches a target voltage level slowly from the low level, the current of the amplifier inside the low dropout regulator circuit also changes slowly (i.e., the response speed of the low dropout regulator circuit is slow) when the low dropout regulator circuit is switched from the standby mode to the active mode.

Therefore, when a back-end (external) circuit needs to pump a large current to the low dropout regulator circuit, a large voltage drop (voltage drop) may be generated instantaneously due to a small internal current and a slow response speed when the low dropout regulator circuit is switched from the standby mode to the start mode, so that a logic circuit connected to an output of the low dropout regulator circuit may malfunction.

Disclosure of Invention

In view of the foregoing background, the present invention provides a current regulation technique, and more particularly, to a current regulation technique for accelerating the response speed of a low dropout regulator (LDO) circuit from a standby mode to a start mode by a current regulation circuit and method.

According to an embodiment of the present invention, a current regulation circuit is provided. The current adjusting circuit comprises a first reverser, a second reverser, a P-type transistor, an N-type transistor and a capacitor. The first inverter receives a control signal. The second inverter receives the control signal. A first gate of the P-type transistor is coupled to the first inverter. The N-type transistor is coupled to the P-type transistor, and a second gate of the N-type transistor is coupled to the second inverter. The capacitor is coupled to a node between the P-type transistor and the N-type transistor, and coupled to a reference node between a low dropout regulator circuit and the N-type transistor.

According to an embodiment of the present invention, a current regulation method is provided. The current adjusting method is suitable for a current adjusting circuit, and the current adjusting method comprises the following steps: turning on a P-type transistor of the current regulation circuit and turning off an N-type transistor of the current regulation circuit when a control signal changes from a first level to a second level, wherein the P-type transistor and the N-type transistor are coupled to a node; and raising the voltage level of the node to a high level to speed up the voltage level of a reference node coupled between the current regulator circuit and a low dropout regulator circuit to a target voltage level, wherein the low dropout regulator circuit is in a standby mode when the control signal is at the first level, and the low dropout regulator circuit is in a start-up mode when the control signal is at the second level.

The current regulation circuit and the method provided by the invention can accelerate the reaction speed of switching the low dropout regulator circuit from the waiting mode to the starting mode.

Other additional features and advantages of the present invention will be apparent to those skilled in the art, and it is intended that various modifications and variations can be made in the current regulation circuit and method disclosed in the present application without departing from the spirit and scope of the invention.

Drawings

FIG. 1 is a diagram illustrating voltage levels of a control signal Vint _ en and a reference Node _ i-ref according to a conventional technique.

Fig. 2 is a circuit diagram of the current regulation circuit 100 according to an embodiment of the invention.

Fig. 3 is a diagram illustrating time intervals according to an embodiment of the invention.

FIG. 4 is a diagram illustrating the voltage levels of the control signal Vint _ en, the Node _0 and the reference Node _ i-ref according to an embodiment of the invention.

Fig. 5 is a flowchart 500 of a current adjustment method according to an embodiment of the invention.

Reference numerals:

100 current regulation circuit

110 first inverter

120 second inverter

200 low dropout regulator circuit

210 amplifier

220 third reverser

500 flow chart

C capacitor

Ground

N1 first N-type transistor

N2 second N-type transistor

N3 third N-type transistor

Node _0 Node

Node _ i-ref reference Node

N4 fourth N-type transistor

N5 fifth N-type transistor

P1 first P-type transistor

P2 second P-type transistor

S510, S520

Vint _ en control signal

Vint input voltage

Vref reference voltage

Detailed Description

The following description is of the best mode for carrying out the invention and is intended to be illustrative of the spirit of the invention and not limiting of the scope of the invention, which is defined by the claims.

Fig. 2 is a circuit diagram of the current regulation circuit 100 according to an embodiment of the invention. As shown in fig. 2, the current adjusting circuit 100 may include a first inverter 110, a second inverter 120, a first P-type transistor P1, a first N-type transistor N1, and a capacitor C. It should be noted that the circuit diagram in fig. 2 is only for convenience of describing the embodiment of the present invention, but the present invention is not limited thereto. The current regulator circuit 100 may also include other components. In addition, as shown in fig. 2, the current regulator circuit 100 is coupled to a Low Dropout (LDO) regulator circuit 200.

According to an embodiment of the present invention, the capacitor C may include a plurality of capacitors. According to the requirements of different capacitance values, capacitors with different sizes can be configured in the capacitor C.

As shown in fig. 2, the first inverter 110 is coupled to the first gate of the first P-type transistor P1, and the first inverter 110 receives a control signal Vint _ en from an external control circuit (not shown). In addition, the second inverter 120 is coupled to the second gate of the first N-type transistor 120, and the second inverter 110 also receives a control signal Vint _ en transmitted from an external control circuit (not shown).

In addition, as shown in fig. 2, a first drain of the first P-type transistor P1 is coupled to the capacitor C at the Node _0, a first source of the first P-type transistor P1 receives an input voltage Vint, a second source of the first N-type transistor N1 is coupled to the capacitor C at the Node _0, and a second drain of the first N-type transistor is coupled to a Ground. In addition, the capacitor C of the current regulator circuit 100 is coupled to the LDO circuit 200 at the reference Node _ i-ref.

Fig. 3 is a circuit diagram of a low dropout regulator (LDO) circuit 200 according to an embodiment of the invention. As shown in FIG. 3, the LDO circuit 200 may include an amplifier 210, a second P-type transistor P2, a second N-type transistor N2, a third N-type transistor N3, a fourth N-type transistor N4, a fifth N-type transistor N5, and a third inverter 220. It should be noted that the circuit diagram in fig. 3 is only for convenience of describing the embodiment of the present invention, but the present invention is not limited thereto. The LDO circuit 200 may also include other components. Further, particularly, the nodes shown in fig. 3, which are on the same line as the reference Node _ i-ref, may be regarded as the reference nodes Node _ i-ref.

As shown in fig. 3, the external control circuit (not shown) also sends a control signal Vint _ en to the low dropout regulator circuit 200 to control the low dropout regulator circuit 200 to operate in a standby mode or an active mode. For example, the LDO circuit 200 operates in the standby mode when the control signal Vint _ en is at a first level (e.g., a low level), and operates in the active mode when the control signal Vint _ en is at a second level (e.g., a high level).

In the embodiment of the invention, when the low dropout regulator circuit 200 is controlled to be in the standby mode, the first path (i.e., the third N-type transistor N3 and the fourth N-type transistor N4) and the second path (i.e., the fifth N-type transistor N5) of the low dropout regulator circuit 200 are both turned on, so that the voltage level of the reference Node _ i-ref is at a low level. When the LDO circuit 200 is controlled to be in the power-on mode, the first path (i.e., the third N-type transistor N3 and the fourth N-type transistor N4) of the LDO circuit 200 is turned off, but the second path (i.e., the fifth N-type transistor N5) is turned on, so that the voltage level of the reference Node _ i-ref is at a high level.

According to an embodiment of the present invention, when the control signal Vint _ en received by the first inverter 110 and the second inverter 110 is at the first level (e.g., low level), the first P-type transistor P1 is turned off, the first N-type transistor N1 is turned on, and the voltage at the Node _0 is at a low level. Since the first P-type transistor P1 is turned off and the first N-type transistor N1 is turned on, the current regulator circuit 100 is not activated when the control signal Vint _ en is at the first level (e.g., a low level), i.e., the current regulator circuit 100 does not adjust the voltage level of the reference Node _ i-ref. In addition, when the control signal Vint _ en received by the first inverter 110 and the second inverter 110 is at the second level (e.g., high level), the first P-type transistor P1 is turned on, the first N-type transistor N1 is turned off, and the voltage of the Node _0 is at a high level. Since the first P-type transistor P1 is turned on and the first N-type transistor N1 is turned off, the current regulator circuit 100 is activated to adjust the voltage level of the reference Node _ i-ref (i.e., increase the speed of the voltage level of Node _ i-ref to a target voltage level) when the control signal Vint _ en is at a second level (e.g., high level).

Therefore, according to an embodiment of the present invention, when the control signal Vint _ en changes from the first level (low level) to the second level (high level), the first P-type transistor P1 is turned on, the first N-type transistor N1 is turned off, and the voltage level of the Node _0 changes from low level to high level. When the voltage level of the Node _0 changes from the low level to the high level, the voltage level of the reference Node _ i-ref can be capacitively coupled through the capacitor C, so as to accelerate the speed at which the voltage level of the reference Node _ i-ref reaches a target voltage level. When the voltage level of the reference Node _ i-ref reaches the target voltage level faster, the current of the amplifier 210 in the LDO circuit 200 increases faster. Therefore, when the low dropout regulator circuit 200 switches from the standby mode to the start-up mode, the response speed of the low dropout regulator circuit 200 will be faster, thereby reducing the generation of the instantaneous large voltage drop (voltage drop).

In addition, according to an embodiment of the present invention, when the control signal Vint _ en changes from the second level (high level) to the first level (low level), the first P-type transistor P1 is turned off, the first N-type transistor N1 is turned on, and the voltage level of the Node _0 changes from high level to low level.

According to an embodiment of the present invention, the size of the first P-type transistor P1 disposed in the current regulator circuit 100 is larger than that of the first N-type transistor N1, so that when the control signal Vint _ en changes from the first level (low level) to the second level (high level), the voltage level of the Node _0 can immediately change from the low level to the high level, and when the control signal Vint _ en changes from the second level (high level) to the first level (low level), the voltage of the Node _0 gradually decreases from the high level to the low level (see fig. 4).

FIG. 4 is a diagram illustrating the voltage levels of the control signal Vint _ en, the Node _0 and the reference Node _ i-ref according to an embodiment of the invention. As shown in fig. 4, when the control signal Vint _ en changes from low level to high level (i.e., the low dropout regulator circuit 200 changes from the standby mode to the active mode), the voltage level of the Node _0 changes from low level to high level. When the voltage level of the Node _0 changes from the low level to the high level, the speed at which the voltage level of the reference Node _ i-ref reaches a target voltage level is increased.

Fig. 5 is a flowchart 500 of a current adjustment method according to an embodiment of the invention. The current adjusting method can be applied to the current adjusting circuit 100 of the present invention. In step S510, when a control signal changes from a first level to a second level, a P-type transistor of the current regulator circuit 100 is turned on, and an N-type transistor of the current regulator circuit 100 is turned off, wherein the P-type transistor and the N-type transistor are coupled to a Node _ 0. In step S520, the voltage level of the Node _0 is raised to a high level to speed up the speed at which the voltage level of a reference Node _ i-ref to which the current regulator circuit 100 and a low dropout regulator circuit are coupled reaches a target voltage level, wherein the low dropout regulator circuit is in a standby mode when the control signal is at the first level, and the low dropout regulator circuit is in a start-up mode when the control signal is at the second level.

According to an embodiment of the present invention, in the current regulation method, when the control signal changes from the second level to the first level, the P-type transistor of the current regulation circuit 100 is turned off, the N-type transistor of the current regulation circuit 100 is turned on, and the voltage level of the Node _0 is decreased from the high level to the low level.

According to the current adjusting method provided by the embodiment of the invention, when the control signal Vint _ en is changed from the first level (low level) to the second level (high level), the voltage level of the Node _0 of the current adjusting circuit 100 is changed from the low level to the high level, so as to increase the speed of the voltage level of the reference Node _ i-ref reaching the target voltage level. When the voltage level of the reference Node _ i-ref reaches the target voltage level, the current in the low dropout regulator circuit 200 increases faster. Therefore, when the low dropout regulator circuit 200 switches from the standby mode to the start-up mode, the response speed of the low dropout regulator circuit 200 will be faster, thereby reducing the generation of the instantaneous large voltage drop (voltage drop).

Reference numerals, such as "first", "second", etc., in the description and in the claims are used for convenience of description and do not have a sequential relationship with each other.

The above paragraphs use various levels of description. It should be apparent that the teachings herein may be implemented in a wide variety of ways, and that any specific architecture or functionality of the invention in an example is merely representative. Any person skilled in the art will appreciate, in light of the teachings herein, that the various aspects of the invention herein may be practiced independently or that more than two aspects may be practiced in combination.

Although the present invention has been described with reference to the above embodiments, it should be understood that various changes and modifications can be made therein by those skilled in the art without departing from the spirit and scope of the invention.