阅读说明：本技术 半导体装置的制造方法 (Method for manufacturing semiconductor device ) 是由 黄建桦 魏慈慧 蔡承孝 于 2019-03-19 设计创作，主要内容包括：本申请提供一种半导体装置的制造方法,所述方法包含：提供包含导电元件和层间电介质的一结构,其中所述层间电介质包含硅且围绕所述导电元件；形成一蚀刻停止层于所述导电元件和层间电介质之上,其中所述蚀刻停止层包含金属氧化物,其中所述蚀刻停止层包含与导电元件接触的第一部分和与层间电介质接触的第二部分；烘烤所述蚀刻停止层以将位于蚀刻停止层的第二部分中的金属氧化物转换为金属硅氧化物；以及选择性蚀刻所述蚀刻停止层以移除蚀刻停止层的第一部分,但不移除蚀刻停止层的第二部分。(The present application provides a method of manufacturing a semiconductor device, the method comprising: providing a structure comprising a conductive element and an interlayer dielectric, wherein the interlayer dielectric comprises silicon and surrounds the conductive element; forming an etch stop layer over the conductive element and the interlayer dielectric, wherein the etch stop layer comprises a metal oxide, wherein the etch stop layer comprises a first portion in contact with the conductive element and a second portion in contact with the interlayer dielectric; baking the etch stop layer to convert the metal oxide in the second portion of the etch stop layer to a metal silicon oxide; and selectively etching the etch stop layer to remove the first portion of the etch stop layer but not the second portion of the etch stop layer.)

1. A method of manufacturing a semiconductor device, the method comprising:

providing a structure comprising a conductive element and an interlayer dielectric, wherein the interlayer dielectric comprises silicon and surrounds the conductive element;

forming an etch stop layer over the conductive element and the interlayer dielectric, wherein the etch stop layer comprises a metal oxide, wherein the etch stop layer comprises a first portion in contact with the conductive element and a second portion in contact with the interlayer dielectric;

baking the etch stop layer to convert the metal oxide located in the second portion of the etch stop layer to a metal silicon oxide; and

selectively etching the etch stop layer to remove the first portion of the etch stop layer but not to remove the second portion of the etch stop layer.

Technical Field

Embodiments of the present invention relate to semiconductor manufacturing technology, and more particularly, to a method for forming a selectively removable etch stop layer in a semiconductor device.

Background

The semiconductor Integrated Circuit (IC) industry has experienced rapid growth. Technological advances in the materials and design of integrated circuits have resulted in generations of integrated circuits, each with smaller and more complex circuits than the previous generation. However, these advances have also increased the complexity of processing and manufacturing integrated circuits, and to achieve such advances, the same advances in integrated circuit processing and manufacturing are needed. As integrated circuit evolution progresses, as geometries (i.e., the smallest components that can be produced using a manufacturing process) shrink, the functional density (i.e., the number of interconnects per chip area) typically increases.

The shrinking geometries have led to challenges in semiconductor fabrication. For example, as the pitch between metal elements decreases, overlay control becomes more difficult because an equal amount of overlay shift now has a more significant impact on device performance (e.g., misaligned vias (via) may cause current leakage between such a via and an adjacent metal element). Overlay shift may reduce device performance and/or cause reliability problems. Thus, while existing semiconductor devices and their manufacture have been generally adequate for their intended purposes, they have not been satisfactory in all respects.

Disclosure of Invention

According to an embodiment of the present invention, there is provided a method of manufacturing a semiconductor device, including: providing a structure comprising a conductive element and an interlayer dielectric, wherein the interlayer dielectric comprises silicon and surrounds the conductive element; forming an etch stop layer over the conductive element and the interlayer dielectric, wherein the etch stop layer comprises a metal oxide, wherein the etch stop layer comprises a first portion in contact with the conductive element and a second portion in contact with the interlayer dielectric; baking the etch stop layer to convert the metal oxide in the second portion of the etch stop layer to a metal silicon oxide; and selectively etching the etch stop layer to remove the first portion of the etch stop layer but not the second portion of the etch stop layer.

According to an embodiment of the present invention, there is provided a semiconductor device including: a substrate; first and second conductive elements disposed on the substrate; an interlayer dielectric disposed on the substrate and between the first and second conductive elements; an etch stop layer comprising a metal silicon oxide extending over and in contact with the interlayer dielectric, wherein the etch stop layer does not extend over the first conductive element or the second conductive element; and a conductive via disposed over and in electrical contact with the first conductive element, wherein the conductive via is separated from the second conductive element by at least a portion of the interlayer dielectric and the etch stop layer.

According to an embodiment of the present invention, there is provided a method of manufacturing a semiconductor device, including: forming a first etch stop layer comprising a first portion in contact with a conductive element and comprising a second portion in contact with a first interlayer dielectric surrounding the conductive element, wherein the first portion of the first etch stop layer comprises a metal oxide and the second portion of the first etch stop layer comprises a metal silicon oxide; etching the first etch stop layer to remove a first portion of the first etch stop layer but not to remove a second portion of the first etch stop layer; forming a second etch stop layer over the second portion of the first etch stop layer and over the conductive element; forming a second interlayer dielectric on the second etch stop layer; etching an opening vertically through the second interlayer dielectric and the second etch stop layer to expose an upper surface of the conductive element; and filling the opening with a conductive material to form a conductive via in the opening, wherein the conductive via is in contact with the upper surface of the conductive element but is separated from the first interlayer dielectric by a second portion of the first etch stop layer.

Drawings

The embodiments of the present invention will be understood more fully from the detailed description given below and from the accompanying drawings. It is emphasized that, in accordance with industry standard practice, many of the features (features) are not drawn to scale. In fact, the dimensions of the various elements may be arbitrarily increased or reduced for clarity of discussion.

FIGS. 1A, 1B, 1C, 1D, 1E, 1F, 1G, 1H, and 1I are cross-sectional schematic views of a semiconductor device at various stages of manufacture according to an embodiment of the present invention.

Fig. 2 is a flow chart of a method of manufacturing a semiconductor device according to an embodiment of the present invention.

Description of the symbols:

100-semiconductor device

102 to substrate

110. 194-interconnect layer

120. 122-conductive element

130. 170 interlayer dielectric

140. 160-etching stop layer

142. 144 to part

150-etching solution

172-cap layer

174 hard mask layer

180-opening

190-conductive material

192-conductive hole

200-method

210. 220, 230, 240, 250, 252, 254, 256, 258 and 260 to the step of

Detailed Description

The following provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present embodiments. These are, of course, merely examples and are not intended to limit the embodiments of the invention. For example, references in the description to a first feature being formed over a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features are formed between the first and second features such that the first and second features are not in direct contact. Moreover, embodiments of the present invention may repeat reference numerals and/or letters in the various examples, for purposes of simplicity and clarity, and do not represent a particular relationship between the various embodiments and/or configurations discussed.

Furthermore, spatially relative terms, such as "below … …," "below … …," "below," "above … …," "above," and the like, may be used herein to facilitate describing the relationship of element(s) or component(s) to another element(s) or component(s) as shown. These spatially relative terms encompass different orientations of the device in use or during a procedure, and the orientation depicted in the figures. When the device is turned to a different orientation (rotated 90 degrees or otherwise), the spatially relative adjectives used herein will also be interpreted in terms of the turned orientation.

Further, when a number or range of numbers is described by the words "about", "about" and the like, the words are intended to cover numbers within a reasonable range, including numbers described, for example, within ± 10% of the number described or other values as would be understood by one of skill in the art. For example, the term "about 5 nm" includes a size range from 4.5nm to 5.5 nm.

The present invention relates generally to, but is not limited to, reducing or preventing problems associated with overlay control. Overlay may refer to alignment between various elements of different film layers in a semiconductor device, such as an integrated circuit chip. For example, an integrated circuit chip may include an interconnect structure comprised of multiple interconnect layers (also referred to as different metallization layers). Each interconnect layer may include one or more conductive elements, such as vias, contacts, or metal lines, surrounded by an interlayer dielectric (ILD). In some cases, a first conductive element in one interconnect level (e.g., an upper layer) may need to be electrically connected to a second conductive element in another interconnect level (e.g., a lower layer). Therefore, it is desirable that the two conductive elements be vertically aligned. If overlay control is not ideal, there may be a significant amount of misalignment between the two conductive elements, which may lead to problems such as overetching (tiger tooth pattern) of the interlayer dielectric next to the second conductive element. Over-etching can shorten the leakage path to adjacent conductive elements, which in turn can lead to reliability and/or performance problems, such as time-dependent dielectric breakdown (TDDB) or other current leakage problems.

In order to overcome the problems discussed above, embodiments of the present invention form a portion of an Etch Stop Layer (ESL) capable of increasing a leakage path length. In some embodiments, this is accomplished by first forming an etch stop layer (comprising a metal oxide) over the conductive elements and over an interlayer dielectric comprising silicon and surrounding the conductive elements. The etch stop layer is then baked at an elevated temperature to change its chemical composition. For example, a metal silicon oxide may be formed in a portion of the etch stop layer in contact with the interlayer dielectric because silicon penetrates into the etch stop layer to react with the metal oxide contained therein. Then, the etch stop layer is selectively removed using a wet etchant containing an alkaline amine (alkali amine). During the selective etching, the portion of the etch stop layer comprising the metal oxide is removed, but the portion of the etch stop layer comprising the metal oxide remains. The remaining etch stop layer portion protects the interlayer dielectric from being undesirably etched in a via (via hole) etch process.

One advantage of the present invention is that problems caused by overlay displacement are mitigated. For example, ideally, the vias should be aligned with the conductive elements. However, due to overlay displacement, the vias and conductive elements may be misaligned. Such misalignment would result in a portion of the interlayer dielectric underlying the via being inadvertently etched if a selectively removable etch stop layer was not implemented. When filling the via with metal, the unintentionally etched hole will also be filled, providing a conductive path closer to the next conductive element if the via is aligned. This may lead to reliability and/or performance issues such as breakdown voltage, time-varying dielectric breakdown, or leakage.

As previously mentioned, overlay control may not be optimal in real world semiconductor manufacturing, particularly as geometries shrink, which can lead to misalignment between vias and conductive elements. The etch selectivity of the etch stop layer disclosed herein helps prevent undesired etching of the interlayer dielectric adjacent the conductive elements and below the vias caused by misalignment. In accordance with various aspects of embodiments of the present invention, a silicon-containing etch stop layer protects portions of an interlayer dielectric located below a misaligned via from being etched. As a result, the resulting semiconductor device has better reliability and/or enhanced performance.

Various aspects of the present invention will now be described in more detail with reference to the appended drawings. In this regard, fig. 1A-1I illustrate schematic cross-sectional side views of a semiconductor device at various stages of manufacture in accordance with an embodiment of the present invention, while fig. 2 illustrates a flow chart of a method performed in accordance with an embodiment of the present invention.

Referring now to fig. 1A, a portion of a semiconductor device (or semiconductor structure) 100 is shown. The semiconductor device 100 includes a substrate 102, and the substrate 102 may be composed of silicon or other semiconductor materials such as germanium. The substrate 102 may also contain a compound semiconductor such as silicon carbide, gallium arsenide, indium arsenide, or indium phosphide. In some embodiments, the substrate 102 may comprise an alloy semiconductor, such as silicon germanium, silicon germanium carbide, gallium arsenic phosphide, or gallium indium phosphide. In some embodiments, the substrate 102 may comprise an epitaxial layer, such as an epitaxial layer overlying a bulk semiconductor. Various microelectronic elements may be formed in or on the substrate 102, such as transistor elements including source/drains and/or gates, isolation structures including Shallow Trench Isolation (STI), or any other suitable element.

The semiconductor device 100 also includes an interconnect layer 110. The interconnect layer 110 may be one of the interconnect layers in a multi-layer interconnect structure (MLI) that is formed over the substrate 102 and may include a plurality of patterned dielectric and conductive layers that provide interconnects (e.g., wires) between various microelectronic elements of the semiconductor device 100. Intermediate layers or elements may be present between the interconnect layer 110 and the substrate 102, but these film layers or elements are not shown for simplicity.

In one embodiment, the interconnect layer 110 includes a plurality of conductive elements (including conductive elements 120 and 122) and an interlayer dielectric 130 that partially or completely surrounds the conductive elements 120 and 122. Conductive elements 120 and 122 may comprise contacts, vias, or metal lines. In some embodiments, the conductive elements 120 and 122 comprise a conductive material, such as aluminum, an aluminum alloy, titanium nitride, tungsten, copper, a copper alloy, tantalum nitride, tungsten, ruthenium, rhodium, or a combination of the foregoing. When the conductive elements 120 and 122 comprise a metallic material, they are also referred to as metallic elements. It is noted that the conductive elements 120 and 122 do not include any silicon (either pure silicon or in the form of a silicide) because the conductive elements 120 and 122 should not react with the overlying film layers (e.g., the etch stop layer 140 as described below) during the baking process to form a silicide.

Unlike conductive elements 120 and 122, interlayer dielectric 130 may be a silicon-containing dioxide material, where silicon is present in various suitable forms. For example, the interlayer dielectric 130 may comprise silicon dioxide or a low-k dielectric material having a dielectric constant value that is less than that of silicon dioxide (approximately 4). In some embodiments, the low-k dielectric material comprises a porous organosilicate film, such as Siloxane (SiOCH), Tetraethoxysilane (TEOS) oxide, undoped silicate glass, boron-doped silicon oxide, such as borophosphosilicate glass (BPSG), Fused Silica Glass (FSG), phosphosilicate glass (PSG), boron-doped silicon dioxide, carbon-doped silicon dioxide, porous carbon-doped silicon dioxide, silicon carbonitride (SiCN), silicon oxycarbide (SiOCN), spin-on silicon-based dielectric polymers, or combinations thereof. It should be understood that a planarization process, such as Chemical Mechanical Polishing (CMP), may be performed on the interconnect layer 110 to flatten the upper surfaces of the conductive elements 120 and 122 and/or the interlayer dielectric 130.

Referring to FIG. 1B, a first etch stop layer 140 is deposited thereinAnd a wiring layer 110. The deposition process includes Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), Atomic Layer Deposition (ALD), thermal ALD, or a combination thereof. In some embodiments, the etch stop layer 140 comprises a metal oxide, such as aluminum oxide (AlOx), hafnium oxide (HfOx), titanium oxide (TiOx), manganese oxide (MnOx), vanadium oxide (VOx), other suitable metal oxides, or combinations of the foregoing. In some embodiments, the etch stop layer 140 has a thickness of between 10 and 60 angstroms

Of the entire thickness. Such a thickness range allows the etch stop layer 140 to not only provide adequate protection (in terms of leakage paths between the upper via structure and the underlying conductive elements), but also minimize parasitic capacitance between adjacent conductive elements 120 and 122 (since the dielectric constant value of the material in the etch stop layer 140 is higher than the dielectric constant value of the low dielectric constant material in the interlayer dielectric 130).

Referring to fig. 1C, the etch stop layer 140 undergoes a baking process at an elevated temperature. The prior art does not perform such a baking process. During baking, one or more portions 142 of the etch stop layer 140 in contact with the interlayer dielectric 130 change or transform its chemical composition, for example, silicon (in any suitable form) contained in the interlayer dielectric 130 migrates or penetrates into the etch stop layer 140 and then reacts with the metal oxide of the portions 142 of the etch stop layer to form a metal silicon oxide. In some embodiments, the portion 142 of the baked etch stop layer comprises a metal silicon oxide, such as aluminum silicon oxide (AlSiOx), hafnium silicon oxide (HfSiOx), titanium silicon oxide (TiSiOx), manganese silicon oxide (MnSiOx), vanadium silicon oxide (VSiOx), other suitable metal silicon oxides, or combinations of the foregoing. It is noted that silicon may be present in the metal silicon oxide in any suitable chemical form. However, during baking, one or more other portions 144 of the etch stop layer 140 in contact with the conductive elements 120 and 122 may not form any metal silicon oxide because the conductive elements 120 and 122 do not include any silicon material. As shown in fig. 1C, the chemical conversion is a self-alignment (self-aligning) process because portions 142 and 144 of the etch stop layer are aligned with respective edges of the interlayer dielectric 130 and the conductive elements 120 and 122. Note that even during the self-alignment process, silicon may not migrate or penetrate completely along vertical lines into the etch stop layer, and thus the edges of portions 142 and 144 of the etch stop layer may not be perfectly (striclly) aligned with the corresponding edges of interlayer dielectric 130 and conductive elements 120 and 122.

In some embodiments, the semiconductor device 100 having the etch stop layer 140 is baked at a temperature of 100 ℃ to 400 ℃. It is noted that the temperature may be varied during baking, for example according to a predetermined temperature profile. In some embodiments, the baking is continued for 30 seconds to 10 minutes. In some embodiments, the baking may be performed in an ambient gas comprising nitrogen (N)₂) Nitrogen and hydrogen (H)₂) A combination of nitrogen and an inert gas such as argon (Ar), or any other suitable gas composition. Suitable ambient gas (e.g. N)₂+H₂) The silicidation process is facilitated to be enhanced by allowing silicon to more readily penetrate into portions 142 of the etch stop layer.

Referring now to fig. 1D, a wet etching process is performed to selectively remove portions of the etch stop layer 140 from the upper surface of the semiconductor device 100. In one embodiment, the etching solution 150 is configured to leave the etch stop layer portion 142 in contact with the interlayer dielectric 130, but remove the etch stop layer portion 144 in contact with the conductive elements 120 and 122. In other words, the etched etch stop layer 140 remains on the upper surface of the interlayer dielectric 130, but does not remain on the upper surfaces of the conductive elements 120 and 122. As shown in fig. 1D, a step height profile or geometry is created along the upper surface of conductive elements 120 and 122.

The reason for selectively removing the etch stop layer 140 is the etch selectivity between the portions 142 and 144 of the etch stop layer, which after baking comprise different materials. In some embodiments, the etch selectivity between portions 142 and 144 of the etch stop layer is significant (e.g., about1: 30 or higher). That is, the etch rate of the portion 144 of the etch stop layer (which comprises a metal oxide) is at least 30 times faster than the etch rate of the portion 142 of the etch stop layer (which comprises a metal silicon oxide) when exposed to the etching solution 150. In some embodiments, the etch rate of the portion 144 of the etch stop layer is about every minuteOr higher. In addition, once the upper surfaces of the conductive elements 120 and 122 are exposed, the etching may be stopped because the etching solution 150 has a low etching rate on the conductive elements 120 and 122. In some embodiments, the etch rate of the conductive elements 120 and 122 does not exceed the rate of etching per minute

In some embodiments, the etching solution 150 comprises a basic amine, such as ammonium hydroxide (NH)₄OH), hydroxylamine (NH)₂OH), other suitable compounds, or combinations of the foregoing. The pH of the etching solution 150 may be set between 8 and 13 to prevent or minimize reaction between the silicon and the etching solution 150 (since silicon is more reactive in an acidic environment). In one embodiment, the concentration of the basic amine in the etching solution 150 is 8% or less (unless otherwise specified, percentages refer to weight). The hydroxide (OH-) in the basic amine creates an etch rate difference between the metal oxide (contained in the portion 144 of the etch stop layer) and the metal silicon oxide (contained in the portion 142 of the etch stop layer). Specifically, the following example formula indicates that the hydroxide reacts with the metal oxide to form a metal hydroxide (e.g., aluminum hydroxide) that is soluble in the etching solution 150, but that the hydroxide does not react with the metal silicon oxide:

example reaction in portion 144 of the etch stop layer: 2OH^-+3H₂O+Al₂O₃→2Al(OH)₄ ^- _(aq)

No reaction in the portion 142 of the etch stop layer: OH group^-+Al(Si)O_x→ no reaction.

To enhance the etching performance, the etching solution 150 may also include a solvent, such as diethylene glycol monomethyl ether (dmethyl ether), ethylene glycol (ethylene glycol), butyl diethylene glycol (butyl diethylene glycol), and dimethyl sulfoxide (dimethyl sulfoxide), any other suitable solvent, or a combination of the foregoing. In addition, the etching solution 150 may include a chelating agent, such as ethylenediaminetetraacetic acid (ethylenediaminetetraacetic acid), diethylenetriaminepentaacetic acid (diethylenetriaminepentaacetic acid), other suitable chelating agents, or a combination of the foregoing. In addition, the etching solution 150 may include a metal corrosion inhibitor to help prevent corrosion of the metal components. Suitable candidates for metal corrosion inhibitors may include Benzotriazole (BTA), dodecylamine (dodekylamine), or combinations of the foregoing. The etching solution 150 may also contain water, for example, at a concentration of 20% to 80%. In some embodiments, the wet etching process is performed at a temperature between room temperature and 60 ℃. Note that the temperature may be changed during etching. In some embodiments, the etching is continued for 1 to 5 minutes.

Referring now to fig. 1E, a deposition process is performed to form a second etch stop layer 160 over the semiconductor device 100. In some embodiments, the deposition process may include a chemical vapor deposition process, a physical vapor deposition process, an atomic layer deposition process, a thermal atomic layer deposition, or a combination of the foregoing. The second etch stop layer 160 may be conformally (conformaly) formed over the remaining portions of the etch stop layer 140 and over the upper surfaces of the conductive elements 120 and 122. In some embodiments, the etch stop layer 160 comprises a dielectric material, which may be the same or different material as the etch stop layer 140. In some embodiments, the etch stop layer 160 comprises a metal oxide, such as aluminum oxide (AlOx), hafnium oxide (HfOx), titanium oxide (TiOx), manganese oxide (MnOx), vanadium oxide (VOx), other suitable metal oxides, or combinations of the foregoing. Alternatively, the etch stop layer 160 may comprise silicon carbonitride (SiCN), silicon oxycarbide (SiOCN), silicon carbide (SiC), silicon nitride (SiN), or combinations thereof. In some embodiments, the etch stop layer 160 has

Or a smaller thickness. The etch stop layer 160 may be used for purposes such as adhesion, protection of metal from oxidation, protection of metal from damage, and ensuring general etch performance.

With continued reference to fig. 1E, another deposition process is performed to form an interlayer dielectric 170 over the etch stop layer 160. The deposition process may comprise, for example, chemical vapor deposition, physical vapor deposition, atomic layer deposition, or a combination of the foregoing. In some embodiments, the interlayer dielectric 170 may comprise a low dielectric constant (low-k) dielectric material, such as Siloxane (SiOCH), Tetraethoxysilane (TEOS), borophosphosilicate glass (BPSG), Fused Silica Glass (FSG), and the like. In some embodiments, interlayer dielectric 130 and interlayer dielectric 170 have the same material composition.

In some embodiments, a capping layer 172 is formed on the interlayer dielectric 170. The cap layer 172 may be deposited using physical vapor deposition, chemical vapor deposition, atomic layer deposition, and/or other suitable methods. Any suitable material may be used for the cap layer 172, such as silicon, silicon oxide (SiO)₂) Silicon nitride (SiN), silicon carbonitride (SiCN), silicon carbide (SiC), or combinations of the foregoing.

In some embodiments, a Hard Mask (HM) layer 174 is formed over the top surface of the semiconductor device 100. Hardmask layer 174 may comprise any suitable material. In one embodiment, the hard mask layer 174 comprises silicon, silicon carbonitride (SiCN), hafnium oxide (HfO)₂) Alumina (Al)₂O₃) Zirconium oxide (ZrO)₂) Titanium nitride (TiN), tungsten carbide (WC), other barrier materials, or combinations of the foregoing. The hard mask layer 174 may be formed by physical vapor deposition, chemical vapor deposition, atomic layer deposition, electroplating, or other suitable method.

Referring now to fig. 1F, one or more processes are performed to etch openings 180, the openings 180 extending vertically through the hard mask layer 174, the cap layer 172, and the interlayer dielectric 170 from top to bottom to reach the etch stop layer 160. In some embodiments, the hard mask layer 174 is first subjected to a photolithography process to define the location of the opening 180 (e.g., through photoresist deposition, exposure, and photoresist removal). An etch process may then be used to remove the hard mask layer 174. The etching process may include wet etching or dry etching. The same etch process or another etch process may be used to remove the cap layer 172 and the interlayer dielectric 170. In one embodiment, a dry etch is used to remove the cap layer 172 and the interlayer dielectric 170. As shown in fig. 1F, opening 180 is not perfectly aligned with metal element 120, which may occur when the overlap is complete. In fig. 1F, the opening 180 stops at the etch stop layer 160, and the etch stop layer 160 has a very low etch rate during the etching process. The etch stop layer 160 (sometimes referred to as a liner layer) helps to ensure that openings are properly created through the different material layers.

Referring now to fig. 1G, another etch process is used to remove a portion of the etch stop layer 160 located on the bottom of the opening 180. The etching process may include wet etching or dry etching, and etches the etch stop layer 160 faster than surrounding materials. As a result, the opening 180 extends to the upper surface of the conductive element 120. In some embodiments, the portion 142 of the intermediate etch stop layer located below the opening 180 is partially etched by an etching process. When the portion 142 of the (deposited) intermediate etch stop layer and the etch stop layer 160 are of the same material, the duration of the etch process is controlled such that the portion 142 of the intermediate etch stop layer is not completely etched. Otherwise, when the portion 142 of the (deposited) intermediate etch stop layer and the etch stop layer 160 are different materials, the etch process may have a relatively low etch rate on the portion 142 of the etch stop layer (but the upper corners of the portion 142 of the intermediate etch stop layer may still be cut, as shown in fig. 1G). In any case, the etching process ensures that the opening 180 does not reach the interlayer dielectric 130.

The openings 180 will later be filled with a conductive material to, for example, form conductive elements that are vias or metal lines. Ideally, the openings 180 should be aligned with the conductive elements 120 so that a good electrical connection can be established between the conductive elements 120 and the conductive elements to be formed in the openings 180. However, this is often the case in real world semiconductor manufacturing, and due to the limited ability to control overlay, the alignment between the opening 180 and the conductive element 120 is not perfect. This problem becomes more severe as the geometry of each semiconductor technology node shrinks. Thus, as shown in FIG. 1F, there is a misalignment between the opening 180 and the conductive element 120, which is manifested in a "right" movement of the opening 180 such that the opening 180 is now located over a portion of the interlayer dielectric. In conventional semiconductor devices, such misalignment may result in portions of the interlayer dielectric 130 underlying the openings 180 being undesirably etched due to over-etching. Then, when the conductive material fills the opening 180, the over-etched portion of the interlayer dielectric 130 will be filled with the conductive material. This may lead to problems such as time-varying dielectric breakdown or current leakage within the semiconductor device 100.

Embodiments of the present invention overcome the above-described problems by forming portion 142 of the etch stop layer, which portion 142 of the etch stop layer prevents potential etching of interlayer dielectric 130 (in creating opening 180). In more detail, as shown in fig. 1G, the etched opening 180 stops vertically at a portion 142 of the intermediate etch stop layer. As previously described, the material composition of etch stop layer 142 and etch stop layer 160 may be configured such that there is a significant etch selectivity between the two during the creation of opening 180. As such, the etch stop layer 160 may be substantially etched without significantly affecting the portion 142 of the intermediate etch stop layer, which allows the portion 142 of the intermediate etch stop layer to act as a protective structure. Because the portion 142 of the intermediate etch stop layer remains, the portion of the interlayer dielectric 130 underlying the portion 142 of the intermediate etch stop layer is also protected from being etched.

Referring now to fig. 1H, a deposition process is performed to form a conductive material 190 over the semiconductor device 100. In various embodiments, the conductive material comprises copper, tungsten, aluminum, other suitable metals, metal alloys, or combinations of the foregoing. The deposition process may comprise, for example, chemical vapor deposition, electroplating, physical vapor deposition, atomic layer deposition, or a combination of the foregoing. In some embodiments, the deposited conductive material 190 comprises a metal or metal alloy, such as copper, aluminum, tungsten, titanium, or a combination of the foregoing. In some embodiments, a barrier layer (e.g., titanium nitride, tantalum nitride, or combinations thereof) may be formed on the sidewalls of the opening 180, and thereafter a conductive material may be filled in the opening 180.

A portion of the deposited conductive material 190 fills the opening 180 to form a conductive via 192. In some embodiments, the conductive vias 192 serve as conductive elements that are electrically connected to the underlying conductive element 120. Likewise, the portion of the interlayer dielectric 130 underlying the portion 142 of the intermediate etch stop layer is not etched since the portion 142 of the intermediate etch stop layer acts as a protective layer during the etching of the via opening (via opening). Thus, even if the conductive elements 120 and the openings 180 are misaligned due to overlay displacement, the deposited conductive material 190 does not inadvertently reach the interlayer dielectric 130.

Referring now to fig. 1I, a planarization process, such as Chemical Mechanical Planarization (CMP), is performed to planarize an upper portion of conductive material 190, leaving conductive vias 192 surrounded by interlayer dielectric 170. The conductive via 192 and interlayer dielectric 170 can be considered to be part of a second interconnect layer 194 of the multilevel interconnect structure, which is located above the interconnect layer 110.

In some embodiments, interconnect layer 110 is M_n(e.g., metal-0) interconnect layer, and interconnect layer 194 is M_n+1(Metal-1) interconnect layer. In some embodiments, M_nThe pitch (distance between adjacent conductive elements) in the interconnect layer is between 16 and 40nm, and the Critical Dimension (CD) of the conductive elements is about 20nm or less. In some embodiments, M_n+1The critical dimension of the bottom surface of the conductive via in the interconnect layer is about 24nm or less, in which case the overlay displacement tolerance (tolerance) may be about 8nm or less. It is noted that overlay displacement tolerance is largely dependent on M_nThe pitch in the interconnect layer (e.g., if the pitch is 40nm, the overlay shift tolerance may be about 8nm, but if the pitch is reduced to 20nm, the overlay shift tolerance may be reduced to 4-6 nm). Embodiments of the present invention improve overlay shift tolerance by using a selectively removable etch stop layer 140.

Note that at this stage of fabrication, most, if not all, of portion 142 of the intermediate etch stop layer remains disposed between conductive via 192 and interlayer dielectric 130. In other words, the portion 142 of the intermediate etch stop layer separates the conductive via 192 from the interlayer dielectric 130 and prevents or minimizes leakage current flowing between the conductive via 192 and the conductive element 122. In some embodiments, depending on the thickness of the etch stop layer, the leakage current may be reduced by 1 to 2 orders of magnitude using the techniques disclosed herein. Portions 142 of the intermediate etch stop layer remain detectable in the final structure of semiconductor device 100. Indeed, the presence of the portion 142 of the intermediate etch stop layer comprising the metal silicon oxide described above is one of the unique physical characteristics of the present invention and may represent that steps of embodiments of the present invention have been performed.

Fig. 2 is a flow diagram of a method 200 for fabricating a semiconductor device, such as semiconductor device 100, according to various aspects of the present invention. The method 200 should be understood in conjunction with FIGS. 1A-1I. First, method 200 includes a step 210 for providing a structure including a conductive element (e.g., conductive element 120) and an interlayer dielectric (e.g., interlayer dielectric 130) that may completely or partially surround conductive element 120. More details are described above with reference to fig. 1A.

The method 200 includes step 220 of forming an etch stop layer, such as etch stop layer 140, comprising a metal oxide, over the conductive elements and the interlayer dielectric. More details are described above with reference to FIG. 1B. The method 200 includes a step 230 of baking the etch stop layer to switch its chemical composition. In one embodiment, after the chemical composition transition, a first portion of the etch stop layer in contact with the conductive element (e.g., portion 144 of the etch stop layer) does not contain any metal silicon oxide, while a second portion of the etch stop layer in contact with the interlayer dielectric (e.g., portion 142 of the etch stop layer) contains metal silicon oxide. Thus, the baking selectively converts the portion 142 of the etch stop layer into a metal silicon oxide. During baking, a metal silicon oxide is formed by a chemical reaction between silicon in the interlayer dielectric and a metal oxide in the second portion of the etch stop layer. More details are described above with reference to fig. 1C.

The method 200 includes a step 240 of selectively etching the etch stop layer to remove a first portion of the etch stop layer without removing a second portion of the etch stop layer. It is noted that, in practice, it may not be absolute to not remove a film or structure (i.e., even if there is a significant difference between etch selectivity, a small portion of the film or structure may still be removed). In an embodiment, the selective etching of the etch stop layer is configured such that the etch rate of the first portion of the etch stop layer is significantly greater (e.g., at least 30 times faster) than the etch rate of the second portion of the etch stop layer. More details are described above with reference to fig. 1D.

The method 200 includes forming 250 a second etch stop layer (e.g., etch stop layer 160) over the second portion of the first etch stop layer and over the first conductive element. At step 252, a second interlayer dielectric (e.g., interlayer dielectric 170) may be formed over the second etch stop layer. At step 254, a capping layer (e.g., capping layer 172) may be formed over the second interlayer dielectric. At step 256, a hard mask layer (e.g., hard mask layer 174) may be formed over the cap layer. More details regarding steps 250-256 are described above with reference to FIG. 1E.

The method 200 includes a step 258 of etching an opening (e.g., the opening 180) exposing an upper surface of the first conductive element. The openings may be fully aligned with the conductive elements (when there is no overlay displacement) or partially aligned with the conductive elements (when there is some overlay displacement). In any case, the second portion of the first etch stop layer protects a portion of the first interlayer dielectric located thereunder from being etched. Further details are described above with reference to fig. 1F and 1G.

The method 200 includes a step 260 of filling the opening with a conductive material (e.g., conductive material 190) to form a conductive via (e.g., conductive via 192) in contact with the conductive element. More details are described above with reference to fig. 1H. In some embodiments, step 260 may comprise a chemical mechanical planarization process as described with reference to fig. 1I.

It should be understood that the method 200 is merely exemplary and is not intended to limit embodiments of the present invention beyond what is explicitly recited. Additional steps may be provided before, during, and after method 200, and some of the steps described may be substituted, eliminated, or moved for additional embodiments of method 200. It should also be understood that the various aspects of the present invention may be applied to planar transistor as well as fin field effect transistor (FinFET) devices. For example, the method 200 may include forming source/drain regions and gate structures of a transistor before performing step 210, and forming additional interconnect layers, packaging, and testing after performing step 260. Other steps may be performed, but for simplicity, are not discussed in detail herein.

Based on the above discussion, it can be seen that embodiments of the present invention provide advantages over conventional devices and methods of making the same. However, it is understood that other embodiments may provide additional advantages, not all of which need be disclosed herein, and not all of which need be provided with a particular advantage.

One advantage of the present invention is that problems caused by overlay displacement are mitigated. For example, in an ideal case, the via holes should be aligned with the conductive elements. However, due to overlay displacement, the vias and conductive elements may be misaligned. Such misalignment would result in a portion of the interlayer dielectric underlying the via being undesirably etched if a selectively removable etch stop layer were not implemented. This may lead to reliability and/or performance issues such as breakdown voltage, time-varying dielectric breakdown, or leakage. The selectively removable etch stop layer serves as a spacer and insulator between the via and the interlayer dielectric. As a result, the etch stop layer protects the underlying portion of the interlayer dielectric from being undesirably etched during the via etch process, which in turn improves the reliability and/or performance of the semiconductor device.

One aspect of an embodiment of the present invention is directed to a method of manufacturing a semiconductor device, the method comprising: providing a structure comprising a conductive element and an interlayer dielectric, wherein the interlayer dielectric comprises silicon and surrounds the conductive element, and forming an etch stop layer over the conductive element and interlayer dielectric, the etch stop layer comprising a metal oxide. The etch stop layer includes a first portion in contact with the conductive element and a second portion in contact with the interlayer dielectric. The method also includes baking the etch stop layer to convert the metal oxide located in the second portion of the etch stop layer to a metal silicon oxide, and selectively etching the etch stop layer to remove the first portion of the etch stop layer but not the second portion of the etch stop layer.

In some embodiments, the etch stop layer is formed to have a thickness of between 10 and

is measured. In some embodiments, baking the etch stop layer does not convert the metal oxide located in the first portion of the etch stop layer to metal silicon oxide. During baking, a metal silicon oxide located in the second portion of the etch stop layer is formed by a chemical reaction between silicon in the interlayer dielectric and the metal oxide in the second portion of the etch stop layer. The etch stop layer is baked in an ambient gas comprising nitrogen and hydrogen. In some embodiments, the etch stop layer is baked at a temperature between 100 ℃ and 400 ℃. In some embodiments, the metal oxide in the second portion of the etch stop layer is selected from the group consisting of: silicon aluminum oxide (AlSiO)_x) Hafnium silicon oxide (HfSiO)_x) Titanium silicon oxide (TiSiO)_x) Manganese silicon oxide (MnSiO)_x) And vanadium silicon oxide (VSiO)_x). In some embodiments, the selective etching of the etch stop layer is performed using an etching solution, and wherein the etching solution comprises ammonium hydroxide, hydroxylamine, or both. In some embodiments, the etching solution further comprises water, a chelating agent, a metal corrosion inhibitor, and a solvent selected from the group consisting of: diethylene glycol monomethyl ether (diethylene glycol monomethyl ether), ethylene glycol (ethylene glycol), butyl diethylene glycol (butyl diethylene glycol), and dimethyl sulfoxide (dimethyl sulfoxide). In some embodiments, the selective etching of the etch stop layer is configured such that the etch rate of the first portion of the etch stop layer is significantly greater than the etch stop layerAn etch rate of the second portion of the layer.

In some embodiments, the interlayer dielectric is a first interlayer dielectric and the etch stop layer is a first etch stop layer. The method further comprises: forming a second etch stop layer over a second portion of the first etch stop layer and over the first conductive element; forming a second interlayer dielectric on the second etch stop layer; and etching openings in the second interlayer dielectric and in the second etch stop layer. The opening is at least partially aligned with the conductive element. The second portion of the first etch stop layer protects a portion of the first interlayer dielectric thereunder from being etched. The method also includes filling the opening with a conductive material to form a conductive via in contact with the conductive element. In some embodiments, the method further comprises, after forming the second interlayer dielectric and before etching openings in the second interlayer dielectric: forming a capping layer over the second interlayer dielectric; and forming a hard mask layer on the cover layer. The opening penetrates the hard mask layer, the capping layer, the second interlayer dielectric, and the second etch stop layer at least from top to bottom.

Another aspect of an embodiment of the present invention includes a semiconductor device, including: a substrate; first and second conductive elements disposed on the substrate; an interlayer dielectric disposed on the substrate and between the first and second conductive elements; and an etch stop layer comprising a metal silicon oxide extending over and in contact with the interlayer dielectric. The etch stop layer does not extend over the first conductive element or the second conductive element. The semiconductor device further comprises a conductive hole arranged on the first conductive element and electrically contacted with the first conductive element. The conductive via is separated from the second conductive element by at least a portion of the interlayer dielectric and the etch stop layer. In some embodiments, the semiconductor device further comprises a second etch stop layer disposed over the first etch stop layer and adjacent to the conductive via; and a second interlayer dielectric disposed on the second etchingA stop layer and surrounding the conductive via. In some embodiments, a conductive via partially covers an upper surface of the first conductive element, and a second etch stop layer also partially covers an upper surface of the first conductive element. In some embodiments, the metal oxide in the etch stop layer is selected from the group consisting of: silicon-aluminum oxide (AlSiOx), silicon-hafnium oxide (HfSiOx), silicon-titanium oxide (TiSiOx), silicon-manganese oxide (MnSiOx), and silicon-vanadium oxide (VSiOx). In some embodiments, the interlayer dielectric comprises silicon. In some embodiments, the etch stop layer has a thickness of between 10 and

is measured.

Another aspect of an embodiment of the present invention is directed to a method of manufacturing a semiconductor device, including: a first etch stop layer is formed including a first portion in contact with a conductive element and including a second portion in contact with a first interlayer dielectric surrounding the conductive element. The first portion of the first etch stop layer comprises a metal oxide and the second portion of the first etch stop layer comprises a metal silicon oxide. The method also includes etching the first etch stop layer to remove a first portion of the first etch stop layer, but not to remove a second portion of the first etch stop layer; forming a second etch stop layer over the second portion of the first etch stop layer and over the conductive element; forming a second interlayer dielectric on the second etch stop layer; etching an opening vertically through the second interlayer dielectric and second etch stop layer to expose an upper surface of the conductive element; and filling the opening with a conductive material to form a conductive hole in the opening. The conductive via is in contact with an upper surface of the conductive element but separated from the first interlayer dielectric by a second portion of the first etch stop layer.

In some embodiments, forming the first etch stop layer comprises: depositing the first etch stop layer, the first and second portions comprising metal oxide but the first and second portions not comprising any metal silicon oxide; and baking the first etch stop layer at a temperature between 100 ℃ and 400 ℃ such that a metal silicon oxide in the second portion of the first etch stop layer is formed by a chemical reaction between silicon in the first interlayer dielectric and a metal oxide in the second portion of the first etch stop layer. In some embodiments, the opening is partially aligned with the conductive element, and the second portion of the first etch stop layer protects the first interlayer dielectric thereunder from being etched during etching of the opening. In some embodiments, etching the first etch stop layer includes using a wet etch solution including a basic amine, and etching the opening includes using a dry etch process.

The components of several embodiments are summarized above so that those skilled in the art to which the invention pertains can more clearly understand the orientation of the embodiments of the invention. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions and alterations herein without departing from the spirit and scope of the present disclosure.