Self-adaptive ZVS circuit and control method thereof
阅读说明：本技术 一种自适应zvs电路及其控制方法 (Self-adaptive ZVS circuit and control method thereof ) 是由 卢鹏飞 于 2019-09-29 设计创作，主要内容包括：本发明公开了一种自适应ZVS电路及其控制方法,自适应ZVS电路包括电源V1,电源V2,电源V3,开关管Q1、开关管Q2、电感器L和双比较单元；开关管Q1的漏极和双比较单元的一个输入端连接到电源V1,开关管Q1的源极,开关管Q2的漏极和双比较单元的另一个输入端连接到电感器L1的一端,开关管Q2的源极连接到电源V2,电感器L1的另一端连接到电源V3。本发明利用广义ZVS的定义,通过双比较单元可以简单快速的判定开关管是否实现ZVS开通,并告诉控制电路下一个周期是否调节以及如何调节电路时序实现开关管的自适应ZVS开通,由于比较的速度远快于采样和保持电路的速度,所以在高频应用时优势更加明显。(The invention discloses a self-adaptive ZVS circuit and a control method thereof, wherein the self-adaptive ZVS circuit comprises a power supply V1, a power supply V2, a power supply V3, a switching tube Q1, a switching tube Q2, an inductor L and double comparison units; the drain of the switch tube Q1 and one input end of the double comparison unit are connected to a power supply V1, the source of the switch tube Q1, the drain of the switch tube Q2 and the other input end of the double comparison unit are connected to one end of an inductor L1, the source of the switch tube Q2 is connected to a power supply V2, and the other end of the inductor L1 is connected to the power supply V3. The invention utilizes the definition of generalized ZVS, can simply and rapidly judge whether the switching tube realizes ZVS switching-on through the double comparison units, and tell whether the control circuit regulates the next period and how to regulate the circuit time sequence to realize the self-adaptive ZVS switching-on of the switching tube.)
1. An adaptive ZVS circuit, comprising: the power supply comprises a power supply V1, a power supply V2, a power supply V3, a switching tube Q1, a switching tube Q2, an inductor L and a double comparison unit; the drain of the switch tube Q1 and one input end of the double comparison unit are connected to a power supply V1, the source of the switch tube Q1, the drain of the switch tube Q2 and the other input end of the double comparison unit are connected to one end of an inductor L1, the source of the switch tube Q2 is connected to a power supply V2, and the other end of the inductor L1 is connected to the power supply V3.
2. The adaptive ZVS circuit of claim 1, wherein: the voltage of the power supply V1 is higher than the voltage of the power supply V2, and the voltage of the power supply V3 is higher than the voltage of the power supply V2.
3. The adaptive ZVS circuit of claim 1, wherein: the inductor L is an inductor or a winding of a transformer.
4. The adaptive ZVS circuit of claim 1, wherein: the double comparison unit is two comparators.
5. The adaptive ZVS circuit of claim 4 wherein: two input ends of the comparator are respectively connected with a power supply V1 and one end of an inductor L1.
6. The adaptive ZVS circuit of claim 4 wherein: at least one of the two input ends of the comparator is connected to one end of a power supply V1 and one end of an inductor L1 after being added with a bias voltage.
7. The adaptive ZVS circuit of claim 4 wherein: one end of the power supply V1 and one end of the inductor L1 are respectively connected to two input ends of the comparator after passing through the voltage division circuit.
8. The adaptive ZVS circuit of claim 7, wherein: the voltage division circuit is formed by connecting a plurality of resistors in series with a voltage division circuit or connecting a plurality of resistors in series with a voltage source, a constant current source or a voltage stabilizing device in series with the voltage division circuit.
9. A method of controlling an adaptive ZVS circuit according to any of claims 1-8, characterized by: in the time period from the turn-off time of the switching tube Q2 to the turn-on time of the switching tube Q1, according to the voltage of the power supply V1, the voltage of one end of the inductor L1 and the double comparison units obtain two paths of high and low level outputs, and then relative to the turn-off time of the switching tube Q2 in the current period, the two paths of high and low level outputs of the double comparison units are used for adjusting the switching tube Q2 to be kept in the next period, and turn-off is carried out in advance or in a delayed mode.
10. An adaptive ZVS circuit, comprising: the power supply comprises a power supply V1, a power supply V2, a power supply V3, a switching tube Q1, a switching tube Q2, an inductor L and a double comparison unit; the drain of the switch tube Q1 is connected to the power supply V1, the source of the switch tube Q1, the drain of the switch tube Q2 and one input end of the double comparison unit are connected to one end of the inductor L1, the source of the switch tube Q2 and the other input end of the double comparison unit are connected to the power supply V2, and the other end of the inductor L1 is connected to the power supply V3.
11. The adaptive ZVS circuit of claim 10, wherein: the voltage of the power supply V1 is higher than the voltage of the power supply V2, and the voltage of the power supply V3 is higher than the voltage of the power supply V2.
12. The adaptive ZVS circuit of claim 10, wherein: the inductor L is an inductor or a winding of a transformer.
13. The adaptive ZVS circuit of claim 10, wherein: the double comparison unit is two comparators.
14. The adaptive ZVS circuit of claim 13, wherein: the two inputs of the comparator are connected to a power supply V2 and one end of an inductor L1, respectively.
15. The adaptive ZVS circuit of claim 13, wherein: at least one of the two input ends of the comparator is connected to one end of a power supply V2 and one end of an inductor L1 after being added with a bias voltage.
16. A method of controlling an adaptive ZVS circuit according to any of claims 11-15, characterized by: in the time period from the turn-off time of the switching tube Q1 to the turn-on time of the switching tube Q2, according to the voltage of the power supply V2, the voltage of one end of the inductor L1 and the double comparison units obtain two paths of high and low level outputs, and then relative to the turn-off time of the switching tube Q1 in the current period, the two paths of high and low level outputs of the double comparison units are used for adjusting the switching tube Q1 to be kept in the next period, and turn-off is carried out in advance or in a delayed mode.
Technical Field
The present invention relates to switching power supplies, and more particularly, to an adaptive ZVS switching converter circuit and a control method thereof.
Background
Fig. 1 is a Buck circuit with a synchronous rectification function, fig. 2 is a timing diagram corresponding to fig. 1, and a condition for implementing ZVS turning-on of the MOS transistor Q1 is to turn off the MOS transistor Q2 when a current IL of the inductor L is a certain negative current at
Fig. 3, 4 and 5 are abstracts OF U.S. patent application No. 13/027,830 entitled ADAPTIVE CONTROL OF SWITCHING POWER IN POWER CONVERTERS, which is based on the inventive concept OF detecting when the polarity OF the current IL IN the inductor L OF fig. 3 is reversed by the current
Disclosure of Invention
In view of the technical defects of the existing self-adaptive ZVS circuit, the technical problem to be solved by the invention is to provide the self-adaptive ZVS circuit and the control method thereof, the self-adaptive ZVS switching-on of the switching tube is realized through a double comparison mode, and the self-adaptive ZVS circuit has the advantages of simple circuit, easiness in realization and low cost, reduces the loss to the maximum extent and improves the power supply efficiency.
In order to achieve the purpose, the invention adopts the following technical scheme:
an adaptive ZVS circuit, comprising: the power supply comprises a power supply V1, a power supply V2, a power supply V3, a switching tube Q1, a switching tube Q2, an inductor L and a double comparison unit; the drain of the switch tube Q1 and one input end of the double comparison unit are connected to a power supply V1, the source of the switch tube Q1, the drain of the switch tube Q2 and the other input end of the double comparison unit are connected to one end of an inductor L1, the source of the switch tube Q2 is connected to a power supply V2, and the other end of the inductor L1 is connected to the power supply V3.
Preferably, the voltage of the power supply V1 is higher than the voltage of the power supply V2, and the voltage of the power supply V3 is higher than the voltage of the power supply V2.
Preferably, the inductor L is an inductor or a winding of a transformer.
Preferably, the dual comparison unit is two comparators.
As a first embodiment of the comparator, two input terminals of the comparator are respectively connected to the power supply V1 and one end of the inductor L1.
As a second embodiment of the above comparator, at least one of the two input terminals of the comparator is connected to one end of the power supply V1 and one end of the inductor L1 after being added with a bias voltage.
As a third embodiment of the comparator, one end of the power source V1 and one end of the inductor L1 are respectively connected to two input ends of the comparator after passing through the voltage dividing circuit.
As an embodiment of the voltage dividing circuit, the voltage dividing circuit is a series-connected voltage dividing circuit of a plurality of resistors or a series-connected voltage dividing circuit of a plurality of resistors connected in series with a voltage source, a constant current source or a voltage stabilizing device.
The invention also provides a control method of the self-adaptive ZVS circuit, which is characterized in that: in the time period from the turn-off time of the switching tube Q2 to the turn-on time of the switching tube Q1, according to the voltage of the power supply V1, the voltage of one end of the inductor L1 and the double comparison units obtain two paths of high and low level outputs, and then relative to the turn-off time of the switching tube Q2 in the current period, the two paths of high and low level outputs of the double comparison units are used for adjusting the switching tube Q2 to be kept in the next period, and turn-off is carried out in advance or in a delayed mode.
The invention also provides another switch converter with the same inventive concept, and the technical scheme is as follows: an adaptive ZVS circuit comprises a power supply V1, a power supply V2, a power supply V3, a switching tube Q1, a switching tube Q2, an inductor L and a double comparison unit; the drain of the switch tube Q1 is connected to the power supply V1, the source of the switch tube Q1, the drain of the switch tube Q2 and one input end of the double comparison unit are connected to one end of the inductor L1, the source of the switch tube Q2 and the other input end of the double comparison unit are connected to the power supply V2, and the other end of the inductor L1 is connected to the power supply V3.
Preferably, the voltage of the power supply V1 is higher than the voltage of the power supply V2, and the voltage of the power supply V3 is higher than the voltage of the power supply V2.
Preferably, the inductor L is an inductor or a winding of a transformer.
Preferably, the dual comparison unit is two comparators.
As a first embodiment of the above comparator, two input terminals of the comparator are respectively connected to the power supply V2 and one end of the inductor L1.
As a second embodiment of the above comparator, at least one of the two input terminals of the comparator is connected to one end of the power supply V2 and one end of the inductor L1 after being added with a bias voltage.
The invention also provides a control method of the self-adaptive ZVS circuit, which is characterized in that: in the time period from the turn-off time of the switching tube Q1 to the turn-on time of the switching tube Q2, according to the voltage of the power supply V2, the voltage of one end of the inductor L1 and the double comparison units obtain two paths of high and low level outputs, and then relative to the turn-off time of the switching tube Q1 in the current period, the two paths of high and low level outputs of the double comparison units are used for adjusting the switching tube Q1 to be kept in the next period, and turn-off is carried out in advance or in a delayed mode.
Description of the meaning of the terms:
drain electrode of the switching tube: for the MOS tube, a drain electrode is referred, for the triode, a collector electrode is referred, for the IGBT, a drain electrode is referred, and other switching tubes can correspond to each other according to the knowledge of a person skilled in the art and are not listed one by one;
source electrode of the switching tube: for the MOS transistor, the source electrode, the emitter electrode, and the source electrode, the other switching transistors may correspond to each other according to the knowledge of those skilled in the art, and are not listed.
Compared with the prior art, the invention has the following beneficial effects:
1) the self-adaptive ZVS (zero voltage switching) switching-on of the switching tube is realized by adopting a double comparison mode, the circuit is simple and easy to realize, the cost is low, and the circuit is particularly suitable for occasions with high switching frequency to realize the self-adaptive ZVS switching-on of the switching tube;
2) the highest voltage at one end of an inductor L1 or the lowest voltage at one end of an inductor L1 in the time period from the turn-off time of a switch tube Q2 to the turn-on time of a switch tube Q1 or the turn-off time of a switch tube Q1 to the turn-on time of a switch tube Q2 is controlled within a proper range in a double comparison mode, and the highest or lowest voltage at one end of an inductor L1 is positively correlated with the current of an inductor L for realizing the turn-on of a switch tube ZVS, so that the current is stably regulated to a proper value, the loss is reduced to the maximum extent, and the power supply efficiency is improved.
Drawings
FIG. 1 is a schematic diagram of a Buck circuit with synchronous rectification function;
FIG. 2 is a timing diagram of the operation of FIG. 1;
FIG. 3 is a schematic diagram of a Buck circuit of
FIG. 4 is a block diagram of the adaptive ZVS control of application No. 13/027,830;
FIG. 5 is a timing diagram illustrating the operation of
FIG. 6 is a functional block diagram of the present invention;
FIG. 7 is another functional block diagram of the present invention;
FIG. 8 is a schematic diagram of an adaptive ZVS circuit using dual compare units according to the first embodiment of the present invention;
FIG. 9 is a timing diagram illustrating the operation of the first embodiment of the present invention;
FIG. 10 is a truth table of the first embodiment of the present invention;
FIG. 11 is a schematic diagram of an adaptive ZVS circuit using dual compare units according to a second embodiment of the present invention;
FIG. 12 is a schematic diagram of an adaptive ZVS circuit using dual compare units according to a third embodiment of the present invention;
fig. 13 is a truth table of the third embodiment of the present invention.
Detailed Description
FIG. 6 is a schematic block diagram of the present invention, which includes a power supply V1, a power supply V2, a power supply V3, a switch Q1, a switch Q2, an inductor L and a dual comparison unit; the drain of the switching tube Q1 and one input end of the double comparison unit are connected to a power supply V1, the source of the switching tube Q1, the drain of the switching tube Q2 and the other input end of the double comparison unit are connected to one end of an inductor L1, the source of the switching tube Q2 is connected to a power supply V2, and the other end of the inductor L1 is connected to the power supply V3; the voltage of the power supply V1 is higher than the voltage of the power supply V2, and the voltage of the power supply V3 is higher than the voltage of the power supply V2.
Fig. 7 is another functional block diagram of the present invention. The power supply comprises a power supply V1, a power supply V2, a power supply V3, a switching tube Q1, a switching tube Q2, an inductor L and a double comparison unit; the drain of the switching tube Q1 is connected to the power supply V1, the source of the switching tube Q1, the drain of the switching tube Q2 and one input end of the double comparison unit are connected to one end of the inductor L1, the source of the switching tube Q2 and the other input end of the double comparison unit are connected to the power supply V2, and the other end of the inductor L1 is connected to the power supply V3; the voltage of the power supply V1 is higher than the voltage of the power supply V2, and the voltage of the power supply V3 is higher than the voltage of the power supply V2.
Coss1 and Coss2 in fig. 6 and fig. 7 are output capacitances of the switching tube Q1 and the switching tube Q2, respectively, and D1 and D2 are body diodes of the switching tube Q1 and the switching tube Q2, respectively.
According to the inventive concept, effects of the related embodiments will be described below with reference to the accompanying drawings. It should be noted that: it is common practice for those skilled in the art to replace the switching tube Q1 and the switching tube Q2 with MOS transistors, triodes, IGBTs, or other types of switching tubes.
First embodiment
Fig. 8 is a schematic diagram of an adaptive ZVS circuit according to this embodiment, which employs a dual comparison unit including a comparator COMP1, a comparator COMP2, and a voltage source U; the reverse terminal of the comparator COMP1 and the positive terminal of the voltage source U are connected to the power source V1, the negative terminal of the voltage source U is connected to the reverse terminal of the comparator COMP2, the positive terminal of the comparator COMP1 and the positive terminal of the comparator COMP2 are connected to the node SW (i.e., one terminal of the inductor L1), the output terminals of the comparator COMP1 and the comparator COMP2 are connected to the anodes of the diodes D3 and D4, respectively, and the cathodes of the diodes D3 and D4 are connected to the output C1 and the output C2, respectively.
The working time of the double comparison unit is from the moment that the switch tube Q2 is turned off to the moment that the switch tube Q1 is turned on, and the working principle is as follows:
for comparator COMP 1: the voltage of the power supply V1 and the voltage of the node SW (i.e., at the end of the inductor L1) are respectively used as reverse and forward inputs of the comparator COMP1 to be compared, and if the voltage of the node SW (i.e., at the end of the inductor L1) is greater than the voltage of V1, the output C1 is at a high level, which indicates that the negative current is too large, and the switching tube Q2 needs to be turned off in advance in the next cycle relative to the current cycle.
For comparator COMP 2: after the bias voltage U is added to the voltage of the power supply V1, the voltage of the node SW (i.e., one end of the inductor L1) is respectively used as the reverse input and the forward input of the comparator COMP2 to be compared, if the voltage of the node SW (i.e., one end of the inductor L1) is not greater than the voltage V1-U, the output C2 is at a low level, which indicates that the negative current is too small, and the switching tube Q2 needs to be turned off after the next cycle is delayed relative to the current cycle.
If the voltage at node SW (i.e., at the end of inductor L1) is not greater than the voltage of power supply V1, output C1 is low, while the voltage at node SW (i.e., at the end of inductor L1) is greater than the voltage of V1-U, output C2 is high, and no early or late turn-off operation of switch Q2 is required relative to the current cycle.
In a narrow sense, ZVS (zero voltage switching) on of the switching tube means that the switching tube is switched on when the voltage difference between the drain electrode and the source electrode is 0V; in a broad sense, ZVS switching on of a switching tube means that the switching tube is switched on when the voltage difference between the drain and the source of the switching tube is lower than a certain voltage. According to the actual debugging result of the circuit, the difference between narrow-sense ZVS turn-on and generalized ZVS turn-on is small, the generalized ZVS is utilized, as long as the voltage of a node SW (namely one end of an inductor L1) can reach between V1 voltage and V1-U voltage in a dead zone time period from the turn-off time of a switching tube Q2 to the turn-on time of a switching tube Q1, the switching tube Q1 can realize ZVS turn-on, only two comparison units are needed to judge whether the switching tube Q1 realizes ZVS turn-on, and then the turn-off time of the switching tube Q2 is adjusted in the next period according to the judged result. The invention is especially suitable for occasions with higher switching frequency because of the extremely fast comparison speed, and compared with the invention patent with the application number of 13/027,830, the invention has the advantages of simple and easily realized circuit, low cost, easy high-frequency application, reduced loss to the maximum extent and improved power supply efficiency because the core device is the comparator.
Fig. 9 shows the operation sequence of the first embodiment, assuming that the voltage of the power supply V1 is greater than the voltage of the power supply V3, as follows:
stage t 0-t 1: at time t0, switching tube Q1 is turned on, the voltage across inductor L1 is V1-V3, inductor L1 is excited, current IL of inductor L rises, and switching tube Q1 is turned off at
stage t 1-t 2: after the switching tube Q1 is turned off, the current IL of the inductor L charges the output capacitor Coss1 of the switching tube Q1 and discharges the output capacitor Coss2 of the switching tube Q2. At time t2, the voltage of the circuit node SW (i.e. one end of the inductor L) is reduced from V1 to V2, and the switching tube Q2 realizes ZVS switching-on;
stage t 2-t 4: the voltage at two ends of the inductor L is V3-V2, the inductor L1 is demagnetized, the current IL is reduced to 0A at the time of t3, and the switching tube Q2 is turned off at the time of t 4;
stage T4-T0 + T: the current IL of the inductor L charges the output capacitor Coss2 of the switching tube Q2, discharges the output capacitor Coss1 of the switching tube Q1, and turns on the switching tube Q1 at time T0+ T. When the highest voltage of the circuit node SW (i.e., one end of the inductor L1) is between V1-U and V1 from time T4 to time T0+ T, according to the definition of the generalized ZVS: the switching tube Q1 realizes ZVS opening;
the cycle is ended and the next duty cycle is started and the above stages are repeated.
If the switching tube Q2 is at t'4Time of day off, waveform shown by long dashed line in FIG. 9, t4At time point SW (i.e., at one end of inductor L1) at time' T0+ TThe voltage is always lower than V1-U, and the next period needs to be prolonged by t3 to t'4The time length is prolonged according to the set stepping time length, and each period is subjected to accumulation adjustment until t'4The highest voltage at node SW (i.e., at the end of inductor L1) is between V1-U and V1 at time T0+ T.
If the switch tube Q2 is at t ″)4At the moment of time, the waveform is shown by the short dashed line, t ″, in FIG. 94The highest voltage of the circuit node SW (i.e. one end of the inductor L1) is higher than V1 until T0+ T, and is clamped to V1+ Vf by the body diode D1 of the switch tube Q1, and Vf is the conduction voltage drop of the body diode D1, so that the next period is reduced by T3 to T ″4The time length of the time length is reduced according to the set stepping time length, and the accumulated adjustment is carried out in each period until t ″4The highest voltage at node SW (i.e., at the end of inductor L1) is between V1-U and V1 at time T0+ T.
The highest voltage of the circuit node SW (namely, at one end of the inductor L1) from time T4 to time T0+ T is determined by the comparator COMP1 and the comparator COMP2, the highest voltage is recorded as SWM4, the obtained truth table is shown in fig. 10, whether the time length from T3 to T4 is prolonged, reduced or unchanged in the next period is determined according to fig. 10, when C1 or C2 is at a high level, the diode connected to the outputs of the comparator COMP1 and the comparator COMP2 is used for keeping the high level of C1 or C2, and the diodes reset the C1 and C2 once in each period.
Since the circuit operates periodically, T in T0+ T means the time length of one cycle.
Second embodiment
Fig. 11 is a schematic circuit diagram of a second embodiment of the present invention. On the basis of the first embodiment, the problem that the voltage at one end of the power supply V1 and the inductor L1 exceeds the maximum withstand voltage of the input end of the comparison unit is mainly solved by the voltage dividing circuit, namely, the input ends of the comparator COMP1 and the comparator COMP2 are indirectly connected through the voltage dividing circuit instead of being directly connected to the power supply V1 and the node SW (namely, one end of the inductor L1), and the voltage source U is replaced by the voltage stabilizing device Z1.
The second embodiment is similar in operation to the first embodiment except that the power supply V1 and one terminal of the inductor L1 are scaled down and the voltage U of the voltage source U in the first embodiment is equivalently replaced by the nominal regulated value Z of the regulator device Z1. Other contents are not described in detail herein.
Third embodiment
Fig. 12 is a circuit schematic of a third embodiment of the present invention. The included devices are substantially the same as the first embodiment, the main difference being the connection relationship: the reverse terminal of the comparator COMP1 and the forward terminal of the voltage source U are connected to the node SW (i.e., the terminal of the inductor L1), and the forward terminal of the comparator COMP1 and the forward terminal of the comparator COMP2 are connected to the power source V2.
The third embodiment still uses the principle of generalized ZVS, the whole operation process and principle are similar to the first embodiment, and the difference is that the lowest voltage of the circuit node SW (i.e. one end of the inductor L1) at time t1 to t2 in fig. 9 is determined by the comparator COMP1 and the comparator COMP2, the lowest voltage is denoted as SWm1, the obtained truth table is fig. 13, the truth table determines whether the time duration from t0 to t1 is prolonged, reduced or unchanged in the next period, when C1 or C2 is high level, the diode connected to the outputs of the comparator COMP1 and the comparator COMP2 is used to maintain the high level of C1 or C2, and the C1 and C2 are reset once per period. Other contents are not described in detail herein.
The above embodiments should not be construed as limiting the present invention, and the scope of the present invention should be determined by the scope of the appended claims. It will be apparent to those skilled in the art that many equivalent substitutions, modifications and alterations can be made without departing from the spirit and scope of the invention, such as fine tuning of the circuit by simple series-parallel connection of devices, etc., depending on the application, and such modifications and alterations should also be considered as the scope of the invention.
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