阅读说明：本技术 低成本lf驱动器电流感测拓扑 (Low cost LF driver current sensing topology ) 是由 赫尔曼纳斯·约翰内斯·埃芬 迪米塔尔·米尔科夫·多切夫 马尔腾·雅各布斯·斯万内堡 于 2019-07-03 设计创作，主要内容包括：描述了一种开关放大器电路,开关放大器电路被连接以驱动基于阻抗的输出负载,开关放大器电路包括高侧开关和低侧开关,高侧开关和低侧开关被配置和连接成响应于栅极控制信号而将第一电源电压线和第二电源电压线连接到第一输出节点和第二输出节点,并且开关放大器电路还包括输出电流感测电路,输出电流感测电路用于使用电流感测电阻器来测量通过输出负载的电流,电流感测电阻器连接于第二电源电压线与低侧栅极-源极开关晶体管中的一个或多个分离式栅极-源极开关晶体管的源极之间,其中连接于电流感测电阻器两端的电压感测电路被配置成对电流感测电阻器两端的电压进行采样以测量电流感测电阻器处的感测电流。(A switching amplifier circuit is described, the switching amplifier circuit connected to drive an impedance-based output load, the switching amplifier circuit including a high-side switch and a low-side switch configured and connected to connect a first supply voltage line and a second supply voltage line to a first output node and a second output node in response to a gate control signal, and the switching amplifier circuit further comprises an output current sensing circuit for measuring current through the output load using a current sense resistor connected between the second supply voltage line and the source of one or more split gate-source switching transistors in the low side gate-source switching transistor, wherein the voltage sensing circuit connected across the current sensing resistor is configured to sample a voltage across the current sensing resistor to measure a sensed current at the current sensing resistor.)

1. A switching amplifier circuit, comprising:

an output drive circuit comprising a high-side switching transistor and a low-side split gate-source switching transistor connected in series between a first supply voltage line and a second supply voltage line;

a switch driver circuit configured to drive the switch transistor with first and second respective control signals;

an output connection between the switching transistors for driving an output load; and

an output current sense circuit to measure a current through the output load using a current sense resistor connected between the second supply voltage line and sources of one or more of the low side split gate-source switching transistors.

2. The switching amplifier circuit according to claim 1, wherein the output driver circuit comprises:

a first high-side split gate-source switching transistor and a second high-side split gate-source switching transistor configured and arranged to connect the first supply voltage line to a first output connection and a second output connection, respectively, in response to a first gate control signal and a second gate control signal; and

a first low side split gate-source switching transistor and a second low side split gate-source switching transistor configured and arranged to connect the second supply voltage line to the first output connection and the second output connection, respectively, in response to the first gate control signal and the second gate control signal.

3. The switching amplifier circuit according to claim 2, wherein the output driver circuit comprises a class D amplifier connected to drive the output load.

4. The switching amplifier circuit of claim 3, wherein the output load comprises an impedance-based antenna load comprising an inductor coupled between the first output connection and the second output connection, the impedance-based antenna load to wirelessly convey the modulated signal from the switching amplifier circuit for reception and demodulation by another circuit.

5. The switching amplifier circuit according to claim 4, wherein the impedance-based antenna load is configured and arranged to wirelessly convey the modulated signal from the switching amplifier circuit at a carrier frequency of at least ten kilohertz for reception and demodulation by a key fob circuit.

6. The switching amplifier circuit of claim 1, wherein the high-side switching transistor comprises a split gate-source switching transistor comprising a first power transistor and a second current sense transistor connected in parallel between the first supply voltage line and the output connection and driven by a common gate control signal, wherein the first power transistor is larger than the second current sense transistor, and wherein the first power transistor and the second power transistor sharing a substrate region are isolated from other components by a substrate isolation structure.

7. The switching amplifier circuit of claim 1, wherein the low side split gate-source switching transistor comprises a first power transistor and a second smaller current sense transistor, each transistor having a drain node directly connected to the output connection and a gate node driven by a common gate control signal, wherein the source node of the first power transistor is connected to the second power supply line, and wherein the source node of the current sense transistor is connected to the current sense resistor.

8. The switching amplifier circuit of claim 1, further comprising a voltage sense circuit connected across the current sense resistor, wherein the voltage sense circuit is configured to sample a voltage across the current sense resistor to measure a sensed current at the current sense resistor.

9. A circuit, characterized in that the circuit comprises:

a switching amplifier comprising a high-side switching transistor and a low-side split gate-source switching transistor connected in series between a first supply voltage line and a second supply voltage line;

an output connection between the high-side switching transistor and the low-side switching transistor for driving an output load;

a switch driver circuit configured to drive the high-side switching transistor and the low-side split gate-source switching transistor with first and second respective control signals; and

an output current sensing circuit for measuring current through the output load using a current sense resistor connected between the second supply voltage line and the sources of one or more of the low side split gate-source switching transistors,

wherein the current sense resistor is an integrated circuit resistor formed in a common semiconductor substrate for the circuit.

10. A wireless communication system, the wireless communication system comprising:

a key fob circuit configured and arranged to wirelessly receive and respond to a modulated signal; and

a class D switching amplifier circuit connected to drive an impedance-based load connected between a first output node and a second output node, the class D switching amplifier circuit comprising:

a first high-side electronic switch and a second high-side electronic switch configured and arranged to connect a first reference voltage to the first output node and the second output node, respectively, in response to a first gate control signal and a second gate control signal; and

a first low side split gate-source electronic switch and a second low side split gate-source electronic switch configured and arranged to connect a second reference voltage to the first output node and the second output node, respectively, in response to the first gate control signal and the second gate control signal; and

an output current sensing circuit for measuring current through the impedance-based load using a current sense resistor connected between the second reference voltage and the sources of one or more of the low side split gate-source switching transistors,

wherein the current sense resistor comprises a polysilicon resistor having a resistance value of about 200Ohm or less.

Technical Field

The present invention relates generally to the field of sensing in switching power amplifiers. In one aspect, the present invention relates to methods, devices, architectures and systems for measuring output current in an integrated circuit switching amplifier.

Background

Switching amplifiers are increasingly used to detect and reproduce audio or Low Frequency (LF) signals in various electronic circuit applications, such as power electronic circuits in the automotive industry, as well as many other portable applications. Most of these electronic circuit applications are embodied as integrated circuits. A specific example of an LF amplifier in an integrated circuit is a basic four-switch class D driver (or amplifier) design with output amplitude control clamping circuitry in the form of regulators and diodes. In such driver designs, the four switches are typically implemented as Field Effect Transistors (FETs) driven in a common mode, with opposite phase signals driving a pair of high-side FETs and a pair of low-side FETs. For some specific LF transmission systems, such as automotive keyless entry systems, it is desirable to control the load current over a wide range. However, due to the switching nature of the output signal and the cost and complexity of existing current sensing methods, such as using an external sense resistor in series with the LF antenna, or using current copy circuitry for generating a small copy of the actual LF driver output current, it is not easy to accurately measure the current from such an amplifier. Other solutions include digitizing the output current (i.e., converting the output current into an electrical signal), which typically requires a 12-bit analog-to-digital converter. As can be seen from the foregoing, existing current sensing solutions are extremely difficult in practice due to challenges presented by design complexity, power control requirements, and increased cost and size.

Disclosure of Invention

According to a first aspect of the present invention, there is provided a switching amplifier circuit comprising:

an output drive circuit comprising a high-side switching transistor and a low-side split gate-source switching transistor connected in series between a first supply voltage line and a second supply voltage line;

a switch driver circuit configured to drive the switch transistor with first and second respective control signals;

an output connection between the switching transistors for driving an output load; and

an output current sense circuit to measure a current through the output load using a current sense resistor connected between the second supply voltage line and sources of one or more of the low side split gate-source switching transistors.

In one or more embodiments, the output driving circuit includes:

a first high-side split gate-source switching transistor and a second high-side split gate-source switching transistor configured and arranged to connect the first supply voltage line to a first output connection and a second output connection, respectively, in response to a first gate control signal and a second gate control signal; and

a first low side split gate-source switching transistor and a second low side split gate-source switching transistor configured and arranged to connect the second supply voltage line to the first output connection and the second output connection, respectively, in response to the first gate control signal and the second gate control signal.

In one or more embodiments, the output driver circuit includes a class D amplifier connected to drive the output load.

In one or more embodiments, the output load comprises an impedance-based antenna load comprising an inductor coupled between the first output connection and the second output connection, the impedance-based antenna load to wirelessly convey the modulated signal from the switching amplifier circuit for reception and demodulation by another circuit.

In one or more embodiments, the impedance-based antenna load is configured and arranged to wirelessly convey the modulated signal from the switching amplifier circuit at a carrier frequency of at least ten kilohertz for reception and demodulation by the key fob circuit.

In one or more embodiments, the high-side switching transistor comprises a split gate-source switching transistor comprising a first power transistor and a second current sense transistor connected in parallel between the first supply voltage line and the output connection and driven by a common gate control signal, wherein the first power transistor is larger than the second current sense transistor, and wherein the first power transistor and the second power transistor sharing a substrate region are isolated from other components by a substrate isolation structure.

In one or more embodiments, the low side split gate-source switching transistor includes a first power transistor and a second smaller current sense transistor, each transistor having a drain node directly connected to the output connection and a gate node driven by a common gate control signal, wherein the source node of the first power transistor is connected to the second power supply line, and wherein the source node of the current sense transistor is connected to the current sense resistor.

In one or more embodiments, the low side split gate-source switching transistor includes a third current sensing transistor having a drain node directly connected to the output connection and a source node connected to the current sensing resistor, wherein the gate node of the third current sensing transistor is connected to the common gate control signal in a first connection state through a connection switch and to the source node of the third current sensing transistor in a second connection state through the connection switch such that less current is provided to the current sensing resistor in the second state than in the first state.

In one or more embodiments, the switching amplifier circuit further comprises a voltage sensing circuit connected across the current sense resistor, wherein the voltage sensing circuit is configured to sample a voltage across the current sense resistor to measure a sensed current at the current sense resistor.

In one or more embodiments, the high-side switching transistor comprises a split gate-source switching transistor.

According to a second aspect of the invention, there is provided a circuit comprising:

a switching amplifier comprising a high-side switching transistor and a low-side split gate-source switching transistor connected in series between a first supply voltage line and a second supply voltage line;

an output connection between the high-side switching transistor and the low-side switching transistor for driving an output load;

a switch driver circuit configured to drive the high-side switching transistor and the low-side split gate-source switching transistor with first and second respective control signals; and

an output current sensing circuit for measuring current through the output load using a current sense resistor connected between the second supply voltage line and the sources of one or more of the low side split gate-source switching transistors,

wherein the current sense resistor is an integrated circuit resistor formed in a common semiconductor substrate for the circuit.

In one or more embodiments, the switching amplifier includes:

a first high-side split gate-source switching transistor and a second high-side split gate-source switching transistor configured and arranged to connect the first supply voltage line to a first output connection node and a second output connection node of the output drive circuit, respectively, in response to a first gate control signal and a second gate control signal from the switch driver circuit; and

a first low side split gate-source switching transistor and a second low side split gate-source switching transistor configured and arranged to connect the second supply voltage line to the first output connection node and the second output connection node, respectively, in response to the first gate control signal and the second gate control signal from the switch driver circuit.

In one or more embodiments, the first and second high-side split gate-source switching transistors and the first and second low-side split gate-source switching transistors are part of a class D amplifier connected to drive the output load, the output load comprising an impedance-based antenna load including an inductor coupled between the first and second output connections, the impedance-based antenna load for wirelessly conveying modulated signals from the switching amplifier circuit for reception and demodulation by another circuit.

In one or more embodiments, the current sense resistor comprises a polysilicon resistor.

In one or more embodiments, the current sense resistor has a resistance between 0.2Ohm and 200 Ohm.

In one or more embodiments, the low side split gate-source switching transistor includes a first power transistor and a second smaller current sensing transistor, each transistor having a drain node directly connected to the output connection and a gate node driven by the first control signal, wherein a source node of the first power transistor is connected to the second supply voltage line, and wherein a source node of the current sensing transistor is connected to the current sensing resistor.

In one or more embodiments, the low side split gate-source switching transistor includes a third current sensing transistor having a drain node directly connected to the output connection and a source node connected to the current sensing resistor, wherein the gate node of the third current sensing transistor is connected to the first control signal in a first connection state through a connection switch and to the source node of the third current sensing transistor in a second connection state through the connection switch such that less current is provided to the current sensing resistor in the second state than in the first state.

In one or more embodiments, the circuit further comprises a voltage sensing circuit connected across the current sense resistor, wherein the voltage sensing circuit is configured to sample a voltage across the current sense resistor to measure a sensed current at the current sense resistor.

According to a third aspect of the present invention, there is provided a wireless communication system comprising:

a key fob circuit configured and arranged to wirelessly receive and respond to a modulated signal; and

a class D switching amplifier circuit connected to drive an impedance-based load connected between a first output node and a second output node, the class D switching amplifier circuit comprising:

a first high-side electronic switch and a second high-side electronic switch configured and arranged to connect a first reference voltage to the first output node and the second output node, respectively, in response to a first gate control signal and a second gate control signal; and

a first low side split gate-source electronic switch and a second low side split gate-source electronic switch configured and arranged to connect a second reference voltage to the first output node and the second output node, respectively, in response to the first gate control signal and the second gate control signal; and

an output current sensing circuit for measuring current through the impedance-based load using a current sense resistor connected between the second reference voltage and the sources of one or more of the low side split gate-source switching transistors,

wherein the current sense resistor comprises a polysilicon resistor having a resistance value of about 200Ohm or less.

In one or more embodiments, the wireless communication system further comprises a voltage sensing circuit connected across the current sense resistor, wherein the voltage sensing circuit is configured to sample a voltage across the current sense resistor to measure a sensed current at the current sense resistor.

These and other aspects of the invention are apparent from and will be elucidated with reference to the embodiments described hereinafter.

Drawings

The present invention may be understood, and its numerous objects, features, and advantages made apparent from the following detailed description of the preferred embodiments, when considered in conjunction with the following drawings.

Fig. 1 shows a switching amplifier connected in an antenna circuit configuration.

Fig. 2 illustrates a circuit schematic of a switching amplifier connected in an antenna circuit configuration with an embedded internal driver current sensing circuit that provides a low cost, area efficient, low resistance implementation for accurately measuring antenna driver current, according to selected embodiments of the present disclosure.

Fig. 3 illustrates a simplified circuit schematic diagram of a current sensor embodied in a split gate-source power FET and an embedded sense resistor, according to selected embodiments of the present disclosure.

FIG. 4 illustrates a cross-sectional view of an integrated circuit current sensor, according to selected embodiments of the present disclosure.

Detailed Description

High performance switching amplifier current sensing circuits, systems, architectures and methods are described for efficiently and accurately measuring driver current by using embedded split gate-source transistor switches with separate power and sense transistors, such that a current sense resistor placed only on the source of one or more small sense transistors can be used to efficiently and accurately measure driver current. In selected differential class D switching amplifier embodiments, the disclosed switching amplifier current sensing circuit includes: an output drive circuit comprising a high side split gate-source switching transistor and a low side gate-source switching transistor connected in series between a pair of supply voltage lines; a switch driver circuit configured to drive the switch transistor with first and second respective control signals; an output connection between the switching transistors for driving an output load; an output current sensing circuit for measuring current through the output load using an integrated circuit current sense transistor connected between a supply voltage line (e.g., ground) and the sources of one or more split gate-source switching transistors of the low side gate-source switching transistors; and a voltage sensing circuit connected across the current sensing resistor, wherein the voltage sensing circuit is configured to sample a voltage across the current sensing resistor.

Although the present disclosure may be used in a wide variety of switching amplifier designs, for the sake of brevity, this specification makes reference to selected switching amplifier embodiments without describing in detail conventional techniques related to signal amplification circuitry in the form of electronic switches and control circuits that affect or act upon the electronic switches and/or output driver circuitry of the signal amplification circuitry. Furthermore, the connecting lines shown in the various figures contained herein are intended to represent example functional relationships and/or physical couplings between the various elements. In certain embodiments, it has been shown that aspects of the present disclosure are beneficial when used in the context of differential class D amplifiers and/or in conjunction with portable and automotive applications in driving antenna loads of the amplifiers. While not necessarily so limited, various aspects may be appreciated from the following discussion of non-limiting examples using the exemplary environment. Accordingly, aspects of the present disclosure are deemed applicable to a variety of different types of switching amplifier circuits, systems, architectures and methods that use control circuitry to affect or act on electronic switching and/or output driver circuitry such that the ramped output drive signal minimizes AM band emissions resulting from activation and deactivation of the switching amplifier.

To provide additional details to better understand the limitations of conventional switching amplifier designs, reference is now made to fig. 1, which illustrates a switching amplifier 100 connected in an antenna circuit configuration. As shown, the switching amplifier 100 may be connected as an output stage of a high power driver including four high power transistors 101 to 104 connecting an antenna load 130 between a first reference voltage and a second reference voltage. High power transistors 101 to 104 are typically transistors handling 0.5A to 100A (or more) for driving various applications, as opposed to low power transistors which are primarily used to control the operation of various applications without directly handling high currents. On the first circuit branch, the high power transistors 101, 103 are connected in series between a first reference voltage (e.g., Vdd) and a second reference voltage (e.g., Vss or ground). And on the second circuit branch the high power transistors 102, 104 are connected in series between the first reference voltage Vdd and the second reference voltage. As shown, the antenna load 130 is connected between a first node ANTP between the high power transistors 111, 113 and a second node ANTN between the high power transistors 112, 114. The controller 120 provides gate drive signals 121-124 to the respective gate driver circuits 111-114 of the high power transistors 101-104 to control the direction of current flow through the antenna load 130 such that current flows only when activated, but not when deactivated.

During the active mode of operation, the output of the antenna switching amplifier 100 is measured with a current sensing circuit comprising an external current sensing resistor R_S-EXTSaid resistor R_S-EXTConnected between the source terminals of the low side switch NMOS transistors 103, 104 and a second reference voltage (e.g., Vss or ground). In such an arrangement, the current or voltage measurement system 140 may be connected to an external sense resistor to detect a voltage drop or flow through resistor R_S-EXTThe current of (2). It is understood that other current sensing techniques may be used, such as by sensing an external current through resistor R_S-EXTConnected to the output of an antenna load driven by linear amplifiers connected in a half-bridge topology, or by using current copy circuitry to generate a small copy of the actual LF driver output current. However, the use of low-ohmic, high-power, accurate series resistors or fully embedded current copy circuits requires significant die area and additional signal processing to meet current measurement accuracy requirements.

To address these and other limitations associated with conventional switching amplifier current sensing designs, referring now to fig. 2, a simplified circuit schematic of a switching amplifier 200 connected in an antenna circuit configuration with an embedded internal driver current sensing circuit that provides a low cost, area efficient, low resistance implementation for accurately measuring antenna driver current is depicted in accordance with selected embodiments of the present disclosure. As shown, the switching amplifier 100 is connected as an output stage of a high power driver comprising field effect transistors (FETs or NMOS FETs) including high side transistors 201, 202 and low side transistors 203, 204 connecting an antenna load 230 between a first reference voltage Vdd and a second reference voltage Vss. As disclosed herein, each transistor (e.g., 201) may be configured as a split gate-source transistor to define a plurality of constituent transistors (e.g., 201A-201D) having a common drain terminal and separate (or "split") gate and source terminals at each constituent transistor. In selected embodiments, transistors 201A-201D are not individual transistors, but rather are individual transistors having individual source fingers formed in the substrate such that transistor structures 201A-201D are electrically isolated (e.g., using deep trench isolation structures, junction isolation structures, SOI trench isolation structures, etc.) from other devices or circuits formed in the substrate (e.g., 202A-202D, 203A-203D, 204A-204D, and any components making up structures 211-214), as described more fully below. With a split gate-source structure, one or more of the constituent transistors (e.g., 201B, 201C) may have a different size than the other constituent transistors (e.g., 201A, 201D). For the high-side transistor 201, the constituent transistors 201A to 201D may have a common drain connected to the first reference voltage Vdd, while the split gate terminals are commonly connected to the gate driving signal from the gate driver circuitry 211, and the split source terminals are commonly connected to the first antenna node ANTP. In a similar manner, the high-side transistor 202 has its constituent transistors 202A to 202D connected to the first reference voltage Vdd through a common drain, while the split gate terminals are commonly connected to the gate drive signal from the gate driver circuitry 212 and the split source terminals are commonly connected to the second antenna node ANTN.

In the low-side transistors 203-204, the split gate-source structure enables the constituent transistors to be configured as one or more relatively large power transistors (e.g., 203A, 203D) and one or more relatively small current sense transistors (e.g., 203B-203C) connected by small series sense resistors to form a current loop for measuring the drive current I at the first antenna node ANTP_D1The current sensing circuit of (1). In particular, by connecting the sense resistor Rs between the sources of the one or more current sense transistors 203B, 203C and the sources of the one or more power transistors 203A, 203D, the sense current I from the one or more current sense transistors 203B, 203C flowing through the sense resistor Rs can be controlled and measured by measuring the differential voltages VSNSresp, VSNSresn across the sense resistor Rs_SThereby measuring a first circuit branch driving current I at a first antenna node ANTP_D1. This current sensing arrangement is mirrored on the second circuit by connecting a sense resistor Rs between the sources of the one or more current sense transistors 204B, 204C and the sources of the one or more power transistors 204A, 204D, in order to control and measure the sense current I from the one or more current sense transistors 204B, 204C flowing through the sense resistor Rs_SAnd measures the differential voltages VSNSresp, VSNSresn across the sense resistor Rs to measure the second circuit branch drive current I at the second antenna node ANTN_D2。

The disclosed current sensing topology 200 utilizing a sense resistor Rs connected to the sources of one or more current sense transistors 203B, 203C provides an area efficient and low cost current sensing circuit that does not meaningfully increase the effective switch RDSon and provides sufficient current measurement accuracy for the target LF driver application. This is accomplished by forming each low side split gate-source transistor with the constituent transistors having different or unequal sizes such that the one or more smaller current sense transistors 203B, 203C pass current to the sense resistor Rs, thereby ensuring substantially equal bias voltages for the one or more current sense transistors 203B, 203C and the one or more power transistors 203A, 203D. And by limiting the maximum voltage on the sense resistor Rs, the required measurement accuracy is obtained. Furthermore, by fabricating the transistor devices in the same silicon processing environment, the one or more power transistors and the one or more current sense transistors of each switch are properly matched.

By sizing one or more current sense transistors (e.g., 203B, 203C) to limit the current being measured, the sense resistor Rs may be implemented internally as an integrated circuit resistor across which the differential voltages VSNSresp, VSNSresn are measured and converted to accurately measure the antenna current (e.g., ± 3-4%). The proposed split gate-source power switch transistor enables to implement a sense resistor Rs with small die area and minimal additional cost, and the resistance value of the sense resistor Rs can be increased to a few (tens) of ohms without increasing the total switch resistance too much, since only the current through one or more sense current transistors passes through the sense resistor Rs. In particular, the proposed split gate-source power switch transistor implementation allows the sense current portion to be easily adapted to the sense resistor values that can be integrated at reasonable cost. For example, for a typical sheet resistance of a polysilicon resistor (e.g., about 200 Ohm/square), the following resistance and area requirements may be obtained:

rs 200Ohm > requires 1 square

Rs 20Ohm > needs 10 square

Rs 2Ohm > needs 100 squares

Rs 0.2Ohm > 1000 squares.

If the split gate-source power FET includes 50 sense fingers, this means that the ratio is 1: 50, 2: 50, 3: 50, etc. For a 1: 50 ratio, a 6Ohm resistor is required at 150mV sense voltage, 1.25A current. For a 2: 50 ratio, a 3Ohm resistor is required, and so on. Thus, the smallest (and therefore lowest cost) resistor is obtained when the largest possible sense current ratio is used.

To provide operational flexibility to the current sensing circuit, one or more low side current sensing transistors (e.g., 203C, 204C) may be programmably connected with one or more switches 220, 221 to improve current sensing performance for different antenna current ranges. With a programmable switch arrangement, one or more additional current sensing transistors (e.g., turn on switch 220) may be effectively added so as to be responsive to the drive current I_DRelatively small, a larger portion of the drive current I is provided to the sense resistor Rs_DFor measurement to ensure that the small input signal can be measured using the differential voltage measurements VSNSresp, VSNSresn. Also, when driving current I_DWhen relatively large, one or more of the current sense transistors may be effectively removed (e.g., switch 220 opened) to provide a smaller portion of the drive current I to the sense resistor Rs_DFor measurement, to prevent differential voltage measurement vsnsresp, vsnsresn exceed a specific range. In general, the ratio of the actual number of current sense transistors Ns (or source "fingers" connected to the sense resistor) to the total number of power transistors Np and current sense transistors Ns determines the drive current I_DWhich part of it will be used as the sense current I_SIs provided to the sense resistor Rs. The equivalent is expressed as: i is_S≈I_D(Ns/(Ns + Np)). From this equation, it can be seen that increasing the number of current sense transistors connected and driven by gate driver circuitry 213 results in a full power FET current I_DLarger of (I)_SAnd (4) partial. This concept can be used to make the sense current I_SIs adapted to the maximum current expected to flow through the low-side switch, so that the resulting sense voltage (V) is measured_S＝I_S×R_S) Neither is it overdriven nor operates with too small a small input signal (resulting in poor signal-to-noise ratio and inaccurate measurement performance).

In the example shown in fig. 2, programmable control of the sense current is provided in the low side switch 203 of the first circuit branch having the gate connected switch 220 to switch the gate of the current sense transistor 203B to the first switch position (connecting the gate of the transistor 203B to the common gate voltage of the low side switch 203) so that the transistor 203B is part of the switch 203 that will conduct its share of the current. Alternatively, the gate connection switch 220 switches the gate of the current sense transistor 203B to the second switch position (connecting the gate of the transistor 203B to its source), so the transistor 203B is off and does not conduct current. In the first switch position of the gate-connected switch 220, the voltage of the sense resistor is generated by the current conducted by the 203C +203B finger, while in the second position of the gate-connected switch 220, the voltage is generated by the current conducted by the 203C finger only.

Similarly, the low side switch 204 on the second circuit branch may include a gate connection switch 221, the gate connection switch 221 for switching the gate of the current sense transistor 204B to either the first switch position (connecting the gate of the transistor 204B to the common gate voltage of the low side switch 204) or the second switch position (connecting the gate of the transistor 204B to its source). In the first placeIn a switching position, at an input current I_DRelatively small, the current sense transistors 203B, 204B drive a larger drive current to the sense resistor Rs, with the source current from transistor 204B turned on to facilitate the drive current through the sense resistor. However, in the second switch position, the current sense transistor 204B is off and does not conduct current, at the input current I_DRelatively large, less drive current is delivered to the sense resistor Rs.

To provide more detail to further an understanding of selected embodiments of the present disclosure, reference is now made to table 1 (below), which shows when connecting switch 220 is open (CurSenseFrac ═ 0) to drive the duty input current I_DLess proportional sense current I_SAnd when the connection switch 220 is closed (currsensefrac ═ 1) to drive the duty cycle input current I_DA sensing current I when the ratio of the sensing current is large_SAnd a sensing voltage V_S：

TABLE 1 LF driver CurSenseFrac force-sense vs. control at internal Current sensing

	CurSenseFrac＝0	CurSenseFrac＝1
			Sensing current	IS＝0.02*ID	IS＝0.04*ID
Sensing voltage	VS＝0.10*ID	VS＝0.20*ID

By programmably controlling the connection of one or more current sensing transistors to the low side switch, the current sensing resistor R can be connected to the low side switch_SA sensing voltage V generated thereon_SControl is within a particular value (e.g., limited to 150mV) to prevent significant current sensing errors due to voltage mismatches between one or more power transistors (e.g., 203A, 203D) and one or more current sense transistors (e.g., 203B, 203C). Using the circuit parameters shown in Table 1, the sense current I is controlled_STo provide a peak sense voltage magnitude of 125mV across the sense resistor and a maximum antenna current level of 1.25A at the low CurSenseFrac setting.

To provide further details to further understand selected embodiments of the present disclosure, reference is now made to fig. 3, which illustrates a simplified circuit schematic of a current sensor 300, the current sensor 300 being embodied in a simplified circuit schematic of a current sensor 300 of a split gate-source power FET 301 and an embedded sense resistor Rs. As depicted, the current sensor 300 includes an input for receiving a gate driver signal that is commonly applied to the gates of the split gate-source transistor 301, the split gate-source transistor 301 defining a first power transistor 301A, a second sense transistor 301B, and a third power transistor 301C. When formed, transistors 301A-301C have a common drain terminal commonly connected to the first power supply voltage Vdd, a plurality of individual (or "split") gate terminals commonly connected to the gate driver signal, and a plurality of individual or "split" source terminals connected as shown. In particular, the source terminals of the power transistors 301A, 301C may be commonly connected to a second power supply voltage (e.g., ground), but the source terminal of the smaller sense transistor 301B may be connected to a first terminal of a sense resistor Rs, the second terminal of which is connected to the second power supply. In such a configuration, current sensing may be implemented with an embedded switch of the power transistor by dividing the embedded switch into a power transistor and one or more current sense transistors, with the current sense resistor Rs placed only in the source of the one or more small current sense transistors.

To provide further details to further an understanding of selected embodiments of the present disclosure, reference is now made to fig. 4, which depicts a cross-sectional view of an integrated circuit current sensor 400. As shown, the current sensor 400 may be formed in a semiconductor substrate 401 using any desired semiconductor fabrication process, wherein a plurality of conductive substrate regions 411 through 414, 421 through 429 are formed in the substrate 401 to be separated from one another by defined isolation regions (ISO) within which the gate electrode stages G1 through G8 are selectively patterned to form separate gate-source power field effect transistors as a plurality of embedded power and current sensing switches having embedded sense resistors Rs connected between the sources of the one or more small current switches and the sources of the one or more power switches. For example, a laterally diffused mosfet (ldmos) fabrication sequence may process a semiconductor wafer substrate layer 401, such as a p-type substrate formed from a single crystal semiconductor material (e.g., silicon), to form defined N-well regions 411-414, such as by selectively implanting N-type dopants (e.g., phosphorus, arsenic) through a patterned mask at a first particular dose and energy using an implant mask to form N-well regions 411-414. Before or after forming the N-well, the wafer may be processed to form an isolation structure ISO in an upper portion of layer 401, such as by etching or otherwise forming a trench filled with a dielectric material, such as silicon oxide, in the substrate using a LOCOS process to define the individual isolation structures ISO. Of course, the isolation structure ISO may also be formed by subsequent deposition, patterning and etching of a dielectric material, such as silicon oxide, after the formation of the N-wells and the P-wells. The formation of the isolation structures ISO is controlled to position each isolation structure ISO within an nwell region so as to separate a drain region D (formed in the nwell) from a source region S (formed outside the nwell).

To control the relative position of the isolation structure ISO with respect to the drain region D, the selective implantation process may selectively implant N- type drain regions 422, 424, 426, 428 using a drain implantation mask (not shown) in combination with the isolation structure ISO at a second specific dose and energy to selectively implant N-type dopants. Gate layers G1 through G8 may then be defined by depositing, patterning, and etching a (conductive) layer (e.g., polysilicon or one or more other gate materials) over wafer 401 using any desired photolithographic etching sequence. Although not shown, each gate layer includes one or more gate dielectric layers formed at least in contact with the underlying substrate, such as by oxidizing the substrate 401 to form an oxide layer or otherwise depositing or growing a dielectric material. After the gate layers G1 through G8 are formed, the relative position of the isolation structure ISO with respect to the source region S is controlled using a selective implantation process that selectively implants N-type dopants using a source implantation mask (not shown) in conjunction with the gate layers G1 through G8 at a third specific dose and energy to selectively implant the N- type drain regions 421, 423, 425, 427, 429. Subsequently, one or more conductive layers are formed within the interconnect stack (not shown) to define the depicted circuit connections. Specifically, one or more first conductor layers are formed to connect the drain terminals 422, 424, 426, 428 in common to a common node that is directly electrically connected to a first reference supply voltage (e.g., Vdd). In addition, one or more second conductor layers are formed to commonly connect the source terminals 421, 423, 427, 429 to a common node that is directly electrically connected to a second reference supply voltage (e.g., ground). Finally, one or more third conductor layers are formed to connect the source terminal 425 to a first terminal of an integrated circuit sense resistor Rs, which has its second terminal connected to a second reference supply voltage (e.g., ground). With the disclosed semiconductor fabrication process, the resulting power FET topology provides improved geometric, mechanical, and thermal matching between the separate source and gate structures within the same substrate region.

It should now be appreciated that switching amplifier circuits, devices, methods and systems having current sensing circuits have been provided for accurately and efficiently measuring output current from a switching amplifier. In a disclosed embodiment, a switching amplifier circuit includes an output drive circuit including a high-side switching transistor and a low-side split gate-source switching transistor connected in series between a first supply voltage line and a second supply voltage line. In selected embodiments, the output drive circuit comprises a first high-side split gate-source switching transistor and a second high-side split gate-source switching transistor, the switching transistors configured and arranged to connect the first supply voltage line to a first output connection and a second output connection, respectively, in response to a first gate control signal and a second gate control signal, and the output drive circuit further comprises a first low-side split gate-source switching transistor and a second low-side split gate-source switching transistor, the switching transistors configured and arranged to connect the second supply voltage line to the first output connection and the second output connection, respectively, in response to the first gate control signal and the second gate control signal. The switching amplifier circuit further includes a switching driver circuit configured to drive the switching transistors with first and second respective control signals, wherein the switching transistors have an output connection between the switching transistors for driving an output load. In selected embodiments, the output drive circuit is a class D amplifier connected to drive the output load, which may be an impedance-based antenna load having an inductor coupled between the first output connection and the second output connection, for wirelessly conveying the modulated signal from the switching amplifier circuit for reception and demodulation by another circuit. In other embodiments, the impedance-based antenna load is configured and arranged to wirelessly convey the modulated signal from the switching amplifier circuit at a carrier frequency of at least ten kilohertz for reception and demodulation by the key fob circuit. Additionally, the switching amplifier circuit includes an output current sensing circuit for measuring current through the output load using a current sense resistor connected between the second supply voltage line and the source of one or more of the low side split gate-source switching transistors. Finally, the switching amplifier circuit includes a voltage sensing circuit connected across the current sense resistor, wherein the voltage sensing circuit is configured to sample a voltage across the current sense resistor to measure a sensed current at the current sense resistor. In selected embodiments, the high-side split gate-source switch transistor includes a first power transistor and a second current sense transistor connected in parallel between the first supply voltage line and the output connection and driven by a common gate control signal, wherein the first power transistor is larger than the second current sense transistor, and wherein the first power transistor and the second power transistor sharing a substrate region are isolated from other components by a substrate isolation structure. In other embodiments, the low side split gate-source switching transistor comprises a first power transistor and a second smaller current sense transistor, each transistor having a drain node directly connected to the output connection and a gate node driven by a common gate control signal, wherein the source node of the first power transistor is connected to the second power supply line, and wherein the source node of the current sense transistor is connected to the current sense resistor. In yet other embodiments, the low side split gate-source switching transistor comprises a third current sensing transistor having a drain node directly connected to the output connection and a source node connected to the current sensing resistor, wherein the gate node of the third current sensing transistor is connected to the common gate control signal in a first connection state through a connection switch and to the source node of the third current sensing transistor in a second connection state through the connection switch such that less current is provided to the current sensing resistor in the second state than in the first state.

In another form, a circuit, apparatus, method and system for accurately measuring output current is provided. In a disclosed embodiment, the circuit includes a switching amplifier, a switching driver circuit, and an output current sensing circuit. The switching amplifier includes a high-side switching transistor and a low-side split gate-source switching transistor connected in series between a first supply voltage line and a second supply voltage line, where there is an output connection between the high-side switching transistor and the low-side switching transistor for driving an output load, which may include an impedance-based load having an inductor coupled between a first output connection node and a second output connection node. Additionally, the output current sensing circuit is provided for measuring current through the output load and includes a current sense resistor connected between the second supply voltage line and the source of one or more of the low side split gate-source switching transistors. As formed, the current sense resistor is an integrated circuit resistor formed in a common semiconductor substrate for the circuit. In selected embodiments, the switching amplifier includes a first high-side electronic switch and a second high-side electronic switch, the electronic switches configured and arranged to connect the first supply voltage line to a first output connection node and a second output connection node, respectively, in response to a first gate control signal and a second gate control signal, and the switching amplifier further includes a first low-side split gate-source switching transistor and a second low-side split gate-source switching transistor, the switching transistors configured and arranged to connect the second supply voltage line to the first output connection node and the second output connection node, respectively, in response to the first gate control signal and the second gate control signal from the switch driver circuit. In selected embodiments, the first and second high-side split gate-source switching transistors and the first and second low-side split gate-source switching transistors are part of a class D amplifier connected to drive the output load, the output load comprising an impedance-based antenna load including an inductor coupled between the first and second output connections, the impedance-based antenna load for wirelessly conveying modulated signals from the switching amplifier circuit for reception and demodulation by another circuit. In other embodiments, the low side split gate-source switching transistor comprises a first power transistor and a second smaller current sense transistor, each transistor having a drain node directly connected to the output connection and a gate node driven by the first control signal, wherein the source node of the first power transistor is connected to the second supply voltage line, and wherein the source node of the current sense transistor is connected to the current sense resistor. Additionally, the low side split gate-source switching transistor may include a third current sensing transistor having a drain node directly connected to the output connection and a source node connected to the current sensing resistor, wherein the gate node of the third current sensing transistor is connected to the first control signal in a first connection state through a connection switch and to the source node of the third current sensing transistor in a second connection state through the connection switch such that less current is provided to the current sensing resistor in the second state than in the first state. In selected embodiments, the current sense resistor is a polysilicon resistor and may have a resistance between 0.2Ohm and 200 Ohm. The circuit also includes a voltage sensing circuit connected across the current sense resistor, wherein the voltage sensing circuit is configured to sample a voltage across the current sense resistor to measure a sensed current at the current sense resistor.

In yet another form, a wireless communication system, circuit, device and method for measuring current at an output load are provided. In a disclosed embodiment, the wireless communication system includes a key fob circuit configured and arranged to wirelessly receive and respond to a modulated signal. In addition, the wireless communication system includes a class D switching amplifier circuit connected to drive an impedance-based load connected between the first output node and the second output node. In selected embodiments, the impedance-based load comprises an inductor coupled between a first output node and a second output node, wherein the impedance-based load is configured and arranged to wirelessly convey the modulated signal from the class D switching amplifier circuit for reception and demodulation by the key fob circuit. As disclosed, the class D switching amplifier circuit includes first and second high-side electronic switches configured and arranged to connect a first reference voltage to the first and second output nodes, respectively, in response to first and second gate control signals. In addition, the class D switching amplifier circuit includes a first and a second low side split gate-source electronic switch configured and arranged to connect a second reference voltage to the first and second output nodes, respectively, in response to the first and second gate control signals. Finally, the class D switching amplifier circuit includes an output current sense circuit for measuring current through the impedance-based load using a current sense resistor connected between the second reference voltage and the source of one or more of the low side split gate-source switching transistors. As disclosed, the current sense resistor may be formed as a polysilicon resistor having a resistance value of about 200Ohm or less. The wireless communication system may further include a voltage sensing circuit connected across the current sensing resistor, wherein the voltage sensing circuit is configured to sample a voltage across the current sensing resistor to measure a sensed current at the current sensing resistor.

Because selected embodiments implementing the present invention are, for the most part, composed of electronic components and circuits known to those skilled in the art, circuit details will not be explained in any greater extent than that considered necessary as illustrated above, for the understanding and appreciation of the underlying concepts of the present disclosure and in order not to obfuscate or distract from the teachings of the present disclosure. It is also to be understood that the terminology used is for the purpose of convenience only and that in actual use, the disclosed structures may be oriented differently than as shown in the figures. Accordingly, the terminology should not be interpreted in a limiting manner. In addition, it should be understood that certain terms may have some overlap in meaning. One example of this is the term "electrode," which may be considered part of a "wire" that does not limit the function of the component or associated circuitry. In many cases, the design may characterize the electrical connection by the "electrode" being used as part of the "wire" and in other designs, vice versa. In addition, the term "electrode" or "lead" may also refer to a combination of a plurality of "electrodes" and "leads" formed in an integrated manner. Also, when an exemplary design is described using FETs, the functionality of the source and drain of the FETs may be switched according to operating conditions and associated voltage polarities; for example, reference to the term "source" or "source terminal" of a FET may be interchangeable with "drain" or "drain terminal" when employing transistors of opposite polarity or changing the direction of current flow in circuit operation. Thus, the terms "source" and "drain" may be interchanged in this description, and similarly, these terms may also be used interchangeably with the terms "source/drain" and "drain/source".

Furthermore, those skilled in the art will recognize that boundaries between the functionality of the above described operations merely illustrative. The functionality of multiple operations may be combined into a single operation, and/or the functionality of a single operation may be distributed in additional operations. Moreover, alternative embodiments may include multiple instances of a particular operation, and the order of operations may be altered in various other embodiments.

The term "coupled," as used herein, is not intended to be limited to a direct coupling or a mechanical coupling. Furthermore, the terms "a" or "an," as used herein, are defined as one or more than one. Furthermore, the use of introductory phrases such as "at least one" and "one or more" in the claims should not be construed to imply that the introduction of another claim element by the indefinite articles "a" or "an" limits any particular claim containing such introduced claim element to inventions containing only one such element, even when the same claim includes the introductory phrases "one or more" or "at least one" and indefinite articles such as "a" or "an". The same holds true for the use of definite articles. Unless otherwise specified, terms such as "first" and "second" are used to arbitrarily distinguish between the elements such terms describe. Thus, these terms are not necessarily intended to indicate temporal or other prioritization of such elements.

Although the described exemplary embodiments disclosed herein relate to methods and systems for measuring output current in circuits, systems, architectures and methods of differential class D switching amplifiers, the invention is not necessarily limited to the exemplary embodiments illustrated herein, and various embodiments of the circuit systems and methods disclosed herein may be implemented with other devices and circuit components. Therefore, the particular embodiments disclosed above are illustrative only and should not be taken as limitations upon the present invention, as the invention may be modified and practiced in different but equivalent manners apparent to those skilled in the art having the benefit of the teachings herein. Therefore, the foregoing description is not intended to limit the invention to the particular form set forth, but on the contrary, is intended to cover such alternatives, modifications and equivalents as may be included within the spirit and scope of the invention as defined by the appended claims so that those skilled in the art should understand that they can make various changes, substitutions and alterations without departing from the spirit and scope of the invention in its broadest form.

Benefits, other advantages, and solutions to problems have been described above with regard to specific embodiments. The benefits, advantages, solutions to problems, and any element(s) that may cause any benefit, advantage, or solution to occur or become more pronounced, however, are not to be construed as a critical, required, or essential feature or element of any or all the claims. As used herein, the terms "comprises," "comprising," "includes" or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus.