阅读说明：本技术 包括具有小粒度的陷阱丰富层的绝缘体上覆半导体(soi)衬底及其形成方法 (Semiconductor-on-insulator (SOI) substrate including trap rich layer having small grain size and method of forming the same ) 是由 郑有宏 吴政达 杜友伦 蔡敏瑛 A·乌先科 于 2019-07-02 设计创作，主要内容包括：本申请案的实施例涉及一种包括具有小粒度的陷阱丰富层的绝缘体上覆半导体(SOI)衬底及其形成方法。在一些实施例中,非晶硅层沉积于高电阻率衬底上。执行快速热退火RTA以使所述非晶硅层结晶为多晶硅的陷阱丰富层,其中大多数晶粒是等轴的。绝缘层形成于所述陷阱丰富层上方。装置层形成于所述绝缘层上方,且包括半导体材料。等轴晶粒小于其它晶粒(例如,柱状晶粒)。由于所述陷阱丰富层中的大多数晶粒是等轴的,所以所述陷阱丰富层具有高晶界面积及高密度的载流子陷阱。所述高密度的载流子陷阱可例如减小寄生表面传导PSC的效应。(Embodiments of the present application relate to a semiconductor-on-insulator (SOI) substrate including a trap rich layer having a small grain size and a method of forming the same. In some embodiments, an amorphous silicon layer is deposited on the high resistivity substrate. A rapid thermal anneal RTA is performed to crystallize the amorphous silicon layer into a trap rich layer of polysilicon, in which most of the grains are equiaxed. An insulating layer is formed over the trap rich layer. A device layer is formed over the insulating layer and includes a semiconductor material. Equiaxed grains are smaller than other grains (e.g., columnar grains). Since most of the grains in the trap rich layer are equiaxed, the trap rich layer has a high crystal interface area and a high density of carrier traps. The high density of carrier traps can, for example, reduce the effects of parasitic surface-conduction PSCs.)

1. A method for forming a semiconductor-on-insulator, SOI, substrate, the method comprising:

depositing an amorphous silicon layer on a high resistivity substrate;

performing a Rapid Thermal Anneal (RTA) to crystallize the amorphous silicon layer into a trap rich layer of polycrystalline silicon, wherein a majority of the grains are equiaxed;

forming an insulating layer over the trap rich layer; and

a device layer is formed over the insulating layer, wherein the device layer includes a semiconductor material.

Technical Field

Embodiments of the invention relate to semiconductor-on-insulator (SOI) substrates including trap rich layers having small grain sizes and methods of forming the same.

Background

Integrated Circuits (ICs) have traditionally been formed on bulk semiconductor substrates. In recent years, semiconductor-on-insulator (SOI) substrates have emerged as an alternative to bulk semiconductor substrates. An SOI substrate includes a handle substrate, an insulating layer overlying the handle substrate, and a device layer overlying the insulating layer. SOI substrates result in, among other things, reduced parasitic capacitance, reduced leakage current, reduced latch-up, and improved semiconductor device performance (e.g., lower power consumption and higher switching speed).

Disclosure of Invention

Embodiments of the invention relate to a method for forming a semiconductor-on-insulator (SOI) substrate, the method comprising: depositing an amorphous silicon layer on a high resistivity substrate; performing a Rapid Thermal Anneal (RTA) to crystallize the amorphous silicon layer into a trap rich layer of polycrystalline silicon, wherein a majority of the grains are equiaxed; forming an insulating layer over the trap rich layer; and forming a device layer over the insulating layer, wherein the device layer comprises a semiconductor material.

Embodiments of the invention relate to a semiconductor-on-insulator (SOI) substrate, comprising: a high resistivity substrate; a trap rich layer overlying the high resistivity substrate, wherein the trap rich layer comprises polycrystalline silicon, wherein a majority of the grains are equiaxed; an insulating layer over the trap rich layer; and a device layer over the insulating layer, wherein the device layer comprises a semiconductor material.

Embodiments of the invention relate to a method for forming a semiconductor structure, the method comprising: depositing an amorphous silicon layer on the high-resistance substrate; heating the amorphous silicon layer to crystallize the amorphous silicon layer into a trap rich layer of polycrystalline silicon, wherein the heating follows a spike temperature profile; forming an insulating layer over the trap rich layer; and forming a device layer over the insulating layer, wherein the device layer comprises a semiconductor material.

Drawings

Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying drawing figures. Note that in accordance with standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

Fig. 1A depicts a cross-sectional view of some embodiments of a semiconductor-on-insulator (SOI) substrate including a trap rich layer having a small grain size.

Fig. 1B depicts an enlarged cross-sectional view of some embodiments of the trap rich layer of fig. 1A.

Fig. 2 depicts a cross-sectional view of some alternative embodiments of the SOI substrate of fig. 1A, wherein a barrier layer separates the trap rich layer from the high resistivity substrate.

Fig. 3 depicts a cross-sectional view of the SOI substrate of fig. 1A, wherein the SOI substrate is subject to substrate warpage.

Fig. 4 depicts a graph of some embodiments of a thickness profile for an insulating layer of the SOI substrate of fig. 1A.

Fig. 5 illustrates a top view of some embodiments of the SOI substrate of fig. 1A.

Fig. 6 illustrates a cross-sectional view of some embodiments of a semiconductor structure in which the SOI substrate of fig. 1A is suitable.

Fig. 7, 8A and 9-17 show a series of cross-sectional views of some embodiments of methods for forming and using an SOI substrate that includes a trap rich layer having a small grain size.

Fig. 8B depicts a graph of some embodiments of temperature profiles for the thermal process performed in fig. 8A.

Fig. 18 depicts a block diagram of some embodiments of the methods of fig. 7, 8A, and 9-17.

Detailed Description

The present disclosure provides many different embodiments, or examples, for implementing different features of the disclosure. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, formation of a feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. Moreover, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Furthermore, spatially relative terms, such as "below …," "below …," "below," "above …," "above," and the like, may be used herein to describe one element or feature's relationship to another element(s) or feature(s), as illustrated in the figures, for convenience of description. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly as such.

Semiconductor-on-insulator (SOI) substrates are commonly used for Radio Frequency (RF) applications. Such SOI substrates may include a high resistivity substrate, an insulating layer overlying the high resistivity substrate, and a device layer overlying the insulating layer. The high resistivity of the high resistivity substrate may reduce RF loss, reduce cross talk, and increase linearity, among other things. However, since the high resistivity substrate is typically silicon, the high resistivity substrate may suffer from Parasitic Surface Conduction (PSC). The fixed charges in the insulating layer attract mobile electrons in the high resistivity substrate, thereby forming a low resistivity region along the top surface of the high resistivity substrate.

Because the low resistivity region has a low resistivity, the low resistivity region negates, at least in part, the benefits of a high resistivity substrate. RF signals (e.g., from devices on an SOI substrate) can induce the formation of eddy currents in low resistivity regions. Eddy currents dissipate RF signals and cause RF losses, whereby passive devices may have low Q factors. Furthermore, eddy currents reflect RF signals, thereby increasing crosstalk and reducing linearity (e.g., increasing second harmonics).

To counteract the effects of the low resistivity region, a trap rich layer of polysilicon may be placed between the high resistivity substrate and the insulating layer. The grain boundaries of the trap rich layer act as carrier traps for mobile electrons, thereby reducing the PSC. However, the trap rich layer is generally formed by slowly heating amorphous silicon into polycrystalline silicon at a high temperature, whereby the trap rich layer has large columnar grains. High temperatures improve throughput but do so at the expense of large particle size. Due to the large columnar grains, the trap rich layer has a low grain boundary area and thus a low trap density, which limits the effectiveness of the trap rich layer in reducing PSCs. In addition, the trap rich layer is generally formed by a single wafer epitaxial tool, whereby the yield is low.

Various embodiments of the present application are directed to SOI substrates comprising a trap rich layer having a small grain size and to SOI substrates produced by the method. In some embodiments, an amorphous silicon layer is deposited on the high resistivity substrate. A Rapid Thermal Anneal (RTA) is performed to crystallize the amorphous silicon layer into a trap rich layer of polycrystalline silicon, in which most of the grains are equiaxed. An insulating layer is formed over the trap rich layer. The device layer is formed over the insulating layer and includes a semiconductor material.

Equiaxed grains are smaller than other grains (e.g., columnar grains). Since most of the crystal grains in the trap rich layer are equiaxed, the trap rich layer has a high crystal interface area and a high density of carrier traps. A high density of carrier traps can, for example, reduce the effects of PSC. By reducing the effects of PSC, SOI substrates facilitate low RF loss, passive devices with high Q factors, low crosstalk, and high linearity (e.g., low second harmonics). The small grain size of the trap rich layer also reduces stress on the high resistivity substrate. The reduced stress reduces substrate warpage and bowing, and further reduces dislocations and slip at the edges of the high resistivity substrate. This in turn can improve yield during the batch fabrication of SOI substrates. Still further, the reduced stress increases the Gate Oxide Integrity (GOI) of at least some devices formed on the SOI substrate, whereby yield may be increased during the bulk fabrication of the devices on the SOI substrate.

Referring to fig. 1A, a cross-sectional view 100A of some embodiments of an SOI substrate 102 is provided. The SOI substrate 102 may be used, for example, for RF applications and/or other applications. In some embodiments, the SOI substrate 102 has a circular top layout and/or has a diameter of about 200, 300, or 450 millimeters. In other embodiments, the SOI substrate 102 has some other shape and/or some other dimensions. Further, in some embodiments, the SOI substrate 102 is a semiconductor wafer (e.g., a bulk silicon wafer). The SOI substrate 102 includes a high resistance substrate 104, a trap rich layer 106, an insulating layer 108, and a device layer 110.

The high-resistance substrate 104 includes a bulk semiconductor region 104b and a low-resistivity region 104 lr. For ease of illustration, hashing (hashing) has been varied between the bulk semiconductor region 104b and the low resistivity region 104 lr. The high resistance substrate 104 may be or may include, for example, monocrystalline silicon, some other silicon material, some other semiconductor material, or any combination of the above.

The bulk semiconductor region 104b underlies the low-resistivity region 104lr and has a high resistance compared to the low-resistivity region 104 lr. The high resistance reduces substrate losses, which improves the Q factor of passive devices (not shown in the figure) on the SOI substrate 102. The high resistance may be, for example, greater than about 1, 3, 4, or 10 kilo-ohms/centimeter (k Ω/cm) and/or may be, for example, between about 1 to 4k Ω/cm, between about 4 to 10k Ω/cm, or between about 1 to 10k Ω/cm. In some embodiments, the high resistance substrate 104 is lightly doped with p-type or n-type dopants to achieve high resistance. The low-resistivity region 104lr extends along the top surface of the high-resistance substrate 104 and is formed due to PSCs. The fixed charges in the insulating layer 108 attract mobile electrons in the high-resistivity substrate 104, thereby forming a low-resistivity region 104 lr.

The trap rich layer 106 overlies the high resistance substrate 104 and is or includes polysilicon. A high percentage of the trap rich layer 106 is defined by equiaxed grains, while a low percentage of the trap rich layer 106 is defined by columnar grains. A high percentage may, for example, be greater than about 80%, 90%, 95%, or 99%, and/or a low percentage may, for example, be less than about 20%, 10%, 5%, or 1%. The percentage may be calculated, for example, as the total area of the trap rich layer 106, the total number of grains in the trap rich layer 106, or some other metric. The columnar grains are large, long grains, so that the columnar grains have a low grain boundary area. Equiaxed grains are small grains having about equal sizes, such that the equiaxed grains have a high grain interface area. Because the equiaxed grains constitute a large percentage of the trap rich layer 106, the trap rich layer 106 has a high crystal interface area and a high density of carrier traps.

The carrier trap traps mobile electrons forming the low-resistivity region 104lr, thereby reducing the size of the low-resistivity region 104lr and reducing the effect of the PSC. Further, due to the high density of carrier traps, the carrier traps trap a large amount of mobile electrons, whereby the low-resistivity region 104lr is small. Accordingly, eddy currents induced in the low resistivity region 104lr by the RF signal are significantly reduced. By significantly reducing eddy currents, RF losses may be low and passive devices on the SOI substrate 102 may have a high Q factor. Furthermore, by significantly reducing eddy currents, linearity is high (e.g., the second harmonic is low), and cross-talk is low. Accordingly, the trap rich layer 106 enhances the SOI substrate 102 for use in conjunction with RF applications and other applications.

In some embodiments, the thickness T of the trap rich layer 106_trIs between about 1 and 2 microns, between about 1.0 and 1.5 microns, or between about 1.5 and 2.0 microns. If the thickness T is_trToo small (e.g., less than about 1.0 micron), the trap rich layer 106 may be inefficient in trapping mobile electrons and reducing the effects of PSC. If the thickness T is_trToo large (e.g., greater than about 2.0 microns), the SOI substrate 102 may be susceptible to substantial substrate warpage. A large amount of substrate warpage may result in poor GOI and misalignment at the edge of the SOI substrate 102, whereby yield may be low.

The insulating layer 108 overlies the trap rich layer 106 and may be or include, for example, silicon oxide, Silicon Rich Oxide (SRO), some other oxide, silicon carbide, silicon nitride, some other dielectric, or any combination of the above. In some embodiments, the thickness of the insulating layer 108T_iIs between about 0.1 and 2 microns, between about 0.1 and 1.0 microns, between about 1.0 and 1.5 microns, or between about 1.5 and 2.0 microns. Furthermore, in some embodiments, the insulating layer 108 has a Total Thickness Variation (TTV) that is low and less than about 10, 25, or 50 nanometers. The TTV may be low due to, for example, small equiaxed grains in the trap rich layer 106. The small equiaxed grains result in the trap rich layer 106 having a relatively smooth top surface, whereby the insulating layer 108 can be formed with a low TTV (e.g., by thermal oxidation).

The device layer 110 overlies the insulating layer 108, and may be or include monocrystalline silicon, some other semiconductor material, or any combination thereof, for example. In some embodiments, the device layer 110 is or includes the same semiconductor material as the high resistance substrate 104. As seen below, the device layer 110 may, for example, support semiconductor devices and/or interconnect structures. The semiconductor device may be, for example, a Metal Oxide Semiconductor Field Effect Transistor (MOSFET) or some other semiconductor device.

Referring to fig. 1B, an enlarged cross-sectional view 100B of some embodiments of the trap rich layer 106 of fig. 1A is provided. The enlarged cross-sectional view 100B may be taken, for example, within block a of fig. 1A, and may, for example, represent the remaining portion of the trap rich layer 106. The trap rich layer 106 includes a plurality of grains 112. For convenience of illustration, only some of the dice 112 are labeled 112. The grains 112 define grain boundaries along which carrier traps are concentrated. As described above, the carrier trap traps mobile electrons forming the low-resistivity region 104lr of fig. 1A, thereby reducing the size of the low-resistivity region 104 lr.

The plurality of grains 112 includes equiaxed grains 112e, and in some embodiments, further includes columnar grains 112 c. For ease of illustration, only some of the equiaxed grains 112e are labeled 112. Equiaxed grains 112e may, for example, constitute more than about 80%, 90%, 95%, or 99% of trap-rich layer 106 and/or may, for example, constitute between about 80% and 90%, between 90% and 95%, or between 95% and 99% of trap-rich layer 106. Columnar grains 112c may, for example, constitute less than about 20%, 10%, 5%, or 1% of trap rich layer 106 and/or may, for example, constitute between about 10% and 20%, between about 5% and 10%, or between about 1% and 5% of trap rich layer 106. The percentage of equiaxed grains 112e and columnar grains 112c may be calculated, for example, as the total area of trap rich layer 106, the total number of grains in trap rich layer 106, or some other metric. In some embodiments, the grains 112 have a respective width W and/or a respective depth (not shown) between about 10-100 nanometers, between about 10-50 nanometers, or between about 50-100 nanometers and/or less than about 100 nanometers, about 50 nanometers, or about 10 nanometers. Note that the individual depths extend into and out of the page, and thus are not visible in fig. 1B.

The equiaxed grains 112e are small grains having about equal sizes such that the equiaxed grains 112e have a high grain interface area. In some embodiments, equiaxed grains 112e have approximately equal dimensions if all dimensions (e.g., height H, width W, and depth D) of equiaxed grains 112e are within about 30%, 20%, or 10% of the average of the dimensions (e.g., (H + W + D)/3). In some embodiments, one, some, or all of the dimensions of equiaxed grains 112e are between about 10 to 100 nanometers, between about 10 to 50 nanometers, or between about 50 to 100 nanometers. For example, the maximum dimension of equiaxed grains 112e may be between one of these ranges. Further, in some embodiments, one (e.g., the largest dimension), some, or all of the dimensions of the equiaxed grains 112e are less than about 100, 50, or 10 nanometers. For example, the maximum size of the equiaxed grains 112e may be less than one or more of these thresholds.

The columnar grains 112c are large, long grains, so that the columnar grains have a low grain boundary area compared to the equiaxed grains 112 e. In some embodiments, if the lateral dimension (e.g., width W and depth D) of the columnar grains 112c is within about 30%, 20%, or 10% of the average of the lateral dimensions (e.g., (W + D)/2), the columnar grains 112c are elongated and the vertical dimension (e.g., height H) of the columnar grains 112c is about 2, 5, 10, or 20 times the average of the lateral dimensions. In some embodiments, one or all of the lateral dimensions (e.g., the largest lateral dimension) of the columnar grains 112c are between about 10-100 nanometers, between about 10-50 nanometers, or between about 50-100 nanometers. For example, the maximum dimension may be between one of these ranges.

Referring to fig. 2, a cross-sectional view 200 of some alternative embodiments of the SOI substrate 102 of fig. 1A is provided in which a barrier layer 202 is interposed between the trap rich layer 106 and the high resistivity substrate 104. The barrier layer 202 may be, for example, silicon oxide, some other dielectric material, or any combination thereof. As seen below, the barrier layer 202 may facilitate formation of the trap rich layer 106, for example, using an epitaxial tool, among other things.

Referring to fig. 3, a cross-sectional view 300 of some embodiments of the SOI substrate 102 of fig. 1A is provided, wherein the SOI substrate 102 has a substrate WARP. The substrate WARP is the separation between the lowest point on the SOI substrate 102 and the highest point on the SOI substrate 102. In some embodiments, the lowest point and the highest point on the SOI substrate 102 correspond to the center 102c of the SOI substrate 102 and the edge 102e of the SOI substrate 102, or vice versa. Substrate WARP may occur, for example, due to different lattices and/or coefficients of thermal expansion between the various layers of the SOI substrate 102 (see fig. 1A).

As seen below, substrate warpage WARP is minimized by using RTA to form the trap rich layer 106. By minimizing substrate WARP, the SOI substrate 102 is less stressed and less susceptible to slip (i.e., dislocation) at the edge 102e of the SOI substrate 102. Furthermore, by minimizing substrate warpage WARP, the GOI of a semiconductor device (not shown) formed on the SOI substrate 102 may be improved. The improved GOI and substrate stress reduction in turn results in higher yields (e.g., during the bulk fabrication of the SOI substrate 102 and/or during the bulk fabrication of devices on the SOI substrate 102).

Referring to fig. 4, a graph 400 depicts a thickness profile 402 for some embodiments of the insulating layer 108 of fig. 1A. Thickness curve 402 depicts thickness T of insulating layer 108 as a function of position along insulating layer 108_i. Further, the thickness profile 402 begins at the left edge LE of the insulating layer 108 and extends beyond the center C of the insulating layer 108 to the right edge RE of the insulating layer 108.

As depicted, the thickness curve 402 has a low TTV. TTV is the difference between the minimum thickness along thickness curve 402 and the maximum thickness along thickness curve 402. The TTV may be low, for example, due to a large number of small equiaxed grains in the trap rich layer 106. The large number of small equiaxed grains results in the trap rich layer 106 having a smooth top surface, whereby the insulating layer 108 is formed with a low TTV (e.g., by thermal oxidation). The TTV may, for example, be low, wherein it is less than about 10, 25, or 50 nanometers and/or between about 5 to 50 nanometers, between about 5 to 25 nanometers, or between about 25 to 50 nanometers.

Referring to fig. 5, a top view 500 of some embodiments of the SOI substrate 102 of fig. 1A is provided. As illustrated, the SOI substrate 102 is a circular wafer and includes a plurality of IC dies 502 arranged in a grid across the device layer 110. For ease of illustration, only some of the IC dies 502 are labeled 502. In some embodiments, each of the IC dies 502 has the same IC and/or each of the IC dies 502 includes a plurality of semiconductor devices.

Referring to fig. 6, a cross-sectional view 600 of some embodiments of a semiconductor structure in which the SOI substrate 102 of fig. 1A is suitable is provided. The semiconductor structure includes a plurality of active devices 602 at a first portion I of the semiconductor structure and further includes a plurality of passive devices 604 at a second portion II of the semiconductor structure. The first part I of the semiconductor structure may for example be used for logic applications, while the second part II of the semiconductor substrate may for example be used for RF applications.

The active devices 602 are laterally spaced above the device layer 110 and are partially defined by the device layer 110. The active device 602 may be, for example, a MOSFET, some other Metal Oxide Semiconductor (MOS) device, some other Insulated Gate Field Effect Transistor (IGFET), some other semiconductor device, or any combination of the above. In some embodiments, the active device 602 includes corresponding source/drain regions 606, corresponding selective conductive vias 608, corresponding gate dielectric layers 610, corresponding gate electrodes 612, and corresponding spacers 614. For convenience of illustration, only one of the source/drain regions 606 is labeled 606, only one of the selective conductive channels 608 is labeled 608, only one of the gate dielectric layers 610 is labeled 610, only one of the gate electrodes 612 is labeled 612, and only one of the spacers 614 is labeled 614.

Source/drain regions 606 and an optional conductive channel 608 are in the device layer 110. The source/drain regions 606 are respectively located at ends of the selectively conductive channels 608, and each of the selectively conductive channels 608 extends from one of the source/drain regions 606 to the other of the source/drain regions 606. The source/drain regions 606 have a first doping type and are directly adjacent to portions of the device layer 110 having a second doping type opposite the first doping type. Gate dielectric layers 610 respectively overlie the selectively conductive channels 608 and gate electrodes 612 respectively overlie the gate dielectric layers 610. The gate dielectric layer 610 may be or may comprise, for example, silicon oxide and/or some other dielectric material, and/or the gate electrode 612 may be or may comprise, for example, doped polysilicon, a metal, some other conductive material, or any combination of the above. Spacers 614 overlie the source/drain regions 606 and line the sidewalls of the gate electrode 612 and the sidewalls of the gate dielectric layer 610, respectively. The spacers 614 may be or include, for example, silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, some other dielectric, or any combination thereof.

In some embodiments, the isolation structures 616 separate the active devices 602 and delineate device regions of the device layer 110 that are individual to the active devices 602. For convenience of illustration, only one of the isolation structures 616 is labeled 616. The isolation structure 616 may be or include, for example, a Shallow Trench Isolation (STI) structure, a Deep Trench Isolation (DTI) structure, some other trench isolation structure, or some other isolation structure. In some embodiments, the isolation structures 616 extend completely through the device layer 110 to the insulating layer 108 for enhanced electrical isolation between the active devices 602. Furthermore, in some embodiments, isolation structures 616 comprise a dielectric material, such as, for example, silicon oxide and/or some other dielectric material.

A back-end-of-line (BEOL) interconnect structure 618 overlies the SOI substrate 102 and the active device 602. The BEOL interconnect structure 618 includes an interconnect dielectric layer 620, a plurality of conductive lines 622, and a plurality of vias 624. For ease of illustration, only some of the conductive lines 622 are labeled 622 and only some of the vias 624 are labeled 624. The interconnect dielectric layer 620 may be or include, for example, phosphosilicate glass (PSG), Undoped Silicon Glass (USG), some other low-k dielectric, silicon oxide, some other dielectric, or any combination of the above. As used herein, a low-k dielectric may be or include, for example, having a dielectric constant k of less than about 3.9, 3, 2, or 1.

Conductive lines 622 and vias 624 are alternately stacked in the interconnect dielectric layer 620 and define conductive paths that extend to the active device 602 and the passive device 604. Note that for ease of illustration, the conductive paths are shown only as extending to active device 602. The conductive paths may, for example, electrically couple the active devices 602 and/or the passive devices 604 to other devices (e.g., other active devices and/or other passive devices), contact pads, or some other structure. The conductive lines 622 and vias 624 may be or may include, for example, copper, aluminum, tungsten, some other metal, or any combination of the above. In some embodiments, the topmost of the conductive lines 622 is thicker than the underlying conductive lines of the conductive lines 622.

The passive devices 604 include passive devices 604r, passive inductors 604i, passive capacitors 604c, or any combination thereof. Furthermore, in some embodiments, the passive device 604 includes a transmission line (not shown in the figures). The passive device 604 may be used, for example, for RF applications of the SOI substrate 102 and the trap rich layer 106 may improve the Q factor of the passive device 604, for example, by reducing crosstalk and improving linearity (e.g., reducing second harmonics).

In some embodiments, the passive resistor 604r is between the SOI substrate 102 and the BEOL interconnect structure 618. In some embodiments, the passive resistor 604r includes a resistive layer 626 and a resistor dielectric layer 628 stacked on the device layer 110. The resistive layer 626 may, for example, be or may comprise doped polysilicon or some other conductive material having a desired resistance. In some embodiments in which the resistive layer 626 is or includes doped polysilicon, the doping concentration of the doped polysilicon is varied to control the resistance of the resistive layer 626. The resistor dielectric layer 628 may, for example, be or may include silicon oxide, some other dielectric material, or any combination of the above.

In some embodiments, the passive inductors 604i are in the BEOL interconnect structure 618 and/or include one or more inductor conductive lines 630. Only one of the inductor wire(s) 630 is labeled 630 for ease of illustration. In some embodiments, inductor wire(s) 630 span multiple heights above SOI substrate 102, and one or more inductor vias 632 interconnect inductor wire(s) 630 across multiple heights. Only one of the inductor via(s) 632 is labeled 632 for convenience of illustration. Inductor wire(s) 630 and inductor via(s) 632 may be or may include, for example, copper, aluminum, tungsten, some other metal, or any combination of the above.

In some embodiments, the passive capacitor 604c is in the BEOL interconnect structure 618 and/or includes a pair of capacitor plates 634 and a capacitor dielectric layer 636. For ease of illustration, only one of the capacitor plates 634 is labeled 634. Capacitor plate 634 and capacitor dielectric layer 636 are stacked with capacitor dielectric layer 636 between capacitor plate 634. Capacitor plate 634 may be or include, for example, copper, aluminum, tungsten, some other metal, or any combination of the above. The capacitor dielectric layer 636 may be or may include, for example, silicon dioxide, some other dielectric material, or any combination thereof.

Although fig. 3-6 are depicted and described using the embodiment of the SOI substrate 102 in fig. 1A, it will be appreciated that the embodiment of the SOI substrate 102 in fig. 2 may also be used. For example, in some embodiments, in fig. 6, the barrier layer 202 of fig. 2 may be arranged between the high resistivity substrate 104 and the trap rich layer 106.

Referring to fig. 7, 8A and 9-17, a series of cross-sectional views 700, 800A, 900-1700 of some embodiments of methods for forming and using SOI substrates comprising trap rich layers having small grain sizes are provided. The method may, for example, be performed to form the SOI substrate of fig. 1A or 2, and/or may, for example, form the semiconductor structure of fig. 6 using an SOI substrate.

As illustrated by the cross-sectional view 700 of fig. 7, a high resistance substrate 104 is provided. In some embodiments, the high resistance substrate 104 has a circular top layout and/or has a diameter of about 200, 300, or 450 millimeters. In other embodiments, the high resistance substrate 104 has some other shape and/or some other dimensions. Further, in some embodiments, the high resistance substrate 104 is a semiconductor wafer (e.g., a bulk silicon wafer). The high resistance substrate 104 has a high resistance and may be or include, for example, monocrystalline silicon, some other silicon material, some other semiconductor material, or any combination of the above.

The high resistance of the high resistance substrate 104 reduces substrate losses, which improves the Q factor of passive devices (not shown) subsequently formed on the formed SOI substrate. The high resistance may be, for example, greater than about 1, 3, 4, or 10k Ω/cm and/or may be, for example, between about 1 to 4k Ω, between about 4 to 10k Ω, or between about 1 to 10k Ω. In some embodiments, the high resistance substrate 104 is lightly doped with p-type or n-type dopants to achieve high resistance. Such a light doping may be performed, for example, by ion implantation or some other doping process.

Also shown by cross-sectional view 700 of fig. 7, an amorphous silicon layer 106' is formed on the high resistance substrate 104. The amorphous silicon layer 106' may be formed, for example, by Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), some other deposition process, or any combination of the above. In some embodiments, the amorphous silicon layer 106 'is formed at a temperature of less than about 600, 550, or 500 degrees celsius (° c) to prevent crystallization of the amorphous silicon layer 106'.

In some embodiments, the amorphous silicon layer 106' is formed in an epitaxial reactor. In some of these embodiments, a barrier layer (not shown) is formed on the high resistance substrate 104 prior to forming the amorphous silicon layer 106', so the epitaxial reactor forms amorphous silicon instead of single crystal silicon. An example of a barrier layer is shown in figure 2 with respect to element 202. Epitaxial reactors may be limited, for example, to processing a single substrate at a time. The barrier layer may, for example, be or may comprise silicon oxide and/or may be formed, for example, while cleaning the high resistivity substrate 104. The cleaning may be performed, for example, by an RCA cleaning process or some other cleaning process. In some embodiments, the amorphous silicon layer 106' is formed by a low pressure cvd (lpcvd) process tool. In some of these embodiments, the amorphous silicon layer 106' may be formed simultaneously on the high resistance substrate 104 and a plurality of other high resistance substrates to improve throughput during batch formation of SOI substrates.

In some embodiments, the thickness T of the amorphous silicon layer 106_aIs between about 1 and 2 microns, between about 1.0 and 1.5 microns, or between about 1.5 and 2.0 microns. If the thickness T is_aToo small (e.g., less than about 1.0 micron),then a subsequent trap rich layer formed from the amorphous silicon layer 106' would be inefficient in reducing the PSC. If the thickness T is_aToo large (e.g., greater than about 2.0 microns), the SOI substrate 102 will be susceptible to substantial substrate warpage. A large amount of substrate warpage will result in poor GOI and misalignment at the edge of the SOI substrate 102, whereby yield may be low.

As illustrated by the cross-sectional view 800A of fig. 8A, a Rapid Thermal Anneal (RTA) is performed on the amorphous silicon layer 106 '(see fig. 7) to convert the amorphous silicon layer 106' into the trap rich layer 106 of polysilicon. The RTA is ramped up at a fast ramp-up rate to a peak temperature above about 600 ℃, held at the peak temperature for a short period of time, and ramped down at a ramp-down rate from the peak temperature to crystallize the amorphous silicon layer 106' in a bulk nucleation (bulk nucleation) mode.

The peak temperature may be, for example, about 1000 ℃, between about 600 to 1500 ℃, between about 600 to 1000 ℃, or between about 1000 to 1500 ℃. The ramp rate may, for example, be at or above about 75, 250, or 1000 ℃/sec, and/or may, for example, be between about 75 to 250 ℃, between about 250 to 625 ℃, or between about 625 to 1000 ℃. The ramp down rate may, for example, be at or above 75, 90, 250, or 1000 ℃/sec, and/or may, for example, be between about 75 to 250 ℃, between about 250 to 625 ℃, or between about 625 to 1000 ℃. In some embodiments, the ramp down rate and the ramp up rate are the same. In some embodiments, the ramp down rate is less than or greater than the ramp up rate. The short period of time at the peak temperature may be, for example, less than or about 0.001, 1, 5, 10, 20, or 30 seconds and/or may be, for example, about 0.001 to 1 second, about 1 to 10 seconds, or about 10 to 30 seconds.

In some embodiments, the RTA follows the spike temperature profile 802 depicted by the graph 800B of fig. 8B. In some embodiments, the amorphous silicon layer 106' is preheated to a preheating temperature prior to RTA. The pre-heating temperature may be, for example, between about 400 to 550 ℃, between about 400 to 500 ℃, or between about 500 to 550 ℃. In some embodiments, the RTA is ramped up from the preheat temperature to the peak temperature, and/or the RTA is ramped down from the peak temperature to the preheat temperature.

In some embodiments, the process for performing RTA includes preheating the amorphous silicon layer 106 'to about 500 ℃, ramping up the heating of the amorphous silicon layer 106' at about 75 ℃/second until about 1000 ℃ is reached, heating the amorphous silicon layer 106 'at about 1000 ℃ for about 10 seconds, and ramping down the heating of the amorphous silicon layer 106'. In other embodiments, the process for performing RTA includes preheating the amorphous silicon layer 106 'to about 500 ℃, ramping up the heating of the amorphous silicon layer 106' at about 1000 ℃/sec up to about 1000 degrees celsius, heating the amorphous silicon layer 106 'at about 1000 degrees celsius for about 1 millisecond, and ramping down the heating of the amorphous silicon layer 106'.

By crystallizing the amorphous silicon layer 106' in the bulk nucleation mode, a high percentage of the trap rich layer 106 is equiaxed grains and a low percentage of the trap rich layer 106 is columnar grains. An example of equiaxed and columnar grains is shown and depicted with respect to fig. 1B, which may be taken, for example, within block a of fig. 8A. A high percentage may, for example, be greater than about 80%, 90%, 95%, or 99%, and/or a low percentage may, for example, be less than about 20%, 10%, 5%, or 1%. The percentage may be calculated, for example, as the total area of the trap rich layer 106, the total number of grains in the trap rich layer 106, or some other metric. If the ramp-up rate during RTA is slow (e.g., less than about 75℃.), the bulk nucleation mode may not take over and the trap rich layer 106 may instead have a high percentage of columnar grains and a low percentage of equiaxed grains.

The columnar grains are large, long grains, so that the columnar grains have a low grain boundary area and a low trap density. Equiaxed grains are small grains having about equal sizes, such that the equiaxed grains have a high grain interface area and a high trap density. Because the equiaxed grains constitute a large percentage of the trap rich layer 106, the trap rich layer 106 has a high crystal interface area and a high density of carrier traps. As seen below, the high density of carrier traps reduces PSC. Further, because the equiaxed grains make up a large percentage of the trap rich layer 106, the trap rich layer 106 generally has small grains. This in turn reduces the stress imposed on the high resistivity substrate 104 by the trap rich layer 106. The reduced stress reduces substrate warpage and bowing, and further reduces dislocations and/or slips at the edge of the high resistivity substrate 104 to improve GOI and yield of subsequently formed devices during mass manufacturing.

In some embodiments, the size (e.g., width, height, and depth) of the equiaxed grains and/or the lateral size (e.g., width and depth) of the columnar grains is between about 10 to 100 nanometers, between about 10 to 50 nanometers, or between about 50 to 100 nanometers and less than about 100 nanometers, about 50 nanometers, or about 10 nanometers. For example, the maximum dimension of equiaxed grains and/or the maximum lateral dimension of columnar grains may be between one of these ranges. In some embodiments, one, some, or all of the equiaxed grains each have approximately equal dimensions, wherein approximately equal dimensions (e.g., height H, width W, and depth D) are within about 30%, 20%, or 10% of an average (e.g., (H + W + D)/3) of approximately equal dimensions. In some embodiments, one, some, or all of the columnar grains each have approximately equal lateral dimensions, wherein approximately equal lateral dimensions (e.g., width W and depth D) are within about 30%, 20%, or 10% of an average of the lateral dimensions (e.g., (W + D)/2). In some embodiments, one, some, or all of the columnar grains each have a vertical dimension (e.g., height) that is about 2, 5, 10, or 20 times the average of the lateral dimensions. In some embodiments, the grains of the trap rich layer 106 are smallest at the bottom of the trap rich layer 106.

As illustrated by the cross-sectional view 900 of fig. 9, a first insulating layer 108a is formed on the trap rich layer 106. The first insulating layer 108a may be, for example, silicon oxide, silicon nitride, some other dielectric, or any combination thereof. Further, the first insulating layer 108a may be formed, for example, by CVD, PVD, thermal oxidation, or some other deposition process. Because a high percentage of the trap rich layer 106 is small equiaxed grains, the top surface of the trap rich layer 106 is relatively smooth. Thus, the first insulating layer 108a has a substantially uniform thickness T_iAnd low TTV.

After and/or concurrently with the formation of the first insulating layer 108a, the PSC may result in the formation of a low resistivity region 104lr in the high resistivity substrate 104. For example, fixed charges in the first insulating layer 108a may attract mobile electrons in the high-resistivity substrate 104, thereby forming the low-resistivity region 104 lr. The low resistivity region 104lr overlies the bulk semiconductor region 104b of the high resistivity substrate 104 and extends along the top surface of the high resistivity substrate 104. Furthermore, the low-resistivity region 104lr has a low resistance compared to the bulk semiconductor region 104 b.

Because a high percentage of the trap rich layer 106 is small equiaxed grains, the trap rich layer 106 has a high density of carrier traps. Further, due to the high density of carrier traps, the carrier traps trap a large amount of mobile electrons, whereby the low-resistivity region 104lr is small. Accordingly, eddy currents induced in the low resistivity region 104lr by the RF signal are significantly reduced. By substantially reducing eddy currents, RF losses can be low and passive devices formed thereafter can have high Q factors. Furthermore, by substantially reducing eddy currents, linearity is high (e.g., the second harmonic is low), and cross-talk is low. Accordingly, the use of RTA to form the trap rich layer 106 enhances SOI substrate formation for use in conjunction with RF applications and other applications.

As illustrated by the cross-sectional view 1000 of fig. 10, a first planarization is performed on the first insulating layer 108 a. The first planarization reduces the thickness T of the first insulating layer 108a_i. In some embodiments, the thickness T_iTo between about 0.1 and 2 microns, between about 0.1 and 1.25 microns, or between about 1.25 and 2.0 microns. The first planarization also reduces the TTV of the first insulating layer 108 a. In some embodiments, the TTV is reduced to less than about 10, 25, or 50 nanometers. Because the TTV is low prior to planarization (as discussed with respect to fig. 9), the first planarization can remove a minimal amount of material to achieve the desired TTV, thereby reducing cost. The first planarization may be performed, for example, by Chemical Mechanical Polishing (CMP) or some other planarization process.

As illustrated by the cross-sectional view 1100 of fig. 11, a device substrate 1102 is provided. In some embodiments, the device substrate 1102 has a circular top layout and/or has a diameter of about 200, 300, or 450 millimeters. In other embodiments, the device substrate 1102 has some other shape and/or some other dimensions. In some embodiments, the device substrate 1102 has the same top layout as the high resistivity substrate 104 (see fig. 10), and/or is a semiconductor wafer (e.g., a bulk silicon wafer). In some embodiments, the device substrate 1102 has a lower resistance than the high resistivity substrate 104 and/or comprises the same semiconductor material as the high resistivity substrate 104. The device substrate 1102 may be or may include, for example, monocrystalline silicon, some other silicon material, some other semiconductor material, or any combination of the preceding.

As illustrated by the cross-sectional view 1100 of fig. 11, a second insulating layer 108b is formed on the device substrate 1102. In some embodiments, the second insulating layer 108b is the same material as the first insulating layer 108a (see fig. 10). The second insulating layer 108b may be, for example, silicon oxide, silicon nitride, some other dielectric, or any combination thereof. Further, the first insulating layer 108a may be formed, for example, by CVD, PVD, thermal oxidation, or some other deposition process.

As illustrated by the cross-sectional view 1200 of fig. 12, an ion-rich layer 1202 is formed completely embedded in the device substrate 1102. As will be seen below, the depth to which the ion-rich layer 1202 is buried affects the thickness of the device layers formed. The ions of the ion-rich layer may be or may include, for example, hydrogen ions and/or some other ions. In some embodiments, the ion-rich layer 1202 is formed by ion-embedding ions 1204 into the device substrate 1102.

As illustrated by the cross-sectional view 1300 of fig. 13, the device substrate 1102 and the second insulating layer 108b are vertically flipped and bonded to the first insulating layer 108a such that the first insulating layer 108a and the second insulating layer 108b are sandwiched between the trap rich layer 106 and the device substrate 1102. The bonding may be performed, for example, by fusion bonding or some other bonding process.

As illustrated by the cross-sectional view 1400 of fig. 14, the device substrate 1102 is cleaved along the ion-rich layer 1202, thereby leaving a portion of the device substrate 1102 (hereinafter device layer 110) bonded to the first insulating layer 108 a. The high resistivity substrate 104, the trap rich layer 106, the first and second insulating layers 108a and 108b, and the device layer 110 collectively define the SOI substrate 102. In some embodiments, the process for cleaving the device substrate 1102 includes annealing. The anneal causes microvoids (or bubbles) to form at the ion-rich layer 1202 (see fig. 13), thereby causing the device substrate 1102 to break apart along the ion-rich layer 1202. In addition, the annealing strengthens the junction between the first insulating layer 108a and the second insulating layer 108 b.

As illustrated by the cross-sectional view 1500 of fig. 15, a second planarization is performed on the device layer 110. The first planarization reduces the thickness T of the device layer 110_dAnd also reduces the TTV of the device layer 110. The second planarization may be performed, for example, by CMP or some other planarization process.

As illustrated by cross-sectional view 1600 of fig. 16, devices are formed on the SOI substrate 102. In some embodiments, the active device 602 is formed at the first portion I of the semiconductor structure formed on the SOI substrate 102. Furthermore, in some embodiments, the passive resistor 604r is formed at the second portion II of the semiconductor structure formed on the SOI substrate 102.

The active devices 602 are laterally spaced above the device layer 110 and are partially defined by the device layer 110. The active device 602 may be, for example, a MOSFET, some other MOS device, some other semiconductor device, or any combination of the above. In some embodiments, the active device 602 includes corresponding source/drain regions 606, corresponding selective conductive vias 608, corresponding gate dielectric layers 610, corresponding gate electrodes 612, and corresponding spacers 614. For convenience of illustration, only one of the source/drain regions 606 is labeled 606, only one of the selective conductive channels 608 is labeled 608, only one of the gate dielectric layers 610 is labeled 610, only one of the gate electrodes 612 is labeled 612, and only one of the spacers 614 is labeled 614. Source/drain regions 606 and an optional conductive channel 608 are in the device layer 110. The source/drain regions 606 are respectively located at ends of the selectively conductive channels 608, and each of the selectively conductive channels 608 extends from one of the source/drain regions 606 to the other of the source/drain regions 606. Gate dielectric layers 610 respectively overlie the selectively conductive channels 608 and gate electrodes 612 respectively overlie the gate dielectric layers 610. Spacers 614 overlie the source/drain regions 606 and line the sidewalls of the gate electrode 612, respectively.

In some embodiments, where gate dielectric layer 610 is or includes an oxide, the GOI of gate dielectric layer 610 is high. The gate dielectric layer 610 may have a high GOI due to the formation of the trap rich layer 106 by RTA. As described above, RTA reduces substrate warpage, which improves GOI. The improved GOI may, for example, improve yield during mass manufacturing of the active devices 602.

In some embodiments, the process for forming the active device 602 includes forming isolation structures 616 in the device layer 110, thereby delineating a device region 1602 individual to the active device 602. The isolation structure 616 may be or may include, for example, an STI structure, a DTI structure, some other trench isolation structure, or some other isolation structure. Thereafter, a dielectric layer is deposited overlying the device layer 110, and a conductive layer is deposited overlying the dielectric layer. The conductive and dielectric layers are patterned (e.g., by a photolithography/etching process) into gate electrode 612 and gate dielectric layer 610. Dopants are implanted into the device region 1602 with the gate electrode 612 in place to define lightly doped portions of the source/drain regions 606 and to form spacers covering the source/drain regions 606 and the gate electrode 612. The spacer layer is etched back to form spacers 614 and dopants are implanted into the device region 1602 with the spacers 614 in place to enlarge the source/drain regions 606.

The passive resistor 604r includes a resistive layer 626 and a resistor dielectric layer 628 stacked on the device layer 110. In some embodiments, the process for forming the passive resistor 604r includes depositing a resistor dielectric layer 628 covering the device layer 110, and further depositing a resistive layer 626 covering the resistor dielectric layer 628. In some embodiments, the resistor dielectric layer 628 and the dielectric layer used to form the gate dielectric layer 610 are the same. Thereafter, the resistor dielectric layer 628 and the resistive layer 626 are patterned (e.g., by a photolithography/etching process) into the passive resistor 604 r.

As illustrated by the cross-sectional view 1700 of fig. 17, a BEOL interconnect structure 618 is formed over the device layer 110. The BEOL interconnect structure 618 includes an interconnect dielectric layer 620, a plurality of conductive lines 622, and a plurality of vias 624. For ease of illustration, only some of the conductive lines 622 are labeled 622 and only some of the vias 624 are labeled 624. Conductive lines 622 and vias 624 are alternately stacked in the interconnect dielectric layer 620 and define conductive paths that interconnect devices (e.g., active devices 602) on the SOI substrate 102.

In some embodiments, the process of forming the BEOL interconnect structure 618 includes forming the bottommost via 624 by a single damascene process, and then forming the bottommost conductive line 622 by a single damascene process. Further, in some embodiments, the process includes forming the remaining layers of vias 624 and the remaining layers of conductive lines 622 by repeatedly performing a dual damascene process. In some embodiments, a single damascene process includes depositing a portion of the interconnect dielectric layer 620, patterning the interconnect dielectric layer 620 with an opening for a single layer of conductive features (e.g., a layer of vias or a layer of conductive lines), and filling the opening with a conductive material to form a single layer of conductive features. In some embodiments, the dual damascene process includes depositing a portion of an interconnect dielectric layer, patterning the interconnect dielectric layer 620 with openings for two layers of conductive features (e.g., a layer of vias and a layer of conductive lines) and filling the openings with conductive material to form two layers of conductive features.

Also illustrated by cross-sectional view 1700 of fig. 17, a passive inductor 604i is formed in the BEOL interconnect structure 618. The passive inductor 604i includes one or more inductor wires 630. Only one of the inductor wire(s) 630 is labeled 630 for ease of illustration. In some embodiments, inductor wire(s) 630 span multiple heights above SOI substrate 102, and passive inductor 604i includes one or more inductor vias 632 interconnecting inductor wire(s) 630 across the multiple heights. Only one of the inductor via(s) 632 is labeled 632 for convenience of illustration. Passive inductor 604i may be formed, for example, with via 624 and conductive line 622. Further, passive inductor 604i may be formed, for example, in the same manner as via 624 and/or conductive line 622, and/or may be formed, for example, using a single damascene process and/or a dual damascene process.

Also illustrated by cross-sectional view 1700 of fig. 17, a passive capacitor 604c is formed in the BEOL interconnect structure 618. Passive capacitor 604c includes a pair of capacitor plates 634 and a capacitor dielectric layer 636. For ease of illustration, only one of the capacitor plates 634 is labeled 634. Capacitor plate 634 and capacitor dielectric layer 636 are stacked with capacitor dielectric layer 636 between capacitor plate 634. The passive capacitor 604c is formed after the formation of the BEOL interconnect structure 618 portion. In some embodiments, the process for forming passive capacitor 604c includes depositing a first plate layer over the partially formed BEOL interconnect structure 618, depositing a capacitor dielectric layer over the first plate layer, and depositing a second plate layer over the capacitor dielectric layer. The first and second plate layers and the capacitor dielectric layer are then patterned (e.g., by a photolithography/etching process) into passive capacitors 604c, and formation of BEOL interconnect structures 618 continues.

Although fig. 7-17 depict forming the SOI substrate 102 using a split of the device substrate 1102, it will be appreciated that other methods of forming the SOI substrate 102 are suitable in other embodiments. However, in these other embodiments, the trap rich layer 106 is still formed as shown and described with respect to fig. 7 and 8. Furthermore, although fig. 16 and 17 depict devices (e.g., passive capacitor 604c) formed on the SOI substrate 102, one, some, or all of these devices may be omitted. Similarly, although fig. 16 and 17 depict the formation of a particular device type on the SOI substrate 102, other device types may be formed on the SOI substrate 102.

Referring to fig. 18, a block diagram 1800 of some embodiments of the methods of fig. 7, 8A, and 9-17 is provided.

At 1802, an amorphous silicon layer is deposited on the high resistivity substrate. See, for example, fig. 7.

At 1804, an RTA is performed on the amorphous silicon layer to convert the amorphous silicon layer to a trap rich layer of polysilicon in the bulk nucleation mode. See, for example, fig. 8A. By crystallizing the amorphous silicon layer in a bulk nucleation mode, a trap rich layer having a high percentage of equiaxed grains and a low percentage of columnar grains is formed. The columnar grains are large, long grains, so that the columnar grains have a low grain boundary area and a low trap density. Equiaxed grains are small grains having about equal sizes, such that the equiaxed grains have a high grain interface area and a high trap density.

Because small grains make up a large percentage of the trap rich layer, the stress imposed on the high resistivity substrate by the trap rich layer is low, and substrate warpage is low. This in turn reduces dislocations and/or slips at the edges of the high resistivity substrate and improves the GOI of the devices formed thereafter. The former can improve yield when bulk forming SOI substrates, while the latter can improve yield when bulk forming devices on SOI substrates.

Because the equiaxed grains constitute a large percentage of the trap rich layer, the trap rich layer has a high crystal interface area and a high density of carrier traps. The carrier traps trap mobile electrons that cause the PSC in the high resistivity substrate, thereby minimizing the PSC. By minimizing PSC, RF losses can be low and passive devices on SOI substrates can have high Q factors. Further, linearity may be high (e.g., the second harmonic may be low), and crosstalk may be low. Accordingly, the trap rich layer enhances the SOI substrate for use in conjunction with RF applications and other applications.

At 1806, a first insulating layer is deposited over the trap rich layer. See, for example, fig. 9.

At 1808, planarization is performed on the first insulating layer. See, for example, fig. 10. Because a high percentage of the trap rich layer is equiaxed grains, the top surface of the trap rich layer is relatively smooth. This results in the first insulating layer having a substantially uniform thickness and a low TTV. Furthermore, because the TTV is low prior to planarization, the first planarization can remove a minimal amount of material from the first insulating layer to achieve the desired TTV, thereby reducing cost.

At 1810, a second insulating layer is formed on the device substrate. See, for example, fig. 11.

At 1812, an ion rich layer is formed to be embedded in the device substrate. See, for example, fig. 12.

At 1814, the first and second insulating layers are bonded together such that the first and second insulating layers are between the device substrate and the trap rich layer. See, for example, fig. 13.

At 1816, the device substrate is cleaved along the ion-rich layer to define a device layer. See, for example, fig. 14.

At 1818, planarization is performed on the device layer. See, for example, fig. 15.

At 1820, a device is formed on the device layer. See, for example, fig. 16.

At 1822, a BEOL interconnect structure is formed overlying the device layer and the devices. See, for example, fig. 17.

While block diagram 1800 of fig. 18 is depicted and described herein as a series of acts or events, it will be appreciated that the depicted ordering of such acts or events are not to be interpreted in a limiting sense. For example, some acts may occur in different orders and/or concurrently with other acts or events apart from those illustrated and/or described herein. Further, not all depicted acts may be required to implement one or more aspects or embodiments described herein, and one or more of the acts depicted herein may be performed in one or more separate acts and/or phases.

In some embodiments, the present application provides a method for forming an SOI substrate, the method comprising: depositing an amorphous silicon layer on a high resistivity substrate; performing RTA to crystallize the amorphous silicon layer into a trap rich layer of polycrystalline silicon, wherein a majority of the grains are equiaxed; forming an insulating layer over the trap rich layer; and forming a device layer over the insulating layer, wherein the device layer comprises a semiconductor material. In some embodiments, the performing of RTA includes ramping up heating of the amorphous silicon layer at a ramp rate of greater than about 75 degrees celsius/second until a high temperature of greater than about 600 degrees celsius is reached. In some embodiments, the performing of RTA includes ramping down the heating of the amorphous silicon layer after heating the amorphous silicon layer for a short period of time less than about 10 seconds. In some embodiments, the RTA forms a trap rich layer having a high percentage of equiaxed grains, and wherein the high percentage is greater than about 80% of the total number of grains. In some embodiments, the method further comprises forming a barrier oxide layer over the high resistivity substrate, wherein the amorphous silicon layer is deposited over the barrier oxide layer by an epitaxial tool. In some embodiments, an amorphous silicon layer is simultaneously deposited on a high resistivity substrate and a plurality of other high resistivity substrates within a multi-substrate process tool. In some embodiments, the forming of the insulating layer comprises: depositing an insulating layer on the trap rich layer; and performing planarization on the insulating layer. In some embodiments, the forming of the device layer includes: depositing a second insulating layer on the device substrate; implanting ions into the device substrate through the second insulating layer to form an ion-rich layer buried in the device substrate; bonding a second insulating layer to the insulating layer such that the insulating layer and the second insulating layer are between the device substrate and the trap rich layer; and fragmenting the device substrate along the ion-rich layer to remove a portion of the device substrate, wherein a remaining portion of the device substrate defines a device layer. In some embodiments, the method further comprises forming a low resistivity region in the high resistivity substrate along a top surface of the high resistivity substrate while formed through the insulating layer, wherein the low resistivity region has a lower resistance than a bulk of the high resistivity substrate.

In some embodiments, the present application provides an SOI substrate comprising: a high resistivity substrate; a trap rich layer overlying the high resistivity substrate, wherein the trap rich layer comprises polycrystalline silicon, wherein a majority of the grains are equiaxed; an insulating layer over the trap rich layer; and a device layer over the insulating layer, wherein the device layer comprises a semiconductor material. In some embodiments, at least about 80% of the polysilicon grains in the trap rich layer are equiaxed grains. In some embodiments, less than about 20% of the polysilicon grains in the trap rich layer are columnar grains. In some embodiments, a majority of the grains have a largest dimension of less than about 100 nanometers. In some embodiments, the high-resistivity substrate includes a low-resistivity region and a bulk semiconductor region, wherein the bulk semiconductor region underlies the low-resistivity region and has a high resistance that is greater than the resistance of the low-resistivity region. In some embodiments, the high resistivity substrate has a high resistance of greater than about 1k Ω/cm. In some embodiments, the SOI substrate further comprises a dielectric barrier layer between the high resistivity substrate and the trap rich layer.

In some embodiments, the present application provides a method for forming a semiconductor structure, the method comprising: depositing an amorphous silicon layer on the high-resistance substrate; heating the amorphous silicon layer to crystallize the amorphous silicon layer into a trap rich layer of polycrystalline silicon, wherein the heating follows a spike temperature profile; forming an insulating layer over the trap rich layer; and forming a device layer over the insulating layer, wherein the device layer comprises a semiconductor material. In some embodiments, heating comprises ramping the temperature at a ramp rate of greater than about 75 degrees celsius per second until an elevated temperature of greater than about 600 degrees celsius is reached. In some embodiments, the heating forms a trap rich layer having a high percentage of equiaxed grains and a low percentage of columnar grains, wherein the high percentage is greater than about 80% of the total number of grains, and wherein the low percentage is less than about 20% of the total number of grains. In some embodiments, the method further comprises: forming a semiconductor device overlying and defined by a device layer portion; and forming an interconnect structure overlying the semiconductor device and the device layer, wherein the interconnect structure comprises an alternating stack of wires and vias.

The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.

Description of the symbols

Cross-sectional view taken at 100A

100B enlarged cross-sectional view

102 semiconductor-on-insulator (SOI) substrate

102c center of the substrate

102e edge of substrate

104 high resistance substrate

104b bulk semiconductor region

104lr low resistivity region

106 trap rich layer

106' amorphous silicon layer

108 insulating layer

108a first insulating layer

108b second insulating layer

110 device layer

112 crystal grains

112c columnar grains

112e equiaxed grain

200 cross-sectional view

202 barrier layer

300 cross-sectional view

400 chart

402 thickness curve

500 Top plan view

502 IC die

600 cross-sectional view

602 active device

604 passive devices

604c passive capacitor

604i passive inductor

604r passive device

606 source/drain regions

608 selective conductive pathway

610 gate dielectric layer

612 gate electrode

614 spacer

616 isolation structures

618 back end of line (BEOL) interconnect structure

620 interconnect dielectric layer

622 wire

624 pathway

626 passive capacitor

628 resistor dielectric layer

630 inductor conductor

632 inductor path

634 capacitor plate

636 capacitor dielectric layer

700 cross-section view

800A cross-sectional view

800B diagram

802 peak temperature curve

900 section view

1000 section view

1100 cross-sectional view

1102 device substrate

1200 cross-sectional view

1202 ion rich layer

1204 ion

1300 cross-sectional view

1400 section view

1500 section view

1600 cross-sectional view

1602 device region

1700 cross-sectional view

1800 block diagram

1802 act

1804 act

1806 actions

1808 actions

1810 action

1812 actions

1814 actions

1816 actions

1818 actions

1820 act

1822 act

I first part

II second part

A square frame

Height H

T_aThickness of

T_dThickness of

T_iThickness of

T_trThickness of

Width W

WARP of WARP substrate