阅读说明：本技术 经编码比特到码元的基于优先级的映射 (Priority-based mapping of encoded bits to symbols ) 是由 H·金 H·桑卡尔 A·Y·格洛科夫 M·麦克克劳德 J·B·索里亚加 于 2018-04-27 设计创作，主要内容包括：公开了可以由UE和基站执行的新无线电(NR)比特优先化规程,其导致具有经优先化比特的调制码元的传送和接收。例如,发射机可以使用低密度奇偶校验码对码块进行编码,以生成经编码比特流。发射机可以根据经编码比特的相对优先级将经编码比特布置在一个或多个调制码元中。最高优先级比特可以位于调制码元的诸最高有效比特中,且因此不太可能经历出错。接收机可以接收调制码元并且在解码经编码比特之前基于相对优先级对根据编码方案的经编码比特进行重排序。与经编码比特到码元的顺序映射相比,调制码元内的比特的优先化可以提供改善的块出错率。(A New Radio (NR) bit prioritization procedure is disclosed that may be performed by a UE and a base station that results in the transmission and reception of modulation symbols with prioritized bits. For example, the transmitter may encode the code block using a low density parity check code to generate an encoded bitstream. The transmitter may arrange the coded bits in one or more modulation symbols according to their relative priorities. The highest priority bits may be located in the most significant bits of the modulation symbol and thus are less likely to experience errors. The receiver may receive the modulation symbols and reorder the encoded bits according to the coding scheme based on the relative priority before decoding the encoded bits. Prioritization of bits within modulation symbols may provide improved block error rates compared to sequential mapping of encoded bits to symbols.)

1. A method of wireless communication, comprising:

encoding a code block using a Low Density Parity Check (LDPC) code to generate an encoded bit stream comprising systematic bits and parity bits;

determining an exponent for each of the systematic bits and parity bits;

determining a relative priority of each encoded bit based on the power of each systematic bit and parity bit;

arranging the coded bits in one or more modulation symbols according to the relative priority of each coded bit; and

transmitting the one or more modulation symbols.

2. The method of claim 1, wherein the arranging comprises reordering the encoded bit stream according to the relative priority.

3. The method of claim 2, further comprising interleaving the encoded bit stream after reordering the encoded bits.

4. The method of claim 1, wherein arranging the coded bits comprises mapping the coded bits to positions in the one or more modulation symbols based on the relative priorities.

5. The method of claim 4, wherein higher priority bits are located in the most significant bits of each of the one or more modulation symbols.

6. The method of claim 4, wherein lower priority bits are located in least significant bits of each of the one or more modulation symbols.

7. The method of claim 4, wherein the mapping comprises looking up the location for each bit based on a mapping table.

8. The method of claim 4, wherein the mapping comprises assigning the location based on a formula.

9. The method of claim 1, further comprising determining relative priorities of the systematic bits and the parity bits based on a coding scheme of the LDPC code.

10. The method of claim 1, wherein the systematic bits and parity bits are grouped in powers, and wherein determining the relative priority comprises determining that each bit in a group of systematic bits or a group of parity bits having the same power has the same relative priority.

11. An apparatus, comprising:

a memory; and

a processor in communication with the memory, wherein the processor is configured to:

encoding a code block using a Low Density Parity Check (LDPC) code to generate an encoded bit stream comprising systematic bits and parity bits;

determining an exponent for each of the systematic bits and parity bits;

determining a relative priority of each encoded bit based on the power of each systematic bit and parity bit;

arranging the coded bits in one or more modulation symbols according to the relative priority of each coded bit; and

transmitting the one or more modulation symbols.

12. The apparatus of claim 11, wherein the processor is configured to reorder the encoded bitstream according to the relative priority.

13. The apparatus of claim 12, wherein the processor is further configured to interleave the encoded bit stream after reordering the encoded bits.

14. The apparatus of claim 11, wherein the processor is configured to map each of the coded bits to a position in the one or more modulation symbols based on the relative priority.

15. The apparatus of claim 14, wherein higher priority bits are located in most significant bits of each of the one or more modulation symbols.

16. The apparatus of claim 14, wherein lower priority bits are located in least significant bits of each of the one or more modulation symbols.

17. The apparatus of claim 14, wherein the processor is configured to look up the position for each encoded bit based on a mapping table.

18. The apparatus of claim 14, wherein the processor is configured to assign the location based on a formula.

19. The apparatus of claim 11, wherein the processor is configured to determine the relative priorities of the systematic bits and the parity bits based on a coding scheme of the LDPC code.

20. The apparatus of claim 11, wherein the parity bits are grouped in powers, and wherein the processor is configured to determine that each bit in a group of systematic bits or a group of parity bits having the same power has the same relative priority.

21. An apparatus, comprising:

means for encoding a code block using a Low Density Parity Check (LDPC) code to generate an encoded bitstream comprising systematic bits and parity bits;

means for determining an exponent of each of the systematic bits and parity bits;

means for determining a relative priority of each encoded bit based on the power of each systematic bit and parity bit;

means for arranging the coded bits in one or more modulation symbols according to the relative priority of each coded bit; and

means for transmitting the one or more modulation symbols.

22. The apparatus of claim 21, wherein the means for arranging is configured to reorder the encoded bitstream according to the relative priority.

23. The apparatus of claim 22, further comprising means for interleaving the encoded bit stream after reordering the encoded bits.

24. The apparatus of claim 21, wherein the means for arranging is configured to map the coded bits to positions in the one or more modulation symbols based on the relative priorities.

25. The apparatus of claim 24, wherein higher priority bits are located in most significant bits of each of the one or more modulation symbols.

26. The apparatus of claim 24, wherein lower priority bits are located in least significant bits of each of the one or more modulation symbols.

27. The apparatus of claim 24, wherein the means for arranging is configured to look up the position for each encoded bit based on a mapping table.

28. The apparatus of claim 24, wherein the means for arranging is configured to assign the location based on a formula.

29. The apparatus of claim 21, wherein the means for determining the relative priority is configured to determine the relative priority based on a coding scheme of the LDPC code.

30. A computer-readable medium storing computer code executable by a processor for wireless communication, comprising one or more codes operable to:

encoding a code block using a Low Density Parity Check (LDPC) code to generate an encoded bit stream comprising systematic bits and parity bits;

determining an exponent for each of the systematic bits and parity bits;

determining a relative priority of each encoded bit based on the power of each systematic bit and parity bit;

arranging the coded bits in one or more modulation symbols according to the relative priority of each coded bit; and

transmitting the one or more modulation symbols.