阅读说明：本技术 氮化物晶体基板、半导体层叠物、半导体层叠物的制造方法以及半导体装置的制造方法 (Nitride crystal substrate, semiconductor laminate, method for manufacturing semiconductor laminate, and method for manufacturing semiconductor device ) 是由 堀切文正 吉田丈洋 于 2018-04-19 设计创作，主要内容包括：一种氮化物晶体基板,其由III族氮化物的晶体形成,且含有n型杂质,将波长设为λ(μm)、将27℃下的氮化物晶体基板的吸收系数设为α(cm<Sup>-1</Sup>)、将氮化物晶体基板中的自由电子浓度设为n(cm<Sup>-3</Sup>)、将K和a各自设为常数时,在至少1μm以上且3.3μm以下的波长范围内的吸收系数α由以下的式(1)(α＝nKλ<Sup>a</Sup>,其中,1.5×10<Sup>-19</Sup>≤K≤6.0×10<Sup>-19</Sup>、a＝3)进行近似。(A nitride crystal substrate nitrided by group IIICrystal of the substance, and contains n-type impurities, wherein the wavelength is lambda (mum), and the absorption coefficient of the nitride crystal substrate at 27 ℃ is alpha (cm) ‑1 ) And n (cm) is the free electron concentration in the nitride crystal substrate ‑3 ) And when K and a are each constant, the absorption coefficient α in a wavelength range of at least 1 μm or more and 3.3 μm or less is represented by the following formula (1) (α ═ nK λ a Wherein, 1.5 is multiplied by 10 ‑19 ≤K≤6.0×10 ‑19 And a is 3).)

1. A nitride crystal substrate formed of a crystal of a group III nitride and containing an n-type impurity,

the wavelength is set to lambda (mum), and the absorption coefficient of the nitride crystal substrate at 27 ℃ is set to alpha (cm)^-1) And n (cm) is a free electron concentration in the nitride crystal substrate^-3) And the absorption coefficient α in a wavelength range of at least 1 μm or more and 3.3 μm or less is approximated by the following formula (1) when K and a are each constant:

α＝nKλ^a…(1)

wherein, 1.5 is multiplied by 10^-19≤K≤6.0×10^-19、a＝3。

2. The nitride crystal substrate according to claim 1, wherein the absorption coefficient α in a wavelength range of at least 1 μm or more and 3.3 μm or less is approximated by the following formula (1) ":

α＝2.2×10^-19nλ³…(1)”。

3. the nitride crystal substrate according to claim 1 or 2, wherein when a difference between a maximum value and a minimum value of the absorption coefficient α in a main surface of the nitride crystal substrate is Δ α, the absorption coefficient α and Δ α satisfy the following expressions (2) and (3) in a wavelength range of at least 1 μm or more and 3.3 μm or less:

α≥0.15λ³…(2)，

Δα≤1.0…(3)。

4. a nitride crystal substrate formed of a crystal of a group III nitride and containing an n-type impurity,

the nitride crystal substrate has an absorption coefficient of 1.2cm at a wavelength of 2 μm^-1In the above-mentioned manner,

the difference between the maximum value and the minimum value of the absorption coefficient at a wavelength of 2 μm in the main surface of the nitride crystal substrate is 1.0cm^-1Within.

5. The nitride crystal substrate according to any one of claims 1 to 4, wherein,

the concentration of intrinsic carriers that are thermally excited between bands of the nitride crystal substrate under the temperature condition of 27 ℃ or more and 1250 ℃ or less is lower than the concentration of free electrons generated in the nitride crystal substrate due to the doping of the n-type impurity under the temperature condition of 27 ℃.

6. The nitride crystal substrate according to any one of claims 1 to 5, wherein,

the concentration of free electrons generated in the nitride crystal substrate by the doping of the n-type impurity is 1 × 10 under the temperature condition of 27 ℃¹⁸cm^-3In the above-mentioned manner,

the difference between the maximum value and the minimum value of the free electron concentration in the main surface of the nitride crystal substrate is 8.3 x 10¹⁷cm^-3Within.

7. The nitride crystal substrate according to any one of claims 1 to 6, wherein,

the concentration of the n-type impurity in the nitride crystal substrate is 1.0 × 10¹⁸at·cm^-3In the above-mentioned manner,

the difference between the maximum value and the minimum value of the concentration of the n-type impurity in the main surface of the nitride crystal substrate is 8.3 × 10¹⁷at·cm^-3Within.

8. The nitride crystal substrate according to any one of claims 1 to 7, wherein,

the concentration of oxygen in the nitride crystal substrate is 1/10 times or less with respect to the total concentration of silicon and germanium in the nitride crystal substrate.

9. A semiconductor laminate, comprising:

a nitride crystal substrate formed of a crystal of a group III nitride and containing an n-type impurity; and

a semiconductor layer provided on the nitride crystal substrate and formed of a group III nitride semiconductor;

the wavelength is set to lambda (mum), and the absorption coefficient of the nitride crystal substrate at 27 ℃ is set to alpha (cm)^-1) And n (cm) is a free electron concentration in the nitride crystal substrate^-3) And the absorption coefficient α in a wavelength range of at least 1 μm or more and 3.3 μm or less is approximated by the following formula (1) when K and a are each constant:

α＝nKλ^a…(1)

wherein, 1.5 is multiplied by 10^-19≤K≤6.0×10^-19、a＝3。

10. A semiconductor laminate, comprising:

a nitride crystal substrate formed of a crystal of a group III nitride and containing an n-type impurity; and

a semiconductor layer provided on the nitride crystal substrate and formed of a group III nitride semiconductor,

the nitride crystal substrate has an absorption coefficient of 1.2cm at a wavelength of 2 μm^-1In the above-mentioned manner,

the difference between the maximum value and the minimum value of the absorption coefficient at a wavelength of 2 μm in the main surface of the nitride crystal substrate is 1.0cm^-1Within.

11. The semiconductor laminate according to claim 9 or 10,

the reflectance of the surface of the semiconductor layer is 5% to 30% in a wavelength range of at least 1 [ mu ] m to 3.3 [ mu ] m.

12. A method for manufacturing a semiconductor laminate, comprising:

preparing a nitride crystal substrate that is formed of a group III nitride crystal and contains an n-type impurity; and

a step of heating the nitride crystal substrate by irradiating the nitride crystal substrate with at least infrared rays,

in the step of preparing the nitride crystal substrate,

as the nitride crystal substrate, the following substrates were prepared: the wavelength is set to lambda (mum), and the absorption coefficient of the nitride crystal substrate at 27 ℃ is set to alpha (cm)^-1) And n (cm) is a free electron concentration in the nitride crystal substrate^-3) And the absorption coefficient α in a wavelength range of at least 1 μm or more and 3.3 μm or less is approximated by the following formula (1) when K and a are each constant:

α＝nKλ^a…(1)

wherein, 1.5 is multiplied by 10^-19≤K≤6.0×10^-19、a＝3。

13. A method for manufacturing a semiconductor laminate, comprising:

preparing a nitride crystal substrate that is formed of a group III nitride crystal and contains an n-type impurity; and

a step of heating the nitride crystal substrate by irradiating the nitride crystal substrate with at least infrared rays,

in the step of preparing the nitride crystal substrate,

as the nitride crystal substrate, an absorption coefficient at a wavelength of 2 μm of 1.2cm was prepared^-1Above and having a difference of 1.0cm between the maximum value and the minimum value of the absorption coefficient at a wavelength of 2 μm in the main plane^-1A substrate inside.

14. The method for manufacturing a semiconductor laminate according to claim 12 or 13,

the step of heating the nitride crystal substrate includes a step of epitaxially growing a semiconductor layer made of a group III nitride semiconductor on the nitride crystal substrate.

15. The method for manufacturing a semiconductor laminate according to claim 14, comprising:

a step of performing epitaxial growth on the nitride crystal substrate using a p-type semiconductor layer containing a p-type impurity as a layer constituting the semiconductor layer; and

and a step of heating the nitride crystal substrate to activate the p-type impurity in the p-type semiconductor layer, the step being a step of heating the nitride crystal substrate.

16. The method for manufacturing a semiconductor laminate according to claim 14, comprising:

implanting an impurity of a predetermined conductivity type into the semiconductor layer; and

and a step of heating the nitride crystal substrate to activate the impurity in the semiconductor layer, the step being a step of heating the nitride crystal substrate.

17. A method for manufacturing a semiconductor laminate, comprising:

preparing a nitride crystal substrate that is formed of a group III nitride crystal and contains an n-type impurity; and

a step of heating the nitride crystal substrate by irradiating the nitride crystal substrate with at least infrared rays,

the step of preparing a nitride crystal substrate includes:

measuring an absorption coefficient of the nitride crystal substrate in an infrared region at 27 ℃; and

determining, based on the measured absorption coefficient of the nitride crystal substrate, that the wavelength is set to λ (μm) and the absorption coefficient of the nitride crystal substrate is set to α (cm)^-1) And n (cm) is a free electron concentration in the nitride crystal substrate^-3) And a step of determining whether or not the absorption coefficient α in a wavelength range of at least 1 μm or more and 3.3 μm or less can be approximated by the following formula (1) when K and a are each constant:

α＝nKλ^a…(1)

wherein, 1.5 is multiplied by 10^-19≤K≤6.0×10^-19、a＝3。

18. A method for manufacturing a semiconductor laminate, comprising:

preparing a nitride crystal substrate that is formed of a group III nitride crystal and contains an n-type impurity; and

a step of heating the nitride crystal substrate by irradiating the nitride crystal substrate with at least infrared rays,

the step of preparing a nitride crystal substrate includes:

measuring an absorption coefficient in an infrared region at least at 2 points or more in a main surface of the nitride crystal substrate; and

determining whether or not the absorption coefficient at a wavelength of 2 μm of the nitride crystal substrate is 1.2cm based on the measured absorption coefficient of the nitride crystal substrate^-1And whether or not the difference between the maximum value and the minimum value of the absorption coefficient at a wavelength of 2 μm in the main surface of the nitride crystal substrate is 1.0cm^-1The following steps.

19. A method for manufacturing a semiconductor device, comprising:

preparing a nitride crystal substrate that is formed of a group III nitride crystal and contains an n-type impurity; and

a step of heating the nitride crystal substrate by irradiating the nitride crystal substrate with at least infrared rays,

in the step of preparing the nitride crystal substrate,

as the nitride crystal substrate, the following substrates were prepared: the wavelength is set to lambda (mum), and the absorption coefficient of the nitride crystal substrate at 27 ℃ is set to alpha (cm)^-1) And n (cm) is a free electron concentration in the nitride crystal substrate^-3) And the absorption coefficient α in a wavelength range of at least 1 μm or more and 3.3 μm or less is approximated by the following formula (1) when K and a are each constant:

α＝nKλ^a…(1)

wherein, 1.5 is multiplied by 10^-19≤K≤6.0×10^-19、a＝3。

20. A method for manufacturing a semiconductor device, comprising:

preparing a nitride crystal substrate that is formed of a group III nitride crystal and contains an n-type impurity; and

a step of heating the nitride crystal substrate by irradiating the nitride crystal substrate with at least infrared rays,

in the step of preparing the nitride crystal substrate,

as the nitride crystal substrate, an absorption coefficient at a wavelength of 2 μm of 1.2cm was prepared^-1Above and having a difference of 1.0cm between the maximum value and the minimum value of the absorption coefficient at a wavelength of 2 μm in the main plane^-1A substrate inside.

Technical Field

The present invention relates to a nitride crystal substrate, a semiconductor laminate, a method for manufacturing a semiconductor laminate, and a method for manufacturing a semiconductor device.

Background

Group III nitride semiconductors are widely used as materials for semiconductor devices constituting light-emitting devices, electronic devices, and the like. In the production of these semiconductor devices, for example, a step of heating a nitride crystal substrate formed of a group III nitride semiconductor such as a step of epitaxially growing a semiconductor layer on the nitride crystal substrate and a step of activating impurities in the semiconductor layer may be performed (see, for example, patent document 1).

Disclosure of Invention

Problems to be solved by the invention

The above-described process of heating a nitride crystal substrate is required to heat the nitride crystal substrate with good accuracy and good reproducibility.

The purpose of the present invention is to provide a technique that can heat the nitride crystal substrate with good accuracy and good reproducibility.

Means for solving the problems

In accordance with one aspect of the present invention,

provided are a nitride crystal substrate formed of a crystal of a group III nitride and containing an n-type impurity,

the wavelength is represented by λ (μm), and the absorption coefficient of the nitride crystal substrate at 27 ℃ is represented by α (cm)^-1) And n (cm) is a free electron concentration in the nitride crystal substrate^-3) And the absorption coefficient alpha in a wavelength range of at least 1 μm to 3.3 μm is approximated by the following formula (1) when K and a are each constant.

α＝nKλ^a…(1)

(wherein, 1.5X 10^-19≤K≤6.0×10^-19、a＝3)

ADVANTAGEOUS EFFECTS OF INVENTION

According to the present invention, the nitride crystal substrate can be heated with good accuracy and good reproducibility.

Drawings

Fig.1 (a) is a schematic plan view showing a nitride crystal substrate 10 of the first embodiment of the present invention, and fig.1 (b) is a schematic cross-sectional view showing the nitride crystal substrate 10 of the first embodiment of the present invention.

Fig. 2 is a diagram illustrating wien's displacement law.

FIG.3 is a graph showing the free electron concentration dependence of the absorption coefficient measured at room temperature (27 ℃) of a GaN crystal produced by the production method of the first embodiment of the invention.

Fig. 4 is a graph showing the intrinsic carrier concentration with respect to the temperature of the GaN crystal.

Fig. 5 (a) is a graph showing the relationship between the absorption coefficient at a wavelength of 2 μm and the free electron concentration in the GaN crystal produced by the production method according to the first embodiment of the present invention, and fig. 5 (b) is a graph comparing the relationship between the absorption coefficient at a wavelength of 2 μm and the free electron concentration.

Fig. 6 is a schematic cross-sectional view showing a semiconductor laminate 1 of the first embodiment of the present invention.

Fig. 7 is a schematic configuration diagram of the vapor phase epitaxy apparatus 200.

Fig.8 (a) is a view showing a case where GaN crystal film 6 is grown thickly on seed substrate 5, and fig.8 (b) is a view showing a case where a plurality of nitride crystal substrates 10 are obtained by slicing GaN crystal film 6 grown thickly.

Fig. 9 (a) is a schematic plan view showing the holding member 300 for mounting the nitride crystal substrate 10 or the semiconductor multilayer structure 1, and fig. 9 (b) is a schematic front view showing the holding member 300 for mounting the nitride crystal substrate 10 or the semiconductor multilayer structure 1.

Fig. 10 (a) and 10 (b) are schematic cross-sectional views showing steps of manufacturing a semiconductor device.

Fig. 11 (a) and 11 (b) are schematic cross-sectional views showing steps of manufacturing a semiconductor device.

Fig. 12 is a schematic cross-sectional view showing a semiconductor device 2 according to a first embodiment of the present invention.

Fig. 13 (a) is a schematic cross-sectional view showing a semiconductor laminate 1 according to a second embodiment of the present invention, and fig. 13 (b) is a schematic cross-sectional view showing a manufacturing process of a semiconductor device.

Fig. 14 (a) and 14 (b) are schematic cross-sectional views showing steps of manufacturing a semiconductor device.

Fig. 15 (a) is a schematic cross-sectional view showing a manufacturing process of a semiconductor device, and fig. 15 (b) is a schematic cross-sectional view showing a semiconductor device 2 according to a second embodiment of the present invention.

Detailed Description

< first embodiment of the present invention >

The first embodiment of the present invention will be explained below with reference to the drawings.

(1) Nitride crystal substrate

The nitride crystal substrate 10 of the present embodiment will be described with reference to fig. 1. Fig.1 (a) is a schematic plan view showing a nitride crystal substrate 10 of the present embodiment, and fig.1 (b) is a schematic cross-sectional view showing the nitride crystal substrate 10 of the present embodiment.

Hereinafter, the main surface of the substrate or the like mainly refers to an upper main surface of the substrate or the like, and may also refer to a surface of the substrate or the like. The back surface of the substrate or the like refers to a lower main surface of the substrate or the like.

As shown in fig.1 (a) and (b), a nitride crystal substrate 10 (hereinafter also referred to as a substrate 10) according to the present embodiment is configured as a disk-shaped substrate used when manufacturing a semiconductor laminate 1 and a semiconductor device 2, which will be described later. The substrate 10 is formed of a single crystal of a group III nitride semiconductor, and in the present embodiment, is formed of a single crystal of gallium nitride (GaN), for example.

The crystal plane direction of the main surface of the substrate 10 is, for example, a (0001) plane (+ c plane, Ga polar plane). The GaN crystal constituting the substrate 10 may have a predetermined off angle with respect to the main surface of the substrate 10. The off angle is an angle formed by a normal direction of the main surface of the substrate 10 and a main axis (c-axis) of a GaN crystal constituting the substrate 10. Specifically, the off angle of the substrate 10 is, for example, 0 ° or more and 1.2 ° or less.

The dislocation density of the main surface of the substrate 10 is, for example, 5 × 10⁶Per cm²The following. If the dislocation density of the main surface of the substrate 10 exceeds 5X 10⁶Per cm²There is a possibility that a local withstand voltage may be lowered in a semiconductor layer 20 formed on the substrate 10, which will be described later. On the other hand, as in the present embodiment, the dislocation density of the main surface of the substrate 10 is set to 5 × 10⁶Per cm²As described below, a local decrease in the withstand voltage can be suppressed in the semiconductor layer 20 formed on the substrate 10.

The main surface of the substrate 10 is an Epi-ready surface (Epi-ready surface), and the surface roughness (arithmetic average roughness Ra) of the main surface of the substrate 10 is, for example, 10nm or less, preferably 5nm or less.

The diameter D of the substrate 10 is not particularly limited, and is, for example, 25mm or more. If the diameter D of the substrate 10 is less than 25mm, the productivity of the semiconductor device 2 described later is likely to be lowered. Therefore, the diameter D of the substrate 10 is preferably 25mm or more. The thickness T of the substrate 10 is, for example, 150 μm or more and 2mm or less. If the thickness T of the substrate 10 is less than 150 μm, the mechanical strength of the substrate 10 may be reduced and it may be difficult to maintain a self-supporting state. Therefore, the thickness T of the substrate 10 is preferably set to 150 μm or more. Here, for example, the diameter D of the substrate 10 is set to 2 inches, and the thickness T of the substrate 10 is set to 400 μm.

The substrate 10 contains, for example, an n-type impurity (donor). Examples of the n-type impurity contained in the substrate 10 include silicon (Si) and germanium (Ge). By doping the substrate 10 with an n-type impurity, free electrons having a predetermined concentration can be generated in the substrate 10.

(concerning absorption coefficient, etc.)

In the present embodiment, the substrate 10 satisfies a predetermined condition in terms of the absorption coefficient in the infrared region. The details will be described below.

In the production of the semiconductor laminate 1 and the semiconductor device 2, for example, as described later, a step of heating the substrate 10 such as a step of epitaxially growing the semiconductor layer 20 on the substrate 10 and a step of activating impurities in the semiconductor layer 20 may be performed. For example, when the substrate 10 is heated by irradiating the substrate 10 with infrared rays, it is important to set the heating conditions based on the absorption coefficient of the substrate 10.

Here, fig. 2 is a diagram illustrating the wien displacement law. In fig. 2, the horizontal axis represents the black body temperature (deg.c), and the vertical axis represents the peak wavelength (μm) of black body radiation. According to the wien's displacement law shown in fig. 2, the peak wavelength of the black body radiation is inversely proportional to the black body temperature. When the peak wavelength is λ (μm) and the temperature is T (° c), λ is 2896/(T + 273). If the radiation from a predetermined heating source in the step of heating the substrate 10 is black body radiation, infrared rays having a peak wavelength corresponding to the heating temperature are irradiated from the heating source to the substrate 10. For example, the peak wavelength λ of infrared rays is 2 μm at a temperature of about 1200 ℃ and 3.3 μm at a temperature of about 600 ℃.

When the substrate 10 is irradiated with infrared rays having such a wavelength, absorption by free electrons (free carrier absorption) occurs in the substrate 10, and the substrate 10 is heated.

Therefore, in the present embodiment, the absorption coefficient in the infrared region of the substrate 10 satisfies the following predetermined condition based on the free carrier absorption of the substrate 10.

FIG.3 is a graph showing the dependence of free electron concentration on the absorption coefficient measured at room temperature (27 ℃ C.) of a GaN crystal produced by the production method of the present embodiment. Fig.3 shows the measurement results of a substrate formed of a GaN crystal produced by doping Si by the production method described later. In FIG.3, the horizontal axis represents the wavelength (nm) and the vertical axis represents the absorption coefficient α (cm) of the GaN crystal^-1). Further, let n be the free electron concentration in the GaN crystal, and the absorption coefficient α of the GaN crystal is plotted for each predetermined free electron concentration n. As shown in fig.3, the GaN crystal produced by the production method described later tends to have an absorption coefficient α that increases (monotonously increases) with the progress toward a long wavelength due to free carrier absorption in a wavelength range of at least 1 μm to 3.3 μm. In addition, it shows a tendency that free carrier absorption in the GaN crystal increases as the free electron concentration n in the GaN crystal increases.

Since the substrate 10 used in the present embodiment is formed of a GaN crystal produced by a production method described later, the substrate 10 of the present embodiment has a small crystal distortion and is in a state of containing almost no impurities other than oxygen (O) and n-type impurities (for example, impurities for compensating for n-type impurities). This shows the free electron concentration dependency of the absorption coefficient as shown in fig. 3. As a result, the substrate 10 of the present embodiment can approximate the absorption coefficient in the infrared region as a function of the free carrier concentration and the wavelength, as described below.

Specifically, let the wavelength be λ (μm) and let the absorption coefficient of the substrate 10 at 27 ℃ be α (cm)^-1) The concentration of free electrons in the substrate 10 is n (cm)^-3) When K and a are constants, the substrate 10 of the present embodiment is at least 1 μm or more and 3.3 μm or less (preferably 1 μm or more and 2.5 μm or less)) The absorption coefficient α in the wavelength range of (a) can be approximated by the following formula (1).

α＝nKλ^a…(1)

(wherein, 1.5X 10^-19≤K≤6.0×10^-19、a＝3)

The phrase "the absorption coefficient α is approximated by the formula (1)" means that the absorption coefficient α is approximated by the formula (1) by the least square method. That is, the above-mentioned specification includes not only a case where the absorption coefficient completely matches the formula (1) (satisfies the formula (1)), but also a case where the formula (1) is satisfied within a predetermined error range. The predetermined error is, for example, within ± 0.1 α, preferably within ± 0.01 α at a wavelength of 2 μm.

The absorption coefficient α in the above wavelength range is considered to satisfy the following expression (1)'.

1.5×10^-19nλ³≤α≤6.0×10^-19nλ³…(1)’

In addition, among the substrates 10 satisfying the above specification, the absorption coefficient α of a high-quality substrate in the above wavelength range is approximated by the following expression (1) "(satisfying the expression (1)").

α＝2.2×10^-19nλ³…(1)”

The specification of "the absorption coefficient α is approximated by the expression (1)" includes not only a case where the absorption coefficient completely matches the expression (1) "(the expression (1)" is satisfied) but also a case where the expression (1) "is satisfied within a predetermined error range, as in the above specification. The predetermined error is, for example, within ± 0.1 α, preferably within ± 0.01 α at a wavelength of 2 μm.

Fig.3 shows an observed value of the absorption coefficient α of a GaN crystal produced by a production method described later as a thin line. Specifically, the thin solid line shows that the free electron concentration n is 1.0 × 10¹⁷cm^-3The measured value of the absorption coefficient α in the case of the above case is shown by a thin broken line that the free electron concentration n is 1.2X 10¹⁸cm^-3The measured value of the absorption coefficient α in the case of time is shown by a thin one-dot chain line that the free electron concentration n is 2.0 × 10¹⁸cm^-3Temporary suctionReceive the measured value of the coefficient alpha. On the other hand, fig.3 shows the function of the above equation (1) as a thick line. Specifically, the thick solid line shows that the free electron concentration n is 1.0 × 10¹⁷cm^-3The function of formula (1) shows, in bold dashed lines, that the free electron concentration n is 1.2X 10¹⁸cm^-3The function of the formula (1) shows that the free electron concentration n is 2.0X 10 in a thick one-dot chain line¹⁸cm^-3A function of equation (1). As shown in fig.3, the measured value of the absorption coefficient α of the GaN crystal produced by the production method described later can be fitted with good accuracy by the function of the formula (1). In the case of fig.3 (Si doping), K is 2.2 × 10^-19In this case, the absorption coefficient α can be approximated to the formula (1) with high accuracy.

As described above, by approximating the absorption coefficient of the substrate 10 by the formula (1), the absorption coefficient of the substrate 10 can be designed with good accuracy based on the concentration n of free electrons in the substrate 10.

In the present embodiment, for example, the absorption coefficient α of the substrate 10 satisfies the following formula (2) in a wavelength range of at least 1 μm or more and 3.3 μm or less.

0.15λ³≤α≤6λ³…(2)

If α is<0.15λ³The substrate 10 cannot sufficiently absorb infrared rays, and the heating of the substrate 10 may become unstable. In contrast, the value of 0.15 λ was used³Not more than α, the substrate 10 can sufficiently absorb infrared rays, and the substrate 10 can be stably heated. On the other hand, if 6 λ³<α corresponds to the concentration of n-type impurities in the substrate 10 exceeding a predetermined value (exceeding 1 × 10), as described later¹⁹at·cm^-3) The crystallinity of the substrate 10 may be reduced. On the other hand, by making α ≦ 6 λ³When the concentration of the n-type impurity in the substrate 10 is equal to or less than a predetermined value, good crystallinity of the substrate 10 can be ensured.

The absorption coefficient α of the substrate 10 preferably satisfies the following expression (2)' or (2) ".

0.15λ³≤α≤3λ³…(2)’

0.15λ³≤α≤1.2λ³…(2)”

This can stably heat the substrate 10 and ensure more favorable crystallinity of the substrate 10.

In the present embodiment, for example, in a wavelength range of at least 1 μm to 3.3 μm, when a difference between a maximum value and a minimum value of the absorption coefficient α in the main surface of the substrate 10 (a difference obtained by subtracting the minimum value from the maximum value; hereinafter, also referred to as "in-plane absorption coefficient difference of the substrate 10") is Δ α, Δ α (cm;) is obtained^-1) Satisfies the formula (3).

Δα≤1.0…(3)

If Δ α >1.0, the heating efficiency by infrared ray irradiation may be uneven in the main surface of the substrate 10. In contrast, by setting Δ α to 1.0 or less, the heating efficiency by infrared ray irradiation can be made uniform in the main surface of the plate 10.

In addition, Δ α preferably satisfies the formula (3)'.

Δα≤0.5…(3)’

By setting Δ α to 0.5 or less, the heating efficiency by infrared ray irradiation can be stabilized and made uniform in the main surface of the substrate 10.

The specifications of the expressions (2) and (3) regarding the absorption coefficients α and Δ α described above may be replaced with specifications at a wavelength of 2 μm, for example.

That is, in the present embodiment, for example, the absorption coefficient of the substrate 10 at a wavelength of 2 μm is 1.2cm^-1Above 48cm^-1The following. The substrate 10 preferably has an absorption coefficient of 1.2cm at a wavelength of 2 μm^-1Above and 24cm^-1Hereinafter, more preferably 1.2cm^-1Above and 9.6cm^-1The following.

In the present embodiment, for example, the difference between the maximum value and the minimum value of the absorption coefficient at a wavelength of 2 μm in the main surface of the substrate 10 is 1.0cm^-1Within, preferably 0.5cm^-1Within.

The upper limit of the in-plane absorption coefficient difference of the substrate 10 is described, but the lower limit of the in-plane absorption coefficient difference of the substrate 10 is preferably zero because the smaller the value is. It is required to say thatThe difference in-plane absorption coefficient of the substrate 10 was set to 0.01cm^-1The effects of the present embodiment can be sufficiently obtained.

Here, the conditions for the absorption coefficient of the substrate 10 are defined at a wavelength of 2 μm corresponding to the peak wavelength of infrared rays at a temperature of about 1200 ℃. However, the effect of satisfying the above conditions in terms of the absorption coefficient of the substrate 10 is not limited to the temperature of about 1200 ℃. This is because the spectrum of the infrared ray irradiated from the heating source has a predetermined wavelength width according to the stefan-boltzmann law, and has a component having a wavelength of 2 μm even at temperatures other than 1200 ℃. Therefore, if the absorption coefficient of the substrate 10 satisfies the above condition at a wavelength of 2 μm corresponding to a temperature of 1200 ℃, the difference between the absorption coefficient of the substrate 10 and the maximum value and the minimum value of the absorption coefficient in the main surface of the substrate 10 is within a predetermined range at a wavelength other than a temperature of 1200 ℃. This enables the substrate 10 to be stably heated even at temperatures other than 1200 ℃, and enables the heating efficiency of the substrate 10 to be uniform over the main surface.

However, FIG.3 above shows the results of measuring the absorption coefficient of a GaN crystal at room temperature (27 ℃ C.). Therefore, when the absorption coefficient of the substrate 10 under a predetermined temperature condition in the step of heating the substrate 10 is taken into consideration, it is necessary to consider how the free carrier absorption of the GaN crystal under the predetermined temperature condition changes from the free carrier absorption of the GaN crystal under the temperature condition of room temperature.

Fig. 4 is a graph showing the intrinsic carrier concentration with respect to the temperature of the GaN crystal. As shown in fig. 4, the GaN crystal constituting the substrate 10 has an intrinsic carrier concentration n thermally excited between bands (between the valence band and the conduction band) as the temperature increases_iThe concentration of (c) increases. However, even if the temperature of the GaN crystal is around 1300 ℃, the intrinsic carrier concentration n is thermally excited between bands of the GaN crystal_iIs also less than 7X 10¹⁵cm^-3Sufficiently lower than the concentration of free carriers generated in the GaN crystal by doping with n-type impurities (e.g., 1X 10¹⁷cm^-3). That is, it can be said that the free carrier concentration of the GaN crystal is at a free carrier under the temperature condition that the temperature of the GaN crystal is lower than 1300 ℃The concentration of the photons is determined by the doping of the n-type impurity, in the so-called extrinsic region.

That is, in the present embodiment, the concentration of intrinsic carriers thermally excited between bands of the substrate 10 under temperature conditions (room temperature (27 ℃) to 1250 ℃) of at least the manufacturing steps of the semiconductor laminate 1 and the semiconductor device 2 described later is lower than the concentration of free electrons generated in the substrate 10 by doping an n-type impurity under temperature conditions of room temperature (for example, 1/10 times or less). From this, it is considered that the free carrier concentration of the substrate 10 under the predetermined temperature condition in the step of heating the substrate 10 is substantially equal to the free carrier concentration of the substrate 10 under the temperature condition of room temperature, and it is considered that the free carrier absorption under the predetermined temperature condition is substantially equal to the free carrier absorption under the room temperature. That is, as described above, when the absorption coefficient in the infrared region of the substrate 10 satisfies the predetermined condition at room temperature, it is considered that the absorption coefficient in the infrared region of the substrate 10 substantially maintains the predetermined condition even under the predetermined temperature condition.

In addition, in the substrate 10 of the present embodiment, since the absorption coefficient α in the wavelength range of at least 1 μm or more and 3.3 μm or less can be approximated by the formula (1), the absorption coefficient α of the substrate 10 and the free electron concentration n have a substantially proportional relationship at the predetermined wavelength λ.

Fig. 5 (a) is a graph showing the relationship between the absorption coefficient at a wavelength of 2 μm and the free electron concentration in the GaN crystal produced by the production method of the present embodiment. In fig. 5 (a), the lower solid line (α ═ 1.2 × 10)^-18n) is defined as K ═ 1.5X 10^-19And λ is 2.0, and the upper solid line (α is 4.8 × 10)^-18n) is such that K is 6.0X 10^-19And λ is 2.0 in the formula (1). In addition, (a) of fig. 5 shows not only GaN crystals doped with Si but also GaN crystals doped with Ge. The results of the absorption coefficient determination by transmission determination and the absorption coefficient determination by ellipsometry are also shown. As shown in FIG. 5 (a), when the wavelength λ is 2.0 μm, the absorption coefficient α and the free form of the GaN crystal produced by the production method described later are shownThe electron concentration n has a substantially proportional relationship. The measured value of the absorption coefficient α of a GaN crystal produced by the production method described later may be 1.5 × 10^-19≤K≤6.0×10^-19Is fitted with good accuracy by the function of equation (1). Since a GaN crystal produced by a production method described later is high-quality, the measured value of the absorption coefficient α can be determined by using K of 2.2 × 10 in many cases^-19Function of equation (1), i.e., α is 1.8 × 10^-18n are fitted with good accuracy.

In the present embodiment, the free electron concentration n in the substrate 10 satisfies the following predetermined condition based on the fact that the absorption coefficient α of the substrate 10 is proportional to the free electron concentration n.

In the present embodiment, the free electron concentration n in the substrate 10 is, for example, 1.0 × 10¹⁸cm^-3Above and 1.0X 10¹⁹cm^-3The following. Thus, according to the formula (1), the absorption coefficient of the substrate 10 at a wavelength of 2 μm can be set to 1.2cm^-1Above 48cm^-1The following. The free electron concentration n in the substrate 10 is preferably 1.0 × 10¹⁸cm^-3Above and 5.0X 10¹⁸cm^-3Hereinafter, more preferably 1.0 × 10¹⁸cm^-3Above and 2.0X 10¹⁸cm^-3The following. Thus, the substrate 10 can have an absorption coefficient of preferably 1.2cm at a wavelength of 2 μm^-1Above and 24cm^-1Less than, more preferably 1.2cm^-1Above and 9.6cm^-1The following.

Further, as described above, when the difference between the maximum value and the minimum value of the absorption coefficient α in the main surface of the substrate 10 is Δ α, the difference between the maximum value and the minimum value of the free electron concentration n in the main surface of the substrate 10 is Δ n, and the wavelength λ is 2.0 μm, the following formula (4) can be obtained by differentiating the formula (1).

Δα＝8KΔn…(4)

In the present embodiment, for example, the difference Δ n between the maximum value and the minimum value of the free electron concentration n in the main surface of the substrate 10 is 8.3 × 10¹⁷cm^-3Up to, preferably 4.2X 10¹⁷cm^-3Within. Thus, according to the formula (4), the difference Δ α between the maximum value and the minimum value of the absorption coefficient at a wavelength of 2 μm can be set to 1.0cm^-1Within, preferably 0.5cm^-1Within.

The upper limit of Δ n is described, but the lower limit of Δ n is preferably zero as it is better. Note that even if Δ n is 8.3 × 10¹⁵cm^-3The effects of the present embodiment can be sufficiently obtained.

In the present embodiment, the free electron concentration n in the substrate 10 is equal to the concentration of the n-type impurity in the substrate 10, and the concentration of the n-type impurity in the substrate 10 satisfies the following predetermined conditions.

In the present embodiment, the concentration of the n-type impurity in the substrate 10 is, for example, 1.0 × 10¹⁸at·cm^-3Above and 1.0X 10¹⁹at·cm^-3The following. Thus, the free electron concentration n in the substrate 10 can be set to 1.0 × 10¹⁸cm^-3Above and 1.0X 10¹⁹cm^-3The following. The concentration of the n-type impurity in the substrate 10 is preferably 1.0 × 10¹⁸at·cm^-3Above and 5.0X 10¹⁸at·cm^-3Hereinafter, more preferably 1.0 × 10¹⁸at·cm^-3Above and 2.0X 10¹⁸at·cm^-3The following. Thus, the free electron concentration n in the substrate 10 can be preferably set to 1.0 × 10¹⁸cm^-3Above and 5.0X 10¹⁸cm^-3The following, more preferably 1.0X 10¹⁸cm^-3Above and 2.0X 10¹⁸cm^-3The following.

In the present embodiment, for example, the difference between the maximum value and the minimum value of the concentration of the n-type impurity in the main surface of the substrate 10 (hereinafter, also referred to as the in-plane concentration difference of the n-type impurity) is 8.3 × 10¹⁷at·cm^-3Up to, preferably 4.2X 10¹⁷at·cm^-3Within. Thus, the difference Δ n between the maximum value and the minimum value of the free electron concentration n in the main surface of the substrate 10 and the in-plane concentration difference of the n-type impurity can be made equal to 8.3 × 10¹⁷cm^-3Up to, preferably 4.2X 10¹⁷cm^-3Within.

The upper limit of the in-plane concentration difference of the n-type impurity is described, but the lower limit of the in-plane concentration difference of the n-type impurity is preferably zero as it is smaller. Note that even if the in-plane concentration difference of the n-type impurity is 8.3 × 10¹⁵at·cm^-3The effects of the present embodiment can be sufficiently obtained.

Further, in the present embodiment, the concentration of each element in the substrate 10 satisfies the following predetermined condition.

In the present embodiment, the concentration of O, which is difficult to control the addition amount, among Si, Ge, and O used as n-type impurities is as low as possible, and the concentration of n-type impurities in the substrate 10 is determined by the total concentration of Si and Ge, which is easy to control the addition amount.

That is, the concentration of O in the substrate 10 is negligibly low with respect to the total concentration of Si and Ge in the substrate 10, for example, 1/10 or less. Specifically, for example, the concentration of O in the substrate 10 is less than 1X 10¹⁷at·cm^-3And the total concentration of Si and Ge in the substrate 10 is 1X 10¹⁸at·cm^-3Above and 1.0X 10¹⁹at·cm^-3The following. Thereby, the concentration of the n-type impurity in the substrate 10 can be controlled by controlling the total concentration of the added amounts of Si and Ge relatively easily. As a result, the free electron concentration n in the substrate 10 can be controlled with good accuracy so as to be equal to the total concentration of Si and Ge in the substrate 10, and the difference Δ n between the maximum value and the minimum value of the concentration of free electrons in the main surface of the substrate 10 can be controlled with good accuracy so as to satisfy the predetermined condition.

In the present embodiment, the concentration of the impurity other than the n-type impurity in the substrate 10 is set to be inconsiderable, for example, 1/10 or less, with respect to the concentration of the n-type impurity (i.e., the total concentration of Si and Ge) in the substrate 10. Specifically, for example, the concentration of impurities other than n-type impurities in the substrate 10 is lower than 1 × 10¹⁷at·cm^-3. This can reduce the barrier to the generation of free electrons from the n-type impurity. As a result, the free electron concentration n in the substrate 10 can be controlled with good accuracy so as to be equal to the concentration of the n-type impurity in the substrate 10, and the free electron concentration n in the main surface of the substrate 10 can be controlled with good accuracyThe difference Δ n between the maximum value and the minimum value of the concentration is such that it satisfies a predetermined condition.

The present inventors have confirmed that the concentrations of the respective elements in the substrate 10 can be stably controlled so as to satisfy the above-described conditions by adopting the manufacturing method described later.

From the manufacturing method described later, it is understood that the respective concentrations of O and carbon (C) in the substrate 10 can be reduced to less than 5 × 10¹⁵at·cm^-3Further, the respective concentrations of iron (Fe), chromium (Cr), boron (B), and the like in the substrate 10 may be reduced to less than 1 × 10¹⁵at·cm^-3. Further, according to this method, it is found that elements other than these elements can be reduced to a concentration lower than the lower limit of detection in measurement by Secondary Ion Mass Spectrometry (SIMS).

Further, in the substrate 10 manufactured by the manufacturing method described later in this embodiment, since the absorption coefficient by free carrier absorption is smaller than that of the conventional substrate, it is estimated that the mobility (μ) of the substrate 10 of this embodiment is higher than that of the conventional substrate. Thus, even when the free electron concentration in the substrate 10 of the present embodiment is equal to that in the conventional substrate, the resistivity (ρ 1/en μ) of the substrate 10 of the present embodiment is lower than that of the conventional substrate. Specifically, the free electron concentration n in the substrate 10 is 1.0 × 10¹⁸cm^-3Above and 1.0X 10¹⁹cm^-3In the following case, the resistivity of the substrate 10 is, for example, 2.2m Ω · cm or more and 17.4m Ω · cm or less.

(2) Semiconductor laminate

Next, a semiconductor laminate (crystal laminate) 1 of the present embodiment will be described with reference to fig. 6. Fig. 6 is a schematic cross-sectional view showing the semiconductor laminate 1 of the present embodiment.

First, an outline of the semiconductor laminate 1 of the present embodiment will be described.

As shown in fig. 6, the semiconductor laminate 1 of the present embodiment is configured as a substrate-shaped intermediate used in the production of a semiconductor device 2 described later. The semiconductor laminate 1 includes, for example, a substrate 10 and a semiconductor layer (semiconductor laminate structure, semiconductor laminate, or epitaxial growth layer) 20.

The substrate 10 is the nitride crystal substrate, and the absorption coefficient of the substrate 10 in the infrared region satisfies the above condition.

The semiconductor layer 20 is formed by epitaxial growth on the main surface of the substrate 10. The semiconductor layer 20 is formed of a single crystal of a group III nitride semiconductor, and in the present embodiment, for example, as in the case of the substrate 10, it is formed of a single crystal of GaN.

In the present embodiment, the surface (main surface) of the semiconductor layer 20 satisfies a predetermined condition in terms of reflectance in the infrared region. Specifically, the reflectance of the surface of the semiconductor layer 20 is 5% to 30% in a wavelength range of at least 1 μm to 3.3 μm. This enables infrared rays to sufficiently reach the substrate 10 in the step of heating the substrate 10 (semiconductor laminate 1). As a result, the substrate 10 can be stably heated.

The surface roughness (arithmetic average roughness Ra) of the surface of the semiconductor layer 20 is, for example, 1nm or more and 30nm or less. Thereby, the reflectance of the surface of the semiconductor layer 20 can be set to 5% or more and 30% or less in a wavelength range of at least 1 μm or more and 3.3 μm or less.

Next, a specific configuration of the semiconductor laminate 1 of the present embodiment will be described.

The semiconductor laminate 1 of the present embodiment is configured as an intermediate used in manufacturing a semiconductor device 2 that is a high-voltage pn junction diode, for example. The semiconductor layer 20 in the semiconductor laminate 1 has a laminated structure, for example. Specifically, the semiconductor layer 20 includes, for example, a base n-type semiconductor layer 21, a drift layer 22, a first p-type semiconductor layer 23, and a second p-type semiconductor layer 24.

(base n-type semiconductor layer)

The base n-type semiconductor layer 21 is provided in contact with the main surface of the substrate 10 as a buffer layer for stably epitaxially growing the drift layer 22 while maintaining the crystallinity of the substrate 10. The underlying n-type semiconductor layer 12 is an n-type GaN layer containing n-type impurities. Examples of the n-type impurity contained in the base n-type semiconductor layer 12 includeAs with the substrate 10, Si and Ge can be cited. The concentration of n-type impurities in the base n-type semiconductor layer 12 is substantially equal to that of the substrate 10, and is, for example, 1.0 × 10¹⁸at·cm^-3Above and 1.0X 10¹⁹at·cm^-3The following.

The thickness of the base n-type semiconductor layer 21 is smaller than that of the drift layer 22, and is, for example, 0.1 μm or more and 3 μm or less.

(drift layer)

The drift layer 22 is provided on the base n-type semiconductor layer 21 and is configured as an n-type GaN layer containing a low concentration of n-type impurities. Examples of the n-type impurity in the drift layer 22 include Si and Ge, as in the case of the n-type impurity in the base n-type semiconductor layer 21.

The n-type impurity concentration in the drift layer 22 is lower than the respective n-type impurity concentrations of the substrate 10 and the base n-type semiconductor layer 21, and is, for example, 1.0 × 10¹⁵at·cm^-3Above and 5.0X 10¹⁶at·cm^-3The following. By making the n-type impurity concentration of the drift layer 22 1.0X 10¹⁵at·cm^-3As described above, the on-resistance of the semiconductor device 2 can be reduced. On the other hand, the n-type impurity concentration of the drift layer 22 is set to 5.0 × 10¹⁶at·cm^-3Hereinafter, a predetermined withstand voltage of the semiconductor device 2 can be ensured.

In order to increase the withstand voltage of the semiconductor device 2, the drift layer 22 is provided thicker than the base n-type semiconductor layer 21, for example. Specifically, the thickness of the drift layer 22 is, for example, 3 μm or more and 40 μm or less. By setting the thickness of the drift layer 22 to 3 μm or more, a predetermined withstand voltage of the semiconductor device 2 can be ensured. On the other hand, by setting the thickness of the drift layer 22 to 40 μm or less, the on-resistance of the semiconductor device 2 can be reduced.

(first p-type semiconductor layer)

The first p-type semiconductor layer 23 is provided on the drift layer 22 and is configured as a p-type GaN layer containing a p-type impurity (acceptor). As the p-type impurity in the first p-type semiconductor layer 23, for example, magnesium (Mg) can be cited. The p-type impurity concentration in the first p-type semiconductor layer 23 is, for example, 1.0 × 10¹⁷at·cm^-3Above and 2.0X 10¹⁹at·cm^-3The following.

The thickness of the first p-type semiconductor layer 23 is thinner than the thickness of the drift layer 22, and is, for example, 100nm to 500 nm.

(second p-type semiconductor layer)

The second p-type semiconductor layer 24 is provided on the first p-type semiconductor layer 23 and is configured as a p-type GaN layer containing a high concentration of p-type impurities. The p-type impurity in the second p-type semiconductor layer 24 includes, for example, Mg, as in the first p-type semiconductor layer 23. In addition, the p-type impurity concentration in the second p-type semiconductor layer 24 is higher than that in the first p-type semiconductor layer 23, and is, for example, 5.0 × 10¹⁹at·cm^-3Above and 2.0X 10²⁰at·cm^-3The following. By setting the p-type impurity concentration in the second p-type semiconductor layer 24 within the above range, the contact resistance between the second p-type semiconductor layer 24 and a p-type electrode described later can be reduced.

The thickness of the second p-type semiconductor layer 24 is thinner than the thickness of the first p-type semiconductor layer 23, and is, for example, 10nm or more and 50nm or less.

(3) Method for manufacturing semiconductor laminate and method for manufacturing semiconductor device

Next, a method for manufacturing the semiconductor laminate 1 and a method for manufacturing the semiconductor device 2 according to the present embodiment will be described with reference to fig. 6 to 12. Fig. 7 is a schematic configuration diagram of the vapor phase epitaxy apparatus 200. Fig.8 (a) is a view showing a case where GaN crystal film 6 is grown thickly on seed substrate 5, and fig.8 (b) is a view showing a case where a plurality of nitride crystal substrates 10 are obtained by slicing GaN crystal film 6 grown thickly. Fig. 9 (a) is a schematic plan view showing the holding member 300 for mounting the nitride crystal substrate 10 or the semiconductor multilayer structure 1, and fig. 9 (b) is a schematic front view showing the holding member 300 for mounting the nitride crystal substrate 10 or the semiconductor multilayer structure 1. Fig. 10 (a) and (b), and fig. 11 (a) and (b) are schematic cross-sectional views showing steps of manufacturing a semiconductor device. Fig. 12 is a schematic cross-sectional view illustrating the semiconductor device 2 of the present embodiment. Hereinafter, the step will be abbreviated as S.

(S110: substrate preparation Process)

First, a substrate preparation step S110 for preparing the substrate 10 is performed. The substrate preparation step S110 of the present embodiment includes, for example, a substrate preparation step S112, a measurement step S114, and a determination step S116.

(S112: substrate production Process)

The substrate 10 was produced using a hydride vapor phase epitaxy apparatus (HVPE apparatus) 200 shown below.

(construction of HVPE apparatus)

The configuration of the HVPE apparatus (vapor phase epitaxy apparatus) 200 used for manufacturing the substrate 10 will be described in detail with reference to fig. 7.

The HVPE apparatus 200 includes a reaction vessel (airtight container) 203 in which a film forming chamber (reaction chamber) 201 is formed. An inner lid 204 is provided in the film forming chamber 201, and a base 208 serving as a base for disposing a seed substrate (hereinafter also referred to as seed substrate) 5 is provided at a position surrounded by the inner lid 204. The base 208 is connected to a rotary shaft 215 of the rotary mechanism 216, and is configured to be rotatable in accordance with the drive of the rotary mechanism 216.

A gas supply pipe 232a for supplying hydrogen chloride (HCl) gas into the gas generator 233a and ammonia (NH) gas into the inner lid 204 are connected to one end of the reaction container 203₃) A gas supply pipe 232b for supplying a dopant gas described later into the inner lid 204, a gas supply pipe 232c for supplying nitrogen (N) as a purge gas into the inner lid 204₂) Gas and hydrogen (H)₂) Gas mixture (N)₂/H₂Gas) and N for supplying a purge gas into the film forming chamber 201₂And a gas supply pipe 232e for gas. The gas supply pipes 232a to 232e are provided with flow rate controllers 241a to 241e and valves 243a to 243e, respectively, in this order from the upstream side. A gas generator 233a for containing a Ga melt as a raw material is provided downstream of the gas supply pipe 232 a. The gas generator 233a is provided with a nozzle 249a for supplying gallium chloride (GaCl) gas generated by the reaction of the HCl gas and the Ga melt to the seed substrate 5 and the like disposed on the susceptor 208. Gas supply pipes 232b and 232c are connected downstream thereof respectivelyAnd nozzles 249b and 249c for supplying the various gases supplied from these gas supply pipes to the seed substrate 5 and the like disposed on the susceptor 208. The nozzles 249a to 249c are arranged so that the gas flows in a direction intersecting the surface of the susceptor 208. The doping gas supplied from the nozzle 249c is a doping source gas and N₂/H₂A mixed gas of carrier gases such as gas. The dopant gas may be circulated together with the HCl gas for the purpose of suppressing thermal decomposition of the halide gas of the dopant material. As a doping source gas constituting the doping gas, for example, when doping silicon (Si), dichlorosilane (SiH) may be used₂Cl₂) Gas or Silane (SiH)₄) When the gas is germanium (Ge) -doped, it is considered to use tetrachlorogermane (GeCl)₄) Gas, dichlorogermane (GeH)₂Cl₂) Gases or germanes (GeH)₄) Gases, but are not necessarily limited to them.

An exhaust pipe 230 for exhausting the inside of the film forming chamber 201 is provided at the other end of the reaction vessel 203. A pump (or blower) 231 is provided in the exhaust pipe 230. Zone heaters 207a and 207b for heating the inside of the gas generator 233a and the seed substrate 5 on the susceptor 208 to a desired temperature by zone are provided on the outer periphery of the reaction vessel 203. In addition, a temperature sensor (not shown) for measuring the temperature in the film forming chamber 201 is provided in the reaction vessel 203.

The components of the HVPE apparatus 200, particularly the components for forming the gas flows of the various gases, may be configured as follows, for example, so as to allow crystal growth with a low impurity concentration as described later.

Specifically, as shown in fig. 7 so as to be distinguishable from the type of hatching, it is preferable to use a member made of a material that does not contain quartz and does not contain boron as a member constituting a high-temperature region in the reaction vessel 203, the high-temperature region being heated to a crystal growth temperature (for example, 1000 ℃ or higher) by irradiation of the zone heaters 207a and 207b and being brought into contact with the gas supplied to the seed substrate 5. Specifically, as the member constituting the high temperature region, for example, a member formed of silicon carbide (SiC) coated graphite is preferably used. On the other hand, in the lower temperature region, a high purity quartz member is preferably used. That is, each member is configured by using SiC-coated graphite instead of high-purity quartz in a high-temperature region which is brought into contact with HCl gas or the like and has a relatively high temperature. Specifically, the inner lid 204, the base 208, the rotary shaft 215, the gas generator 233a, the nozzles 249a to 249c, and the like are made of SiC-coated graphite. Since only quartz is used as the core tube constituting the reaction vessel 203, an inner lid 204 surrounding the susceptor 208, the gas generator 233a, and the like is provided in the film forming chamber 201. The wall portions at both ends of the reaction vessel 203, the exhaust pipe 230, and the like may be formed using a metal material such as stainless steel.

For example, according to "Polyakov et al.J.appl.Phys.115,183706 (2014)", it is disclosed that growth of a GaN crystal with a low impurity concentration can be achieved by growth at 950 ℃. However, such low-temperature growth causes a decrease in the quality of the obtained crystal, and a crystal excellent in thermophysical properties, electrical characteristics, and the like cannot be obtained.

In contrast, according to the HVPE apparatus 200 of the present embodiment, each member is configured using SiC-coated graphite in a high-temperature region that is brought into contact with HCl gas or the like at a relatively high temperature. Thus, even in a temperature region suitable for growth of GaN crystal, such as 1050 ℃ or higher, supply of impurities such as Si, O, C, Fe, Cr, and Ni to the crystal growth portion due to quartz, stainless steel, and the like can be blocked. As a result, a GaN crystal having high purity and exhibiting excellent characteristics in terms of thermal and electrical properties can be grown.

Each component of the HVPE apparatus 200 is configured as follows: the controller 280 configured as a computer is connected to the control unit, and the processing procedure and the processing condition described later are controlled by a program executed on the controller 280.

(Process for producing substrate 10)

Next, a series of processes from the time when GaN single crystal is epitaxially grown on the seed substrate 5 using the HVPE apparatus 200 and then the grown crystal is sliced to obtain the substrate 10 will be described in detail with reference to fig. 7. In the following description, operations of respective parts constituting the HVPE apparatus 200 are controlled by the controller 280.

The manufacturing process of the substrate 10 includes a loading step, a crystal growth step, a carrying-out step, and a slicing step.

(carrying-in step)

Specifically, first, the furnace mouth of the reaction vessel 203 is opened, and the seed substrate 5 is placed on the susceptor 208. The seed substrate 5 placed on the susceptor 208 serves as a base (seed) for manufacturing a substrate 10 described later, and is a plate-like object formed of a GaN single crystal, which is an example of a nitride semiconductor.

When the seed substrate 5 is placed on the susceptor 208, the main surface (crystal growth surface, basal surface) of the seed substrate 5 placed on the susceptor 208, that is, the side facing the nozzles 249a to 249C is made to be the + C surface (Ga polarity surface) which is the (0001) surface of the GaN crystal.

(Crystal growth step)

In this step, after the seed substrate 5 is carried into the film forming chamber 201, the furnace opening is closed, and the supply of H into the film forming chamber 201 is started while heating and exhausting the inside of the film forming chamber 201₂Gas or H₂Gas and N₂A gas. Then, when the inside of the film forming chamber 201 reaches a desired process temperature and process pressure and the atmosphere in the film forming chamber 201 becomes a desired atmosphere, the supply of HCl gas and NH gas from the gas supply pipes 232a and 232b is started₃Gas, respectively supplying GaCl gas and NH gas to the surface of the seed substrate 5₃A gas.

As a result, as shown in the cross-sectional view of fig.8 (a), a GaN crystal 6 is formed by epitaxially growing a GaN crystal on the surface of the seed substrate 5 in the c-axis direction. At this time, SiH is supplied₂Cl₂As the gas, Si as an n-type impurity may be added to GaN crystal 6.

In this step, in order to prevent thermal decomposition of the GaN crystal constituting the seed substrate 5, it is preferable to start supply of NH into the film forming chamber 201 at or before the time when the temperature of the seed substrate 5 reaches 500 ℃₃A gas. In order to improve the in-plane film thickness uniformity of GaN crystal 6, it is preferable that the susceptor 208 be rotated in this stepAnd (5) implementing.

In this step, the temperature of the zone heaters 207a and 207b is preferably set to a temperature of, for example, 700 to 900 ℃ in the heater 207a for heating the upstream portion of the film forming chamber 201 including the gas generator 233a, and to a temperature of, for example, 1000 to 1200 ℃ in the heater 207b for heating the downstream portion of the film forming chamber 201 including the susceptor 208. Thus, the base 208 is adjusted to a predetermined temperature of 1000 to 1200 ℃. In this step, the internal heater (not shown) may be used in a closed state, but temperature control using the internal heater may be performed as long as the temperature of the susceptor 208 is in the range of 1000 to 1200 ℃.

Other processing conditions in this step are exemplified below.

Treatment pressure: 0.5 to 2 atmospheres

Partial pressure of GaCl gas: 0.1 to 20kPa

NH₃Partial pressure of gas/partial pressure of GaCl gas: 1 to 100

H₂Partial pressure of gas/partial pressure of GaCl gas: 0 to 100

SiH₂Cl₂Partial pressure of gas: 2.5X 10^-5～1.3×10^-3kPa

In addition, GaCl gas and NH were supplied to the surface of the seed substrate 5₃In the case of gas, N as a carrier gas may be added from the gas supply pipes 232a to 232b, respectively₂A gas. By adding N₂By adjusting the blowing flow rate of the gas supplied from the nozzles 249a to 249b, the distribution of the amount of the raw material gas supplied to the surface of the seed substrate 5 and the like can be appropriately controlled, and a uniform growth rate distribution can be achieved over the entire surface area. Instead of N, a rare gas such as Ar gas or He gas may be added₂A gas.

(carrying out step)

After GaN crystal 6 of a desired thickness is grown on seed substrate 5, NH is supplied into film forming chamber 201₃Gas, N₂While the gas is being exhausted from the film forming chamber 201, the supply of HCl gas to the gas generator 233a is stoppedAnd supplying H into the film forming chamber 201₂Gas, based on heating of zone heaters 207a, 207 b. Then, after the temperature in the film forming chamber 201 is lowered to 500 ℃ or lower, the supply of NH is stopped₃Gas for replacing the atmosphere in the film forming chamber 201 with N₂Gas, returning it to atmospheric pressure. Then, the temperature in the film forming chamber 201 is lowered to, for example, 200 ℃ or lower, that is, a temperature at which the GaN ingot (seed substrate 5 having GaN crystals 6 formed on the main surface) can be carried out from the reaction vessel 203. Then, the ingot is carried out of the film forming chamber 201 to the outside.

(slicing step)

Then, by slicing the ingot taken out, for example, in a direction parallel to the growth plane of GaN crystal 6, as shown in fig.8 (b), 1 or more substrates 10 can be obtained. The various compositions, various physical properties, and the like of the substrate 10 are as described above, and therefore, the description thereof is omitted. The slicing process can be performed using, for example, a wire saw, an electric discharge machine, or the like. The thickness of the substrate 10 is 250 μm or more, for example, about 400 μm. Then, the surface (+ c-surface) of the substrate 10 is polished to a predetermined degree, thereby forming a mirror surface ready for use (Epi-ready) after opening the case. The back surface (-c surface) of the substrate 10 is a polished surface or a mirror surface.

(S114: measuring step)

After the plurality of substrates 10 are produced, the plurality of substrates 10 are irradiated with light, and the absorption coefficient in the infrared region is measured for each of the plurality of substrates 10. At this time, the absorption coefficient in the infrared region is measured at least at 2 points or more in the main surface of the substrate 10. In this case, the measurement site in the main surface of the substrate 10 is, for example, 2 points or more and 10 points or less, and preferably 3 points or more and 5 points or less. If the measurement site is only 1 point, the difference in absorption coefficient in the main surface of the substrate 10 cannot be obtained. On the other hand, if the measurement site exceeds 10 points, the time for the measurement step becomes long, and the productivity of the substrate 10 may be lowered.

It is preferable to measure the absorption coefficient at least at the center of the main surface of the substrate 10 and at a position radially distant from the center of the main surface of the substrate 10 by a predetermined distance. Here, in the substrate preparation step S112, since the GaN crystal 6 is grown while rotating the seed substrate 5, the absorption coefficient of the substrate 10 tends to be equal concentrically with respect to the center of the main surface of the substrate 10. Therefore, by measuring the absorption coefficient at least at the center of the main surface of the substrate 10 and at a position radially distant from the center of the main surface of the substrate 10 by a predetermined distance, the distribution of the absorption coefficient in the main surface of the substrate 10 can be accurately grasped (predicted). The measurement position other than the center of the main surface of the substrate 10 is, for example, a position separated from the center of the main surface of the substrate 10 in the radial direction by a distance of 20% to 80% of the radius of the substrate 10.

(S116: determination step)

Next, based on the measured absorption coefficient of the substrate 10, it is determined whether or not the absorption coefficient in the infrared region of the substrate 10 satisfies a predetermined condition. Specifically, for example, it is determined whether or not the absorption coefficient α in the wavelength range of at least 1 μm or more and 3.3 μm or less can be approximated by the above formula (1). Further, for example, it is judged whether or not the absorption coefficient of the substrate 10 at a wavelength of 2 μm is 1.2cm^-1Above 48cm^-1And whether or not the difference between the maximum value and the minimum value of the absorption coefficient at a wavelength of 2 μm in the main surface of the substrate 10 is 1.0cm^-1Within. In this case, the above determination is performed for each of the plurality of substrates 10 obtained in the substrate production step S112.

Then, based on the determination result, the substrate 10 satisfying the above condition in the absorption coefficient in the infrared region among the plurality of substrates 10 is selected as a good product, and the substrate 10 not satisfying the above condition is excluded. This makes it possible to select as an excellent product a substrate 10 that can be heated with good accuracy and good reproducibility in a step of heating the substrate 10 described later, and to select as an excellent product a substrate 10 that can make uniform the heating efficiency in a step of heating the substrate 10 described later.

It is also possible to determine whether or not the absorption coefficient of the substrate 10 at a wavelength of 2 μm is 1.2cm^-1Above and 24cm^-1And whether or not the difference between the maximum value and the minimum value of the absorption coefficient at a wavelength of 2 μm in the main surface of the substrate 10 is 0.5cm^-1And selecting one of the plurality of substrates 10 in the infrared regionThe substrate 10 satisfying the above conditions in terms of absorption coefficient is the most preferable.

As described above, the substrate 10 of the present embodiment is manufactured as shown in fig. 1.

The semiconductor laminate 1 and the semiconductor device 2 are manufactured by using the substrate 10 selected as an excellent product (or an optimum product). In the following steps, as at least 1 step, a step of heating the substrate 10 by irradiating at least infrared rays to the substrate 10 is performed. In the present embodiment, examples of the step of heating the substrate 10 include a semiconductor layer forming step S120, an activation annealing step S130, a protective film forming step S143, an ohmic alloy step S146, and the like.

(S120: semiconductor layer Forming Process)

Next, the substrate 10 is irradiated with at least infrared light by, for example, a Metal Organic Vapor Phase Epitaxy (MOVPE) method, thereby epitaxially growing the semiconductor layer 20 on the substrate 10.

In this case, since the substrate 10 satisfies the above-described condition in terms of the absorption coefficient in the infrared region, the substrate 10 can be stably heated by irradiating the substrate 10 with infrared rays, and the temperature of the substrate 10 can be controlled with good accuracy. In addition, the heating efficiency by infrared ray irradiation can be made uniform in the main surface of the substrate 10. As a result, the crystallinity, thickness, various impurity concentrations, and the like of the semiconductor layer 20 can be controlled with good accuracy so as to be uniform in the main surface of the substrate 10.

Specifically, the semiconductor layer 20 of this embodiment mode is formed, for example, in the following steps.

First, the substrate 10 is carried into a processing chamber of a MOVPE apparatus (not shown).

At this time, as shown in fig. 9 (a) and (b), the substrate 10 is placed on the holding member 300. The holding member 300 has, for example, 3 convex portions 300p, and is configured to hold the substrate 10 by the 3 convex portions 300 p. Thus, when heating the substrate 10, the substrate 10 can be heated mainly by irradiating infrared rays to the substrate 10, not by heat transfer from the holding member 300 to the substrate 10. Here, in the case where the substrate 10 is heated by heat transfer from the plate-shaped holding member (or in the case where the heating is performed in combination with the heat transfer), it is difficult to uniformly heat the substrate 10 over the entire surface thereof, depending on the state of the back surface of the substrate 10 and the state of the front surface of the holding member. In addition, warpage may occur in the substrate 10 as the substrate 10 is heated, and the degree of contact between the substrate 10 and the holding member may gradually change. Therefore, the heating condition of the substrate 10 may not be uniform over the entire surface. In contrast, in the present embodiment, by using the holding member 300 of the above-described type, the substrate 10 is heated mainly by irradiating the substrate 10 with infrared rays, so that such a problem can be solved, and the substrate 10 can be stably and uniformly heated in the main surface.

In order to reduce the influence of heat transfer, the shape and size of the projection 300p are preferably selected so that the contact area between the projection 300p and the substrate 10 is 5% or less, preferably 3% or less of the supported surface of the substrate 10.

After the substrate 10 is placed on the holding member 300, hydrogen gas and NH are supplied into the processing chamber of the MOVPE apparatus₃Gas (further N)₂Gas), the substrate 10 is heated by irradiating the substrate 10 with infrared rays from a predetermined heating source (e.g., a lamp heater). After the temperature of the substrate 10 reaches a predetermined growth temperature (for example, 1000 ℃ to 1100 ℃), for example, Trimethylgallium (TMG) as a group III organometallic raw material and NH as a group V raw material are supplied to the substrate 10₃A gas. At the same time, SiH as an n-type impurity material is supplied to the substrate 10, for example₄A gas. Thereby, the underlying n-type semiconductor layer 21 as an n-type GaN layer is epitaxially grown on the substrate 10.

Next, drift layer 22, which is an n-type GaN layer containing an n-type impurity at a lower concentration than base n-type semiconductor layer 21, is epitaxially grown on base n-type semiconductor layer 21.

Next, the first p-type semiconductor layer 23 as a p-type GaN layer is epitaxially grown on the drift layer 22. At this time, instead of the n-type impurity material, for example, biscyclopentadienyl magnesium (Cp) as a p-type impurity material is supplied to the substrate 10₂Mg)。

Next, the second p-type semiconductor layer 24, which is a p-type GaN layer containing a p-type impurity at a higher concentration than the first p-type semiconductor layer 23, is epitaxially grown on the first p-type semiconductor layer 23.

After the growth of the second p-type semiconductor layer 24 is completed, the supply of the group III organometallic raw material and the heating of the substrate 10 are stopped. After the temperature of the substrate 10 reaches 500 ℃ or lower, the supply of the group V material is stopped. Then, the atmosphere in the processing chamber of the MOVPE device is replaced by N₂The gas is returned to atmospheric pressure, and the temperature is lowered to a temperature at which the substrate can be carried out of the processing chamber, and then the grown substrate 10 is carried out of the processing chamber.

Thus, as shown in fig. 6, the semiconductor laminate 1 of the present embodiment is manufactured.

(S130: activation annealing step)

Next, the substrate 10 is irradiated with at least infrared rays in an inert gas atmosphere by, for example, a predetermined heat treatment apparatus (not shown), and the semiconductor laminate 1 is annealed. Thereby, hydrogen (H) bonded to the p-type impurity is desorbed from the first p-type semiconductor layer 23 and the second p-type semiconductor layer 24, respectively, and the p-type impurity in each of the first p-type semiconductor layer 23 and the second p-type semiconductor layer 24 is (electrically) activated.

At this time, in the semiconductor layer 20, at least the drift layer 22 has a low free electron concentration and a low absorption coefficient in the infrared region, and thus heating is difficult. In contrast, in the present embodiment, at least the substrate 10 is heated by irradiating infrared rays from a predetermined heating source (for example, a lamp heater), and the first p-type semiconductor layer 23 and the second p-type semiconductor layer 24 are heated.

In this case, since the substrate 10 satisfies the above-described condition in terms of the absorption coefficient in the infrared region, the substrate 10 can be stably heated by irradiating the substrate 10 with infrared rays, and the temperature of the substrate 10 can be controlled with good accuracy. In addition, the heating efficiency by infrared ray irradiation can be made uniform in the main surface of the substrate 10. As a result, the degree of activation (activation rate, free hole concentration) of the p-type impurity in each of the first p-type semiconductor layer 23 and the second p-type semiconductor layer 24 can be controlled with good accuracy and made uniform within the main surface of the substrate 10.

In addition, at this time, the substrate 10 is heated using the holding member 300 shown in fig. 9 (a) and (b). Thus, the substrate 10 can be heated mainly by irradiating the substrate 10 with infrared rays, not by heat transfer from the holding member 300 to the substrate 10. As a result, the substrate 10 can be stably and uniformly heated in the main surface.

In this case, the inert gas atmosphere contains N, for example₂A gas, or an atmosphere of a rare gas such as argon (Ar) gas. The temperature of the substrate 10 (semiconductor laminate 1) is set to, for example, 500 ℃ to 700 ℃, and the annealing time is set to, for example, 3 minutes to 30 minutes.

(S140: semiconductor device fabrication Process)

Next, a semiconductor device fabrication step S140 of fabricating a semiconductor device 2 using the semiconductor laminate 1 is performed. The semiconductor device manufacturing step S140 of the present embodiment includes, for example, a mesa forming step S141, a first p-type electrode forming step S142, a protective film forming step S143, a second p-type electrode forming step S144, an n-type electrode forming step S145, and an ohmic alloy step S146.

(S141: mesa formation step)

Next, the second p-type semiconductor layer 24, the first p-type semiconductor layer 23, and a part of the drift layer 22 are etched by, for example, a Reactive Ion Etching method (RIE) in a state where a predetermined resist pattern (not shown) is formed on the second p-type semiconductor layer 24.

Thereby, as shown in fig. 10 (a), a mesa structure 29 is formed on the second p-type semiconductor layer 24, the first p-type semiconductor layer 23, and the drift layer 22. Then, the resist pattern is removed.

(S142: first p-type electrode Forming Process)

Next, a palladium (Pd)/nickel (Ni) film is formed by, for example, sputtering so as to cover the surface of the mesa structure 29 and the drift layer 22, and the Pd/Ni film is patterned into a predetermined shape by photolithography.

Thereby, as shown in fig. 10 (b), the first p-type electrode (first anode) 320 is formed on the upper surface of the mesa structure 29, that is, on the second p-type semiconductor layer 24.

(S143: Process for Forming protective film)

Next, an SOG (Spin On Glass) film is formed by, for example, a Spin coating method so as to cover the surface of the mesa structure 29 and the drift layer 22. In this case, the thickness of the SOG film is set to, for example, 100nm to 500 nm.

Next, for example, by a predetermined heat treatment apparatus (not shown), the reaction is performed on, for example, N₂The substrate 10 is irradiated with at least infrared rays in an inert gas atmosphere such as a gas to anneal the semiconductor laminate 1. Thereby, the organic solvent component is volatilized from the SOG film, and the SOG film is cured.

At this time, since the SOG film has a low absorption coefficient in the infrared region, the SOG film itself is difficult to be heated by irradiation with infrared rays. In contrast, in the present embodiment, at least the substrate 10 is heated by irradiating infrared rays from a predetermined heating source (for example, a lamp heater) to heat the SOG film.

In this case, when the substrate 10 satisfies the above-described condition in terms of the absorption coefficient in the infrared region, the substrate 10 can be stably heated by irradiating the substrate 10 with infrared rays, and the temperature of the substrate 10 can be controlled with good accuracy. In addition, the heating efficiency by infrared ray irradiation can be made uniform in the main surface of the substrate 10. As a result, the film quality of the SOG film (the degree of volatilization of the solvent from the SOG film, the degree of curing, and the like) can be controlled with good precision and made uniform within the main surface of the substrate 10.

In addition, at this time, the substrate 10 is heated using the holding member 300 shown in fig. 9 (a) and (b). Thus, the substrate 10 can be heated mainly by irradiating the substrate 10 with infrared rays, not by heat transfer from the holding member 300 to the substrate 10. As a result, the substrate 10 can be stably and uniformly heated in the main surface.

In this case, the inert gas atmosphere contains N, for example₂And an atmosphere of a rare gas such as Ar gas. The temperature of the substrate 10 (semiconductor laminate 1) is set to, for example, 200 ℃ to 500 ℃, and the annealing time is set to, for example, 30 minutes to 3 hours.

After forming the SOG film, forming a second layer on the SOG filmA silicon oxide film (SiO) is formed thereon by, for example, sputtering₂A film). In addition, SiO is added₂The thickness of the film is set to, for example, 100nm to 500 nm. Formation of SiO on SOG film₂After the film formation, the oxide film is patterned into a predetermined shape by photolithography.

As a result, as shown in fig. 11 (a), the protective film 40 is formed so as to cover the surface of the drift layer 22 outside the mesa structure 29, the side surfaces of the mesa structure 29, and a part of the surface of the second p-type semiconductor layer 24 (the periphery of the upper surface of the mesa structure 29).

(S144: second p-type electrode Forming Process)

Next, a Ti/Al film is formed by, for example, sputtering so as to cover the first p-type electrode 32 and the protective film 40 in the opening of the protective film 40, and the Ti/Al film is patterned into a predetermined shape by photolithography.

Thereby, as shown in fig. 11 (b), the second p-type electrode (p-type electrode pad) 34 is formed so as to contact the first p-type electrode 32 in the opening of the protective film 40, extend to the outside of the first p-type electrode 32 on the protective film 40, and cover the mesa structure 29. Specifically, the second p-type electrode 34 is formed so as to overlap a part of the surface of the drift layer 22 outside the mesa structure 29, the side surface of the mesa structure 29, and the upper surface of the mesa structure 29 when the semiconductor laminate 1 is viewed from above in a plan view. This can suppress concentration of an electric field in the vicinity of the pn junction interface near the end of first p-type electrode 32 and the side surface of mesa structure 29.

(S145: n-type electrode Forming step)

Next, a Ti/Al film is formed on the back surface side of the substrate 10 by, for example, sputtering, and the Ti/Al film is patterned into a predetermined shape by photolithography. Thereby, n-type electrode 36 is formed on the back surface side of substrate 10.

(S146: ohmic alloy working procedure)

Next, the semiconductor laminate 1 is irradiated with at least infrared rays in an inert gas atmosphere by, for example, a predetermined heat treatment apparatus (not shown), and the semiconductor laminate 1 is annealed. This improves the adhesion of the metal films constituting the first p-type electrode 32, the second p-type electrode 34, and the n-type electrode 36, and reduces the contact resistance of the first p-type electrode 32 to the second p-type semiconductor layer 24, the contact resistance of the second p-type electrode 34 to the first p-type electrode 32, and the contact resistance of the n-type electrode 36 to the substrate 10.

At this time, the first p-type electrode 32, the second p-type electrode 34, and the n-type electrode 36 are directly heated by irradiating infrared rays from a predetermined heating source (for example, a lamp heater). The substrate 10 is heated by irradiation with infrared rays, thereby heating the first p-type electrode 32, the second p-type electrode 34, and the n-type electrode 36.

In this case, when the substrate 10 satisfies the above-described condition in terms of the absorption coefficient in the infrared region, the substrate 10 can be stably heated by irradiating the substrate 10 with infrared rays, and the temperature of the substrate 10 can be controlled with good accuracy. In addition, the heating efficiency by infrared ray irradiation can be made uniform in the main surface of the substrate 10. As a result, the contact resistance of the first p-type electrode 32 to the second p-type semiconductor layer 24, the contact resistance of the second p-type electrode 34 to the first p-type electrode 32, and the contact resistance of the n-type electrode 36 to the substrate 10 can be made uniform within the main surface of the substrate 10.

In addition, at this time, the substrate 10 is heated using the holding member 300 shown in fig. 9 (a) and (b). Thus, the substrate 10 can be heated mainly by irradiating the substrate 10 with infrared rays, not by heat transfer from the holding member 300 to the substrate 10. As a result, the substrate 10 can be stably and uniformly heated in the main surface.

In this case, the inert gas atmosphere contains N, for example₂A gas, or an atmosphere of a rare gas such as Ar gas. The temperature of the substrate 10 (semiconductor laminate 1) is set to, for example, 500 ℃ to 700 ℃, and the annealing time is set to, for example, 30 minutes to 3 hours.

Then, the semiconductor laminate 1 is diced and divided into chips having a predetermined size.

As described above, the semiconductor device 2 of the present embodiment is manufactured as shown in fig. 12.

(4) Effects obtained by the present embodiment

According to the present embodiment, 1 or more effects shown below can be obtained.

(a) The substrate 10 manufactured by the manufacturing method of the present embodiment has a small crystal distortion and contains substantially no O or impurities other than n-type impurities (e.g., impurities for compensating for n-type impurities). Thus, the substrate 10 of the present embodiment can be represented by the above formula (1) (α ═ nK λ) using the predetermined constant K and the constant a^a) The absorption coefficient alpha in a wavelength range of at least 1 [ mu ] m or more and 3.3 [ mu ] m or less is approximated. As a result, the heating condition in the step of heating the substrate 10 by irradiating at least infrared rays to the substrate 10 can be easily set, and the substrate 10 can be heated with good accuracy and good reproducibility.

For reference, it is difficult for a GaN crystal produced by a conventional production method to approximate the absorption coefficient α with good accuracy from the above formula (1) using the above-described predetermined constant K and constant a.

Here, fig. 5 (b) is a graph comparing the relationship between the absorption coefficient at a wavelength of 2 μm and the free electron concentration. Fig. 5 (b) shows not only the absorption coefficient of the GaN crystal produced by the production method of the present embodiment but also the absorption coefficients of the GaN crystals described in papers (a) to (D).

Paper (a): A.S. Barker Physical Review B7 (1973) p743Fig.8

Paper (B): P.Perlin, Physicsl Review Letter 75(1995) p296Fig.1 was extrapolated from a curve of 0.3 GPa.

Paper (C): bentuomi, Material Science Engineering B50(1997) p142-147Fig.1

Paper (D): S.Porowski, J.Crystal Growth 189-

As shown in fig. 5 (b), the absorption coefficient α of the conventional GaN crystal described in articles (a) to (D) is larger than the absorption coefficient α of the GaN crystal produced by the production method of the present embodiment. In addition, the slope of the absorption coefficient α of the conventional GaN crystal is different from the slope of the absorption coefficient α of the GaN crystal produced by the production method of the present embodiment. Note that, in papers (a) and (C), it can also be seen that the slope of the absorption coefficient α changes as the free electron concentration n increases. Therefore, it is difficult for the conventional GaN crystals described in papers (a) to (D) to approximate the absorption coefficient α with good accuracy from the above formula (1) using the above-specified constant K and constant a. Specifically, for example, the constant K may be higher than the predetermined range or the constant a may be a value other than 3.

This is considered to be based on the following reason. It is considered that a conventional GaN crystal has a large crystal distortion due to its manufacturing method. When crystal distortion occurs in the GaN crystal, dislocations increase in the GaN crystal. Therefore, dislocation scattering occurs in the conventional GaN crystal, and the absorption coefficient α is considered to be increased or varied due to the dislocation scattering. Alternatively, it is considered that the concentration of O accidentally mixed into the GaN crystal produced by the conventional production method is high. If O is mixed into the GaN crystal at a high concentration, the lattice constants a and c of the GaN crystal increase (refer to Chris G. Van de Walle, Physical Review B vol.68,165209 (2003)). Therefore, in the conventional GaN crystal, a local lattice mismatch occurs between the portion contaminated with O and the portion having a high purity, and crystal distortion occurs in the GaN crystal. As a result, the absorption coefficient α of the conventional GaN crystal is considered to be increased or varied. Alternatively, it is considered that a compensation impurity for compensating for an n-type impurity is accidentally mixed into a GaN crystal manufactured by a conventional manufacturing method, and the concentration of the compensation impurity is high. If the concentration of the compensating impurity is high, a high concentration of the n-type impurity is required to obtain a predetermined free electron concentration. Therefore, the concentration of the compensation impurity and the total impurity containing the n-type impurity in the conventional GaN crystal is increased, and the crystal distortion is considered to be increased. As a result, the absorption coefficient α of the conventional GaN crystal is considered to be increased or varied. It has been confirmed that the GaN free-standing substrate containing O and having lattice distortion actually has a higher absorption coefficient α (lower mobility) than the substrate 10 of the present embodiment having the same free electron concentration.

For this reason, it is difficult for the conventional GaN crystal to approximate the absorption coefficient α with good accuracy from the above formula (1) using the above-described predetermined constant K and constant a. That is, it is difficult for the conventional GaN crystal to design the absorption coefficient with good accuracy based on the concentration n of free electrons. Therefore, in a process of heating a substrate formed of a conventional GaN crystal by irradiating the substrate with at least infrared rays, heating efficiency tends to vary depending on the substrate, and it is difficult to control the temperature of the substrate. As a result, there is a possibility that the reproducibility of the temperature of each substrate is lowered.

In contrast, the substrate 10 manufactured by the manufacturing method of the present embodiment has a small crystal distortion and contains almost no O or n-type impurity. The absorption coefficient of the substrate 10 of the present embodiment is less affected by scattering due to crystal distortion (dislocation scattering), and is mainly determined by ionized impurity scattering. This can reduce the variation in the absorption coefficient α of the substrate 10, and the absorption coefficient α of the substrate 10 can be approximated by the above equation (1) using the predetermined constant K and the constant a. By approximating the absorption coefficient α of the substrate 10 by the above formula (1), the absorption coefficient of the substrate 10 can be designed with good accuracy based on the concentration n of free electrons generated by doping the substrate 10 with an n-type impurity. By designing the absorption coefficient of the substrate 10 with good accuracy based on the concentration n of free electrons, in the step of heating the substrate 10 by irradiating at least infrared rays to the substrate 10, the heating conditions can be easily set, and the temperature of the substrate 10 can be controlled with good accuracy. As a result, the reproducibility of the temperature of each substrate 10 can be improved. Thus, the present embodiment can heat the substrate 10 with good accuracy and good reproducibility.

(b) In this embodiment, by growing the semiconductor layer 30 on the substrate 10 having small crystal distortion, the crystal distortion can be reduced even in the semiconductor layer 30, and the crystallinity of the semiconductor layer 30 can be improved. In addition, by controlling the temperature of the substrate 10 with good accuracy, the crystallinity, thickness, various impurity concentrations, and the like of the semiconductor layer 20 and the like grown on the substrate 10 can be controlled with good accuracy. By this, the semiconductor layer 20 can be manufactured with high quality, and the characteristics of the entire semiconductor device 2 can be made uniform.

For example, when the semiconductor device 2 is a light emitting element such as a light emitting diode or a laser diode, the light emitting efficiency of the semiconductor device 2 as the light emitting element can be improved by reducing crystal distortion of the light emitting layer. In addition, since the amount of indium (In) introduced depends on the growth temperature of the light-emitting layer, the composition ratio of In the light-emitting layer can be controlled with good accuracy by controlling the temperature of the substrate 10 with good accuracy. This makes it possible to make the light-emitting wavelength of the entire semiconductor device 2 as a light-emitting element uniform.

(c) Since the absorption coefficient of the substrate 10 manufactured by the manufacturing method of the present embodiment based on free carrier absorption is smaller than that of the conventional substrate, the resistivity of the substrate 10 of the present embodiment is lower than that of the conventional substrate.

For reference, it is considered that the conventional GaN crystal has a low mobility (μ) because the absorption coefficient by free carrier absorption at a predetermined free electron concentration is large as shown in fig. 5 (b). Therefore, the resistivity (ρ 1/en μ) of the conventional GaN crystal is considered to be high. As a result, the on-resistance of the semiconductor device using the substrate formed of the conventional GaN crystal was considered to be high.

In order to obtain a desired resistivity in a conventional GaN crystal, it is conceivable to increase the concentration of an n-type impurity. However, since increasing the concentration of the n-type impurity tends to lower the mobility, it is necessary to excessively increase the concentration of the n-type impurity in order to obtain a desired resistivity in a conventional GaN crystal. Therefore, crystal distortion of the conventional GaN crystal tends to increase. As a result, the absorption coefficient α of the conventional GaN crystal is likely to increase or vary.

In contrast, the substrate 10 manufactured by the manufacturing method of the present embodiment is assumed to have higher mobility than the conventional substrate because the absorption coefficient by free carrier absorption is smaller than that of the conventional substrate. Thus, even when the free electron concentration in the substrate 10 of the present embodiment is equal to that in the conventional substrate, the resistivity of the substrate 10 of the present embodiment is lower than that of the conventional substrate. As a result, the on-resistance of the semiconductor device 2 using the substrate 10 of the present embodiment can be reduced.

In addition, the substrate 10 of the present embodiment can make the concentration of n-type impurities for obtaining a desired resistivity lower than that of the conventional substrate. This reduces crystal distortion and improves the crystallinity of the substrate 10. As a result, desired resistivity of the substrate 10 can be obtained while reducing the unevenness of the absorption coefficient α of the substrate 10.

(d) The absorption coefficient α of the substrate 10 of the present embodiment is set to 0.15 λ³Not more than α, the substrate 10 can sufficiently absorb infrared rays, and the substrate 10 can be stably heated. Further, by setting Δ α to 1.0 or less, the heating efficiency by infrared ray irradiation can be made uniform in the main surface of the substrate 10 in the step of heating the substrate 10. This makes it possible to make the quality of the semiconductor laminate 1 manufactured using the substrate 10 uniform within the main surface of the substrate 10. As a result, the quality and yield of the semiconductor device 2 manufactured using the semiconductor laminate 1 can be improved.

(e) The concentration of intrinsic carriers that are thermally excited between bands of the substrate 10 under the temperature condition of 27 ℃ or more and 1250 ℃ or less is lower than the concentration of free electrons generated in the substrate 10 by the doping of the n-type impurity under the temperature condition of 27 ℃. By satisfying this condition, it is considered that the free carrier concentration of the substrate 10 under a predetermined temperature condition in the step of heating the substrate 10 is substantially equal to the free carrier concentration of the substrate 10 under a temperature condition of room temperature. From this, it is considered that the free carrier absorption under the predetermined temperature condition is substantially equal to the free carrier absorption at room temperature. That is, as described above, when the absorption coefficient in the infrared region of the substrate 10 satisfies the predetermined condition at room temperature, it is considered that the absorption coefficient in the infrared region of the substrate 10 substantially maintains the predetermined condition even under the predetermined temperature condition.

(f) The concentration of free electrons generated in the substrate 10 by doping of the n-type impurity is 1 × 10 under the temperature condition of 27 ℃¹⁸cm^-3As described above, the difference between the maximum value and the minimum value of the free electron concentration in the main surface of the substrate 10 is 8.3 × 10¹⁷cm^-3Within. As a result, the absorption coefficient of the substrate 10 at a wavelength of 2 μm can be set to 1.2cm^-1As described above, the difference between the maximum value and the minimum value of the absorption coefficient at a wavelength of 2 μm in the main surface of the substrate 10 can be set to 1.0cm^-1Within.

(g) The concentration of O in the substrate 10 is 1/10 times or less with respect to the total concentration of Si and Ge in the substrate 10. Thus, the concentration of the n-type impurity in the substrate 10 can be controlled by controlling the total concentration of the added amounts of Si and Ge relatively easily. Since the concentration of the n-type impurity in the substrate 10 can be easily controlled, the free electron concentration n in the substrate 10 can be controlled with good accuracy so as to satisfy the predetermined condition, and the difference Δ n between the maximum value and the minimum value of the concentration of the free electrons in the main surface of the substrate 10 can be controlled with good accuracy so as to satisfy the predetermined condition. As a result, the absorption coefficient of the substrate 10 can be adjusted with good accuracy and good reproducibility, and the absorption coefficient in the main surface of the substrate 10 can be stabilized and made uniform.

< second embodiment of the present invention >

In the above-described embodiment, the case where the semiconductor laminate 1 is configured to manufacture the semiconductor device 2 as a pn junction diode has been described, but the semiconductor laminate 1 may be configured to manufacture another device as in the second embodiment described below. The present embodiment will be described only for the elements different from the above embodiments.

(1) Semiconductor laminate

The semiconductor laminate 1 of the present embodiment will be described with reference to fig. 13 (a). Fig. 13 (a) is a schematic cross-sectional view showing the semiconductor laminate 1 of the present embodiment.

As shown in fig. 13 (a), the semiconductor laminate 1 of the present embodiment is configured as an intermediate used in manufacturing a semiconductor device 2 which is a Schottky Barrier Diode (SBD), for example. The semiconductor laminate 1 includes, for example, a substrate 10 and a semiconductor layer 20. The semiconductor layer 20 may have a p-type semiconductor layer, for example, having a base n-type semiconductor layer 21 and a drift layer 22. The substrate 10, the base n-type semiconductor layer 21, and the drift layer 22 are the same as the substrate 10, the base n-type semiconductor layer 21, and the drift layer 22, respectively, in the first embodiment. The drift layer 22 has an implanted portion (reference numeral is not shown) of a p-type impurity.

(2) Method for manufacturing semiconductor laminate and method for manufacturing semiconductor device

Next, a method for manufacturing the semiconductor laminate 1 and a method for manufacturing the semiconductor device 2 according to the present embodiment will be described with reference to fig. 13 to 15. Fig. 13 (b), 14 (a), (b), and 15 (a) are schematic cross-sectional views illustrating a manufacturing process of a semiconductor device, and fig. 15 (b) is a schematic cross-sectional view illustrating the semiconductor device 2 according to this embodiment.

(S210 to S220: substrate preparation step and semiconductor layer formation step)

As shown in fig. 13 (a), a semiconductor laminate 1 is produced in the same manner as the substrate preparation step S110 to the semiconductor layer formation step S120 of the first embodiment, except that the p-type semiconductor layer is not formed.

(S240: semiconductor device fabrication Process)

Next, a semiconductor device fabrication step S240 of fabricating a semiconductor device 2 using the semiconductor laminate 1 is performed. The semiconductor device manufacturing step S240 of the present embodiment includes, for example, an ion implantation step S241, an activation annealing step S242, a protective film forming step S243, a p-type electrode forming step S244, an n-type electrode forming step S245, and an ohmic alloy step S246.

(S241: ion implantation step)

First, as shown in fig. 13 (b), a front side cap layer 52 made of a silicon nitride film (SiNx film) or an aluminum nitride film (AlN film) is formed on the semiconductor layer 20 by, for example, sputtering. This can suppress damage to the drift layer 22 when ion implantation is performed on the drift layer 22, and can also suppress the absence of nitrogen (N) from the drift layer 22 in the activation annealing step S242 described later. In this case, the thickness of the front side cap layer 52 is set to, for example, 20nm to 50 nm.

After the front side cover layer 52 is formed, a predetermined resist pattern 54 is formed on the front side cover layer 52 as shown in fig. 14 (a). At this time, an opening (not shown) is formed in the resist pattern 54 at the position of the implanted portion of the drift layer 22 in a plan view. In the present embodiment, the opening of the resist pattern 54 is formed in a ring shape in a plan view, for example.

After the resist pattern 54 is formed, the implanted portion of the drift layer 22 is subjected to ion implantation of p-type impurities through the opening of the resist pattern 54. Thereby, a p-type region 25 containing a p-type impurity is formed in the drift layer 22 (for example, a part of the front surface side region of the drift layer 22). P-type region 25 has, for example, a ring shape in a plan view.

At this time, at least one selected from the group consisting of Mg, C, iron (Fe), beryllium (Be), zinc (Zn), vanadium (V), and antimony (Sb), for example, is used as the p-type impurity to Be ion-implanted. In this case, the acceleration voltage for ion implantation of the p-type impurity is set to, for example, 10keV or more and 100keV or less, and the dose is set to, for example, 1 × 10¹³cm^-2Above and 1 × 10¹⁵cm^-2The following. Thus, the maximum value of the p-type impurity concentration in p-type region 25 is, for example, 1 × 10¹⁸at·cm^-3Above and 1 × 10²⁰at·cm^-3Hereinafter, the depth of the p-type region 25 from the surface of the drift layer 22 is, for example, 50nm or more and 300nm or less.

After the p-type impurity is ion-implanted, the resist pattern 54 is removed.

(S242: activation annealing step)

Next, as shown in fig. 14 (b), a back side cap layer 56 made of a SiNx film or an AlN film is formed on the back side of the substrate 10 by, for example, sputtering. This can suppress the absence of nitrogen (N) from the substrate 10 in the activation annealing step S242 described later. In this case, the thickness of the back surface side layer 56 is set to, for example, 20nm to 50 nm.

After the formation of the back surface side cover layer 56, the substrate 10 is irradiated with at least infrared rays in an inert gas atmosphere by, for example, a predetermined heat treatment apparatus (not shown), and the semiconductor laminate 1 is annealed. This recovers the crystal damage to semiconductor layer 20 in ion implantation step S241, and introduces the p-type impurity in p-type region 25 into the crystal lattice to (electrically) activate the same.

At this time, in the semiconductor layer 20, at least the drift layer 22 has a low free electron concentration and a low absorption coefficient in the infrared region, and thus heating is difficult. In contrast, in the present embodiment, at least the substrate 10 is heated by irradiating infrared rays from a predetermined heating source (for example, a lamp heater), thereby heating the semiconductor layer 20.

In this case, when the substrate 10 satisfies the above-described condition in terms of the absorption coefficient in the infrared region, the substrate 10 can be stably heated by irradiating the substrate 10 with infrared rays, and the temperature of the substrate 10 can be controlled with good accuracy. In addition, the heating efficiency by infrared ray irradiation can be made uniform in the main surface of the substrate 10. As a result, the degree of activation (activation rate, free hole concentration) of the p-type impurity in p-type region 25 can be controlled with good accuracy and made uniform within the main surface of substrate 10.

In addition, at this time, the substrate 10 is heated using the holding member 300 shown in fig. 9 (a) and (b). Thus, the substrate 10 can be heated mainly by irradiating the substrate 10 with infrared rays, not by heat transfer from the holding member 300 to the substrate 10. As a result, the substrate 10 can be stably and uniformly heated in the main surface.

In this case, the annealing treatment is performed, for example, according to the following treatment steps and treatment conditions: the temperature is raised from the start temperature to the annealing temperature for a period of time within a range of 3 to 30 seconds, the annealing temperature is maintained for a period of time within a range of 20 seconds to 3 minutes, and then the temperature is lowered from the annealing temperature to the stop temperature for a period of time within a range of 1 to 10 minutes. The stop temperature and the start temperature are set to temperatures within a range of 500 to 800 ℃, for example. The annealing temperature is set to a temperature in the range of 1100 ℃ to 1250 ℃, for example. The inert gas atmosphere for annealing treatment contains N₂The pressure of the atmosphere of a rare gas such as a gas or an Ar gas is set to a pressure in the range of 100 to 250kPa, for example.

After the annealing treatment is completed, as shown in fig. 15 (a), the front side cover layer 52 and the back side cover layer 56 are removed with a predetermined solvent.

(S244: P-type electrode Forming step)

Next, a Pd/Ni film is formed by, for example, sputtering so as to cover the semiconductor layer 20, and the Pd/Ni film is patterned into a predetermined shape by photolithography. Thus, p-type electrode 31 is formed such that the outer peripheral portion of p-type electrode 31 overlaps p-type region 25 in a plan view.

(S145: n-type electrode Forming step)

Next, a Ti/Al film is formed on the back surface side of the substrate 10 by, for example, sputtering, and the Ti/Al film is patterned into a predetermined shape by photolithography. Thereby, n-type electrode 36 is formed on the back surface side of substrate 10.

(S246: ohmic alloy working procedure)

Next, an ohmic alloy step S246 is performed in the same manner as the ohmic alloy step S146 of the first embodiment.

Then, the semiconductor laminate 1 is diced and divided into chips having a predetermined size.

As described above, the semiconductor device 2 of the present embodiment is manufactured as shown in fig. 15 (b). In the semiconductor device 2, the p-type region 25 is formed as a guard ring on the front surface side of the drift layer 22, whereby electric field concentration around the p-type electrode 31 can be suppressed. As a result, the withstand voltage of the semiconductor device 2 can be improved.

(3) Effects obtained by the present embodiment

In the present embodiment, in the activation annealing step S242 after ion implantation, the semiconductor layer 20 is heated by heating the substrate 10 satisfying the above-described condition on the absorption coefficient in the infrared region, thereby activating the p-type impurity in the p-type region 25.

Here, the activation annealing step after ion implantation is often performed at a high temperature for a short time because the p-type impurity is activated while crystal damage is suppressed. Therefore, if it is difficult to design the absorption coefficient by the free electron concentration n as in the case of a substrate formed of a conventional GaN crystal, there is a possibility that the heating efficiency varies greatly depending on the substrate. As a result, there is a possibility that the degree of activation of the p-type impurity varies among the substrates, or that crystal damage (e.g., N loss) of the semiconductor layer varies among the substrates. In addition, if variation occurs in heating efficiency in the main surface of the substrate, variation may occur in the degree of activation of the p-type impurity in the main surface of the substrate, or variation may occur in the main surface of the substrate due to crystal damage of the semiconductor layer.

In contrast, in the present embodiment, since the substrate 10 satisfies the above-described condition in terms of the absorption coefficient in the infrared region, the temperature of the substrate 10 heated by irradiation with infrared rays can be controlled with good accuracy in the activation annealing step S242 after ion implantation, and the reproducibility of the temperature of each substrate 10 can be improved. This can suppress variations in the degree of activation of the p-type impurity in each substrate. In addition, variation in crystal damage of the semiconductor layer of each substrate can be suppressed, and crystal damage itself of the semiconductor layer can be easily suppressed by forming an appropriate cap layer. Further, when the substrate 10 satisfies the above-described condition in terms of the absorption coefficient in the infrared region, the heating efficiency by infrared ray irradiation can be made uniform in the main surface of the substrate 10. Thus, in the activation annealing step S242, the degree of activation of the p-type impurity can be made uniform in the main surface of the substrate 10 (semiconductor layer 20), and the occurrence of local crystal damage in the semiconductor layer 20 can be suppressed. As a result, the quality and yield of the semiconductor device 2 manufactured using the semiconductor laminate 1 can be improved.

< other embodiment >

The embodiments of the present invention have been specifically described above. However, the present invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the invention.

In the above embodiment, the case where the substrate 10 and the semiconductor layer 20 are each formed of GaN was described, but the substrate 10 and the semiconductor layer 20 are not limited to GaN, and may be formed of, for example, Al, which is a group III nitride semiconductor such as AlN, aluminum gallium nitride (AlGaN), indium nitride (InN), indium gallium nitride (InGaN), or aluminum indium gallium nitride (AlInGaN), or the like_xIn_yGa_1-x-yAnd N (x is 0 to 1, y is 0 to 1, and x + y is 0 to 1) is a group III nitride semiconductor represented by the formula.

In the above embodiment, the case where the semiconductor layer 20 is formed of the same group III nitride semiconductor (GaN) as the substrate 10 was described, but the semiconductor layer 20 may be formed of a group III nitride semiconductor different from the substrate 10.

In the above embodiment, the case where the seed substrate 5 made of GaN single crystal is used to manufacture the substrate 10 in the substrate manufacturing step S112 has been described, but the substrate 10 may be manufactured by the following method. For example, a GaN layer provided on a different-type substrate such as a sapphire substrate may be used as a base layer, and an ingot obtained by growing a GaN layer thick through a nano mask or the like may be separated from the different-type substrate, and a plurality of substrates 10 may be cut from the ingot.

In the above embodiment, the case where the semiconductor layer 20 is formed by the MOVPE method in the semiconductor layer forming step S120 is described, but the semiconductor layer 20 may be formed by other vapor phase epitaxy method such as HVPE method, a liquid phase growth method such as flux method, and an ammonothermal method.

In the first embodiment, the case where the semiconductor device 2 is a pn junction diode is described, and in the second embodiment, the case where the semiconductor device 2 is an SBD is described, but the semiconductor device 2 may be configured as another device as long as the substrate 10 containing an n-type impurity is used. For example, the semiconductor device 2 may be a light emitting diode, a laser diode, a junction barrier schottky diode (JBS), a bipolar transistor, or the like.

In the second embodiment, the case where the ion implantation of the p-type impurity is performed to the semiconductor layer 20 in the ion implantation step S241 has been described, but the ion implantation of another impurity such as an n-type impurity may be performed to the semiconductor layer 20 as necessary.

< preferred embodiment of the present invention >

The preferred embodiments of the present invention are described below.

(attached note 1)

A nitride crystal substrate formed of a crystal of a group III nitride and containing an n-type impurity,

the wavelength is represented by λ (μm), and the absorption coefficient of the nitride crystal substrate at 27 ℃ is represented by α (cm)^-1) And n (cm) is a free electron concentration in the nitride crystal substrate^-3) And the absorption coefficient alpha in a wavelength range of at least 1 μm to 3.3 μm is approximated by the following formula (1) when K and a are each constant.

α＝nKλ^a…(1)

(wherein, 1.5X 10^-19≤K≤6.0×10^-19、a＝3)

(attached note 2)

The nitride crystal substrate according to supplementary note 1, wherein,

the absorption coefficient α in a wavelength range of at least 1 μm or more and 3.3 μm or less is approximated by the following formula (1) ".

α＝2.2×10^-19nλ³…(1)”

(attached note 3)

The nitride crystal substrate according to supplementary note 1 or 2, wherein,

when a difference between a maximum value and a minimum value of the absorption coefficient α in the main surface of the nitride crystal substrate is Δ α, the absorption coefficient α and the Δ α satisfy the following expressions (2) and (3) in a wavelength range of at least 1 μm or more and 3.3 μm or less.

α≥0.15λ³…(2)

Δα≤1.0…(3)

(attached note 4)

A nitride crystal substrate formed of a crystal of a group III nitride and containing an n-type impurity,

the nitride crystal substrate has an absorption coefficient of 1.2cm at a wavelength of 2 μm^-1In the above-mentioned manner,

the difference between the maximum value and the minimum value of the absorption coefficient at a wavelength of 2 μm in the main surface of the nitride crystal substrate is 1.0cm^-1Within.

(attached note 5)

The nitride crystal substrate according to any one of supplementary notes 1 to 4, wherein,

the concentration of intrinsic carriers thermally excited between bands of the nitride crystal substrate at a temperature of 27 ℃ or higher and 1250 ℃ or lower is lower than the concentration of free electrons generated in the nitride crystal substrate by doping of the n-type impurity at a temperature of 27 ℃.

(attached note 6)

The nitride crystal substrate according to any one of supplementary notes 1 to 5, wherein,

is preceded by the doping of the aforementioned n-type impurityThe concentration of free electrons generated in the nitride crystal substrate is 1X 10 under the temperature condition of 27 DEG C¹⁸cm^-3In the above-mentioned manner,

the difference between the maximum value and the minimum value of the free electron concentration in the main surface of the nitride crystal substrate is 8.3X 10¹⁷cm^-3Within.

(attached note 7)

The nitride crystal substrate according to any one of supplementary notes 1 to 6, wherein,

the concentration of the n-type impurity in the nitride crystal substrate is 1.0X 10¹⁸at·cm^-3In the above-mentioned manner,

the difference between the maximum value and the minimum value of the concentration of the n-type impurity in the main surface of the nitride crystal substrate is 8.3X 10¹⁷at·cm^-3Within.

(attached note 8)

The nitride crystal substrate according to any one of supplementary notes 1 to 7, wherein,

the concentration of oxygen in the nitride crystal substrate is 1/10 times or less with respect to the total concentration of silicon and germanium in the nitride crystal substrate.

(attached note 9)

The nitride crystal substrate according to supplementary note 8, wherein,

the concentration of oxygen in the nitride crystal substrate is less than 1X 10¹⁷at·cm^-3，

The total concentration of silicon and germanium in the aforementioned nitride crystal substrate is 1X 10¹⁸at·cm^-3The above.

(attached note 10)

A semiconductor laminate, comprising:

a nitride crystal substrate formed of a crystal of a group III nitride and containing an n-type impurity; and

a semiconductor layer provided on the nitride crystal substrate and formed of a group III nitride semiconductor,

the wavelength is represented by λ (μm), and the absorption coefficient of the nitride crystal substrate at 27 ℃ is represented by α (cm)^-1) Nitriding the above-mentioned materialThe concentration of free electrons in the substrate is n (cm)^-3) And the absorption coefficient alpha in a wavelength range of at least 1 μm to 3.3 μm is approximated by the following formula (1) when K and a are each constant.

α＝nKλ^a…(1)

(wherein, 1.5X 10^-19≤K≤6.0×10^-19、a＝3)

(attached note 11)

A semiconductor laminate, comprising:

a nitride crystal substrate formed of a crystal of a group III nitride and containing an n-type impurity; and

a semiconductor layer provided on the nitride crystal substrate and formed of a group III nitride semiconductor,

the nitride crystal substrate has an absorption coefficient of 1.2cm at a wavelength of 2 μm^-1In the above-mentioned manner,

the difference between the maximum value and the minimum value of the absorption coefficient at a wavelength of 2 μm in the main surface of the nitride crystal substrate is 1.0cm^-1Within.

(attached note 12)

The semiconductor laminate according to supplementary note 10 or 11, wherein,

the reflectance of the surface of the semiconductor layer is 5% to 30% in a wavelength range of at least 1 μm to 3.3 μm.

(attached note 13)

The semiconductor laminate according to any one of supplementary notes 10 to 12, wherein,

the semiconductor layer has a p-type semiconductor layer provided on the nitride crystal substrate and containing a p-type impurity.

(attached note 14)

The semiconductor laminate according to any one of supplementary notes 10 to 12, wherein,

the semiconductor layer has an implanted portion of an impurity.

(attached note 15)

A method for manufacturing a semiconductor laminate, comprising:

preparing a nitride crystal substrate that is formed of a group III nitride crystal and contains an n-type impurity; and

a step of heating the nitride crystal substrate by irradiating the nitride crystal substrate with at least infrared rays,

in the step of preparing the nitride crystal substrate,

as the nitride crystal substrate, the following substrates were prepared: the wavelength is represented by λ (μm), and the absorption coefficient of the nitride crystal substrate at 27 ℃ is represented by α (cm)^-1) And n (cm) is a free electron concentration in the nitride crystal substrate^-3) And the absorption coefficient alpha in a wavelength range of at least 1 μm to 3.3 μm is approximated by the following formula (1) when K and a are each constant.

α＝nKλ^a…(1)

(wherein, 1.5X 10^-19≤K≤6.0×10^-19、a＝3)

(subsidiary 16)

A method for manufacturing a semiconductor laminate, comprising:

preparing a nitride crystal substrate that is formed of a group III nitride crystal and contains an n-type impurity; and

a step of heating the nitride crystal substrate by irradiating the nitride crystal substrate with at least infrared rays,

in the step of preparing the nitride crystal substrate,

as the nitride crystal substrate, an absorption coefficient at a wavelength of 2 μm of 1.2cm was prepared^-1Above and having a difference of 1.0cm between the maximum value and the minimum value of the absorption coefficient at a wavelength of 2 μm in the main plane^-1A substrate inside.

(attached note 17)

The method of manufacturing a semiconductor laminate according to supplementary note 15 or 16, wherein,

the step of heating the nitride crystal substrate includes a step of epitaxially growing a semiconductor layer made of a group III nitride semiconductor on the nitride crystal substrate.

(attached note 18)

The method for manufacturing a semiconductor laminate according to supplementary note 17, comprising:

a step of performing epitaxial growth on the nitride crystal substrate using a p-type semiconductor layer containing a p-type impurity as a layer constituting the semiconductor layer; and

and a step of heating the nitride crystal substrate to activate the p-type impurity in the p-type semiconductor layer, the step being a step of heating the nitride crystal substrate.

(attached note 19)

The method for manufacturing a semiconductor laminate according to supplementary note 17, comprising:

implanting an impurity of a predetermined conductivity type into the semiconductor layer; and

and a step of heating the nitride crystal substrate to activate the impurity in the semiconductor layer, the step of heating the nitride crystal substrate.

(attached note 20)

The method for manufacturing a semiconductor laminate according to any one of supplementary notes 17 to 19, comprising:

forming an electrode so as to be in contact with at least one of the back surface of the nitride crystal substrate and the main surface of the semiconductor layer; and

and a step of heating the nitride crystal substrate to reduce the contact resistance of the electrode, the step being a step of heating the nitride crystal substrate.

(attached note 21)

The method for manufacturing a semiconductor laminate according to any one of supplementary notes 17 to 20, comprising:

forming a protective film on the semiconductor layer; and

and a step of heating the nitride crystal substrate to cure the protective film, the step of heating the nitride crystal substrate.

(attached note 22)

The method of manufacturing a semiconductor laminate according to any one of supplementary notes 17 to 21, wherein,

the step of preparing a nitride crystal substrate includes a crystal growth step of: a seed crystal substrate and a raw material containing a group III element are carried into a reaction vessel, and a halide and a nitriding agent of the raw material are supplied to the seed crystal substrate heated to a predetermined crystal growth temperature, whereby a crystal of a nitride of the group III element is grown on the seed crystal substrate,

in the step of growing the crystal, the crystal is grown,

as a member constituting a high temperature region in the reaction vessel, a member is used, at least the surface of which is formed of a material containing no quartz and no boron, the high temperature region being a region heated to at least the crystal growth temperature and being in contact with a gas supplied to the seed crystal substrate.

(attached note 23)

The method of manufacturing a semiconductor laminate according to supplementary note 22, wherein,

as the member constituting the high-temperature region, a member formed of silicon carbide-coated graphite is used.

(attached note 24)

A method for manufacturing a semiconductor laminate, comprising:

preparing a nitride crystal substrate that is formed of a group III nitride crystal and contains an n-type impurity; and

a step of heating the nitride crystal substrate by irradiating the nitride crystal substrate with at least infrared rays,

the step of preparing the nitride crystal substrate includes:

measuring an absorption coefficient of the nitride crystal substrate in an infrared region at 27 ℃; and

based on the measured absorption coefficient of the nitride crystal substrate, it is determined that the wavelength is λ (μm) and the absorption coefficient of the nitride crystal substrate is α (cm)^-1) And n (cm) is a free electron concentration in the nitride crystal substrate^-3) And each of K and a is set toAnd (b) if the absorption coefficient α in a wavelength range of at least 1 μm to 3.3 μm can be approximated by the following formula (1).

α＝nKλ^a…(1)

(wherein, 1.5X 10^-19≤K≤6.0×10^-19、a＝3)

(attached note 25)

A method for manufacturing a semiconductor laminate, comprising:

preparing a nitride crystal substrate that is formed of a group III nitride crystal and contains an n-type impurity; and

a step of heating the nitride crystal substrate by irradiating the nitride crystal substrate with at least infrared rays,

the step of preparing the nitride crystal substrate includes:

measuring an absorption coefficient in an infrared region at least at 2 points or more in a main surface of the nitride crystal substrate; and

based on the measured absorption coefficient of the nitride crystal substrate, it was judged whether or not the absorption coefficient of the nitride crystal substrate at a wavelength of 2 μm was 1.2cm^-1Whether or not the difference between the maximum value and the minimum value of the absorption coefficient at a wavelength of 2 μm in the main surface of the nitride crystal substrate is 1.0cm^-1The following steps.

(attached note 26)

A method for manufacturing a semiconductor device, comprising:

preparing a nitride crystal substrate that is formed of a group III nitride crystal and contains an n-type impurity; and

a step of heating the nitride crystal substrate by irradiating the nitride crystal substrate with at least infrared rays,

in the step of preparing the nitride crystal substrate,

as the nitride crystal substrate, the following substrates were prepared: the wavelength is represented by λ (μm), and the absorption coefficient of the nitride crystal substrate at 27 ℃ is represented by α (cm)^-1) Will be beforeThe free electron concentration in the nitride crystal substrate is n (cm)^-3) And the absorption coefficient alpha in a wavelength range of at least 1 μm to 3.3 μm is approximated by the following formula (1) when K and a are each constant.

α＝nKλ^a…(1)

(wherein, 1.5X 10^-19≤K≤6.0×10^-19、a＝3)

(attached note 27)

A method for manufacturing a semiconductor device, comprising:

preparing a nitride crystal substrate that is formed of a group III nitride crystal and contains an n-type impurity; and

a step of heating the nitride crystal substrate by irradiating the nitride crystal substrate with at least infrared rays,

in the step of preparing the nitride crystal substrate,

as the nitride crystal substrate, an absorption coefficient at a wavelength of 2 μm of 1.2cm was prepared^-1Above and having a difference of 1.0cm between the maximum value and the minimum value of the absorption coefficient at a wavelength of 2 μm in the main plane^-1A substrate inside.

Description of the reference numerals

1 semiconductor laminate

2 semiconductor device

10 nitride crystal substrate (substrate)

20 semiconductor layer