阅读说明：本技术 一种降流调节器芯片 (Current-reducing regulator chip ) 是由 赵福合 于 2019-08-29 设计创作，主要内容包括：本发明公开了一种降流调节器芯片,包括外部封装结构和内部电路,其特征在于,所述内部电路包括基准电压源Reference、恒定关闭时间模块COT control、比较器U1、比较器U2、逻辑与门P1和RS触发器U4,所述基准电压源Reference的一端连接引脚VDD,基准电压源Reference的另一端连接比较器U1的输入端正极,比较器U1的输出端连接加法器U5的一个输入端,比较器U2的输入端负极通过电阻连接引脚LD,本发明降流调节器芯片可以在输入直流电源为恒流源时正常控制输出电压,电流稳定性。(The invention discloses a down regulator chip, which comprises an external packaging structure and an internal circuit, and is characterized in that the internal circuit comprises a Reference voltage source Reference, a constant closing time module COT control, a comparator U1, a comparator U2, a logic AND gate P1 and an RS trigger U4, wherein one end of the Reference voltage source Reference is connected with a pin VDD, the other end of the Reference voltage source Reference is connected with the anode of the input end of the comparator U1, the output end of the comparator U1 is connected with one input end of an adder U5, and the cathode of the input end of the comparator U2 is connected with a pin LD through a resistor.)

1. A droop regulator chip comprising an external package and an internal circuit, wherein the internal circuit comprises a Reference voltage source Reference, a constant off-time module COT control, a comparator U1, a comparator U2, a logic AND gate P1 and an RS flip-flop U4, wherein one end of the Reference voltage source Reference is connected to a pin VDD, the other end of the Reference voltage source Reference is connected to an anode of an input terminal of a comparator U1, an output terminal of the comparator U1 is connected to an input terminal of an adder U5, a cathode of an input terminal of the comparator U2 is connected to a pin LD through a resistor, an output terminal of the comparator U2 is connected to another input terminal of the adder U5, an output terminal of the adder U5 is connected to a pin R of an RS flip-flop U4, a pin S of the RS flip-flop U4 is connected to a constant off-time module COTcontrol, a pin Q of the RS flip-flop U4 is connected to an input terminal of a logic AND gate P1, and another input terminal of the logic AND gate P1 is connected, the output terminal of the logic and gate P1 is connected to the pin DRV and the constant off time block COTcontrol, the negative terminal of the input terminal of the comparator U1 is connected to the positive terminal of the input terminal of the comparator U2 and the pin CS, and the constant off time block COT control is also connected to the pin RT.

2. A buck regulator chip according to claim 1, wherein said pin LD is an analog dimming pin.

3. A buck regulator chip according to claim 1, wherein said pin DPWM is a digital dimming pin.

4. A buck regulator chip according to claim 1, wherein said pin RT is a switching frequency setting pin.

5. A buck regulator chip according to any one of claims 1 to 4, wherein pin DRV is an external MOSFET control pin.

6. The buck regulator chip according to claim 1, wherein the Reference voltage source Reference is controlled by a pin VDD supply pin for high precision voltage regulation, and outputs an internal Reference voltage.

7. A buck regulator chip as claimed in claim 1, wherein a zener diode is also connected to pin VDD.

Technical Field

The invention relates to the technical field of LEDs (light emitting diodes), in particular to a current reduction regulator chip.

Background

A buck regulator is a proposed solution to solve system efficiency, especially efficiency of high power systems, and is particularly widely used in LED dimming circuits, which is a power electronic device that converts dc power into dc power with controllable voltage or current required by a load. The constant direct current voltage is chopped into a series of pulse voltages by the fast on-off control of a power electronic device, the pulse width of the pulse series is changed by controlling the change of the duty ratio so as to realize the adjustment of the average value of the output voltage, and the output voltage is filtered by an output filter to obtain the direct current electric energy with controllable current or voltage on a controlled load.

Most of the existing down-flow regulators are complex in structure and unstable in performance, and the invention provides a down-flow regulator chip which is small in size and stable in performance.

Disclosure of Invention

The present invention is directed to a droop regulator chip to solve the above-mentioned problems of the background art.

In order to achieve the purpose, the invention provides the following technical scheme:

a droop regulator chip includes an external package structure and an internal circuit including a Reference voltage source Reference having one end connected to a pin VDD, the other end connected to a positive terminal of an input terminal of a comparator U1, a comparator U1, a comparator U2, a logic AND gate P1 and an RS flip-flop U4, an output terminal of the Reference voltage source Reference being connected to an input terminal of an adder U1, an output terminal of the comparator U1 being connected to an input terminal of an adder U5, a negative terminal of an input terminal of the comparator U2 being connected to a pin LD via a resistor, an output terminal of the comparator U2 being connected to another input terminal of the adder U5, an output terminal of the adder U5 being connected to a pin R of the RS flip-flop U4, a pin S of the RS flip-flop U4 being connected to the constant off time module COTcontrol, a pin Q of the RS flip-flop U4 being connected to an input terminal of the logic AND gate P1, another input terminal of the logic AND gate P1 being connected to a, the output terminal of the logic and gate P1 is connected to the pin DRV and the constant off time block COTcontrol, the negative terminal of the input terminal of the comparator U1 is connected to the positive terminal of the input terminal of the comparator U2 and the pin CS, and the constant off time block COT control is also connected to the pin RT.

As a further technical scheme of the invention: the pin LD is an analog dimming pin.

As a further technical scheme of the invention: the pin DPWM is a digital dimming pin.

As a further technical scheme of the invention: the pin RT is a switching frequency setting pin.

As a further technical scheme of the invention: the pin DRV is an external MOSFET control pin.

As a further technical scheme of the invention: the Reference voltage source Reference is controlled by a pin VDD power supply pin in a high-precision voltage stabilization mode, and outputs an internal Reference voltage.

As a further technical scheme of the invention: and the pin VDD is also connected with a voltage stabilizing diode.

Compared with the prior art, the invention has the beneficial effects that: the inventive drop regulator chip can normally control output voltage and current stability when the input DC power supply is a constant current source.

Drawings

Fig. 1 is a circuit diagram of an application of the present invention.

Fig. 2 is an internal circuit diagram of the present invention.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.